pipelining
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This document discusses pipelining in microprocessors. It describes how pipelining works by dividing instruction processing into stages - fetch, decode, execute, memory, and write back. This allows subsequent instructions to begin processing before previous instructions have finished, improving processor efficiency. The document provides estimated timing for each stage and notes advantages like quicker execution for large programs, while disadvantages include added hardware and potential pipeline hazards disrupting smooth execution. It then gives examples of how four instructions would progress through each stage in a pipelined versus linear fashion.
pipelining
- 2. Estimated timings for each of the stages: Instruction Fetch 2ns Instruction Decode 1ns Execution 2ns Memory and IO 2ns Write Back 1ns
- 3. Advantages: More efficient use of processor Quicker time of execution of large number of instructions Disadvantages: Pipelining involves adding hardware to the chip Inability to continuously run the pipeline at full speed because of pipeline hazards which disrupt the smooth execution of the pipeline.
- 4. Linear Pipeline Processor Linear pipeline processes a sequence of subtasks with linear precedence At a higher level - Sequence of processors Data flowing in streams from stage S1 to the final stage Sk Control of data flow : synchronous or asynchronous S1 S2 Sk 3
- 5. S1 S2 S3 T1 T1 T1 T2 T2 T2 T3 T3 T4 1 2 3 4 Time (in pipeline cycles) Full pipeline after 4 cycles
- 6. Asynchronous Pipeline Transfers performed when individual processors are ready Handshaking protocol between processors Mainly used in multiprocessor systems with message-passing 5
- 8. Synchronous Pipeline All transfers simultaneous One task or operation enters the pipeline per cycle Processors reservation table : diagonal 4
- 9. A technique used in advanced microprocessors where the microprocessor begins executing a second instruction before the first has been completed. - A Pipeline is a series of stages, where some work is done at each stage. The work is not finished until it has passed through all stages. With pipelining, the computer architecture allows the next instructions to be fetched while the processor is performing arithmetic operations, holding them in a buffer close to the processor until each instruction operation can performed.
- 10. The pipeline is divided into segments and each segment can execute it operation concurrently with the other segments. Once a segment completes an operations, it passes the result to the next segment in the pipeline and fetches the next operations from the preceding segment.
- 11. Instruction 1 Instruction 2 Instruction 3Instruction 4 X X XX Four sample instructions, executed linearly
- 12. Four Pipelined Instructions IF IF IF IF ID ID ID ID EX EX EX EX M M M M W W W W 5 1 1 1
- 13. Instructions Fetch The instruction Fetch (IF) stage is responsible for obtaining the requested instruction from memory. The instruction and the program counter (which is incremented to the next instruction) are stored in the IF/ID pipeline register as temporary storage so that may be used in the next stage at the start of the next clock cycle.
- 14. Instruction Decode The Instruction Decode (ID) stage is responsible for decoding the instruction and sending out the various control lines to the other parts of the processor. The instruction is sent to the control unit where it is decoded and the registers are fetched from the register file.
- 15. Execution The Execution (EX) stage is where any calculations are performed. The main component in this stage is the ALU. The ALU is made up of arithmetic, logic and capabilities.
- 16. Memory and IO The Memory and IO (MEM) stage is responsible for storing and loading values to and from memory. It also responsible for input or output from the processor. If the current instruction is not of Memory or IO type than the result from the ALU is passed through to the write back stage.
- 17. Write Back The Write Back (WB) stage is responsible for writing the result of a calculation, memory access or input into the register file.
- 18. Presentation In Pipelining Submitted to : Preeti mam Submitted by : Pradeep Shrivastava Sudhir Saurav
- 21. Decode Instruction and Calculate Effective Address Fetch Instruction From Memory Branch ? Update PC Empty Pipe Interrupt Handling Fetch Operand From memory Execute Instruction Interrupt YES NO YES NO
- 22. INTRODUCTION Pipelining is technique of decomposing a sequential process into suboperation, with each subprocess being executed in a special dedicated segment that operates concurrently with all other segments. The name “pipeline” implies a flows of information analogous to an industrial assembly line.
- 23. The name “pipeline” implies a flow of information analogous to an industrial assembly line. It is characteristic of pipelines that several computation can be in progress in distinct at the same time. Each subtask can be processed independently on a different machine. The pipelining design provides a way to start a new task before an old one has been completed.
- 24. F 1 E 1 F 2 E 2 F 3 E 3 I1 I2 I3 (a) Sequential execution Instruction fetch unit Exelution unit Interstage buffer B1 (b) Hardware organization Time F1 E1 F2 E2 F3 E3 I1 I2 I3 Instruction (c) Pipelined execution Clock cycle 1 2 3 4 Time Fetch + Execution
- 25. pipelining processing: Perform arithmetic operation (Ai*Bi)+(Ci*Di) with a stream of number. A specify pipeline configuration to carry out the task. Register in the pipeline for i=1 through 6. It consist of seven registers that receive new data with every clock pulse ,two multipliers and one adder circuits .
- 26. R1 R2 R3 R4 MULTIPLIER MULTIPLIER R5 R6 ADDER R7 Stage 1 Stage 2 Stage 3 Ai Bi Ci Di