![32
ASCII
Dec Hex Char Dec Hex Char Dec Hex Char Dec Hex Char
0 00 NUL 32 20 SP 64 40 @ 96 60 ‘
1 01 SOH 33 21 ! 65 41 A 97 61 a
2 02 STX 34 22 " 66 42 B 98 62 b
3 03 ETX 35 23 # 67 43 C 99 63 c
4 04 EOT 36 24 $ 68 44 D 100 64 d
5 05 ENQ 37 25 % 69 45 E 101 65 e
6 06 ACK 38 26 & 70 46 F 102 66 f
7 07 BEL 39 27 ’ 71 47 G 103 67 g
8 08 BS 40 28 ( 72 48 H 104 68 h
9 09 HT 41 29 ) 73 49 I 105 69 i
10 0A LF 42 2A * 74 4A J 106 6A j
11 0B VT 43 2B + 75 4B K 107 6B k
12 0C FF 44 2C , 76 4C L 108 6C l
13 0D CR 45 2D - 77 4D M 109 6D m
14 0E SO 46 2E . 78 4E N 110 6E n
15 0F SI 47 2F / 79 4F O 111 6F o
16 10 DLE 48 30 0 80 50 P 112 70 p
17 11 DC1 49 31 1 81 51 Q 113 71 q
18 12 DC2 50 32 2 82 52 R 114 72 r
19 13 DC3 51 33 3 83 53 S 115 73 s
20 14 DC4 52 34 4 84 54 T 116 74 t
21 15 NAK 53 35 5 85 55 U 117 75 u
22 16 SYN 54 36 6 86 56 V 118 76 v
23 17 ETB 55 37 7 87 57 W 119 77 w
24 18 CAN 56 38 8 88 58 X 120 78 x
25 19 EM 57 39 9 89 59 Y 121 79 y
26 1A SUB 58 3A : 90 5A Z 122 7A z
27 1B ESC 59 3B ; 91 5B [ 123 7B {
28 1C FS 60 3C < 92 5C 124 7C |
29 1D GS 61 3D = 93 5D ] 125 7D }
American
Standard
Code for
Information
Interchange
Encoding 128 characters](https://image.slidesharecdn.com/chapter02datarepresentation-241103163118-94cffc0c/85/Chapter_02_Data_Representation-Yifeng-Zhu-32-320.jpg)
![ASCII
33
Memory
Address
Memory
Content
Letter
str + 12 0x00 0
str + 11 0x79 y
str + 10 0x6C l
str + 9 0x62 b
str + 8 0x6D m
str + 7 0x65 e
str + 6 0x73 s
str + 5 0x73 s
str + 4 0x41 A
str + 3 0x20 space
str + 2 0x4D M
str + 1 0x52 R
str 0x41 A
char str[13] = “ARM Assembly”;
//The length has to be at least 13
// even though it has 12 letters.The
// NULL terminator should be included.](https://image.slidesharecdn.com/chapter02datarepresentation-241103163118-94cffc0c/85/Chapter_02_Data_Representation-Yifeng-Zhu-33-320.jpg)
![Find out String Length
35
Pointer dereference operator *
int strlen (char *pStr){
int i = 0;
// loop until pStr[i] is
NULL
while( pStr[i] )
i++;
return i;
}
Array subscript operator [ ]
int strlen (char *pStr){
int i = 0;
// loop until *pStr is NULL
while( *pStr ) {
i++;
pStr++;
}
return i;
}
Stings are terminated with a null character (NUL,ASCII value 0x00)](https://image.slidesharecdn.com/chapter02datarepresentation-241103163118-94cffc0c/85/Chapter_02_Data_Representation-Yifeng-Zhu-35-320.jpg)
![Convert to Upper Case
36
Pointer dereference operator *
void toUpper(char *pStr){
for(char *p = pStr; *p; ++p){
if(*p >= ’a’ && *p <= ’z’)
*p -= ‘a’ – ‘A’;
//or: *p -= 32;
}
}
Array subscript operator [ ]
void toUpper(char *pStr){
char c = pStr[0];
for(int i = 0; c; i++, c =
pStr[i];) {
if(c >= ’a’ && c <= ’z’)
pStr[i] -= ‘a’ – ‘A’;
// or: pStr[i] -= 32;
}
}
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A
a b c d e f g h i j k l m n o p q r s t u v w x y z
61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A
‘a’ – ‘A’ = 0x61 – 0x41 = 0x20 = 32](https://image.slidesharecdn.com/chapter02datarepresentation-241103163118-94cffc0c/85/Chapter_02_Data_Representation-Yifeng-Zhu-36-320.jpg)
Chapter_02_Data_Representation Yifeng Zhu
- 1. Dr. Yifeng Zhu Electrical and Computer Engineering University of Maine Spring 2018 Embedded Systems with ARM Cortex-M Microcontrollers in Assembly Language and C Chapter 2 Data Representation 1
- 2. Bit, Byte, Half-word, Word, Double-Word 2
- 3. Binary, Octal, Decimal and Hex 3 Decimal Binary Octal Hex 0 0000 00 0x0 1 0001 01 0x1 2 0010 02 0x2 3 0011 03 0x3 4 0100 04 0x4 5 0101 05 0x5 6 0110 06 0x6 7 0111 07 0x7 8 1000 010 0x8 9 1001 011 0x9 10 1010 012 0xA 11 1011 013 0xB 12 1100 014 0xC 13 1101 015 0xD 14 1110 016 0xE 15 1111 017 0xF
- 4. Magic 32-bit Numbers 4 Used as a special pattern for debug Used as a special pattern of memory values during allocation and de- allocation 0xDEADBEEF Dead Beef 0xBADDCAFE Bad Cafe 0xFEE1DEAD Feel Dead 0x8BADF00D Ate Bad Food 0xBAADF00D Bad Food 0xDEADC0DE Dead Code 0xFACEB00C Facebook 0xDEADD00D Deade Dude
- 5. Unsigned Integers 5 𝟏𝟎𝟏𝟏𝟐=𝟏×𝟐𝟑 +𝟎×𝟐𝟐 +𝟏×𝟐𝟏 +𝟏×𝟐𝟎 Convert from Binary to Decimal: Five-bit binary code
- 6. Unsigned Integers 6 Convert Decimal to Binary 5210 = 1101002 Example 1 3210 = 1000002 Example 2
- 7. Carry/borrow flag bit for unsigned numbers 7 • When adding two unsigned numbers in an n-bit system, a carry occurs if the result is larger than the maximum unsigned integer that can be represented (i.e. ). • When subtracting two unsigned numbers, borrow occurs if the result is negative, smaller than the smallest unsigned integer that can be represented (i.e. 0). • On ARM Cortex-M3 processors, the carry flag and the borrow flag are physically the same flag bit in the status register. • For an unsigned subtraction, Carry = NOT Borrow
- 8. Carry/borrow flag bit for unsigned numbers 8 16 00000 0 1 2 3 4 5 6 7 8 01000 00001 00010 00011 00100 00101 00110 00111 9 10 11 12 13 14 15 01001 01010 01011 01100 01101 01110 01111 24 25 26 27 28 29 30 31 11001 11010 11011 11100 11101 11110 11111 10000 17 18 19 20 21 22 23 11000 10001 10010 10011 10100 10101 10110 10111 Carry +6 28 + 6 A carry occurs when adding 28 and 6 If the traverse crosses the boundary between 0 and , the carry flag is set on addition and is cleared on subtraction. • Carry flag = 1, indicating carry has occurred on unsigned addition. • Carry flag is 1 because the result crosses the boundary between 31 and 0. 1 1 1 0 0 0 0 1 1 0 + 1 0 0 0 1 0 1 1 1 0 0 Carry 5-bit result Extra bit is discarded. 28 6 + 2
- 9. Carry/borrow flag bit for unsigned numbers 9 16 00000 0 1 2 3 4 5 6 7 8 01000 00001 00010 00011 00100 00101 00110 00111 9 10 11 12 13 14 15 01001 01010 01011 01100 01101 01110 01111 24 25 26 27 28 29 30 31 11001 11010 11011 11100 11101 11110 11111 10000 17 18 19 20 21 22 23 11000 10001 10010 10011 10100 10101 10110 10111 Carry -5 3 - 5 A borrow occurs when subtracting 5 from 3. If the traverse crosses the boundary between 0 and , the carry flag is set on addition and is cleared on subtraction. • Carry flag = 0, indicating borrow has occurred on unsigned subtraction. • For subtraction, carry = NOT borrow. 0 0 0 1 1 0 0 1 0 1 - 1 1 1 1 0 1 1 1 0 0 Borrow 5-bit result 3 5 - 30
- 10. 10 Three ways to represent signed binary integers: Signed magnitude One’s complement () Two’s complement () Signed Integer Representation Overview Sign-and-Magnitude One’s Complement Two’s Complement Range Zero Two zeroes () Two zeroes () One zero Unique Numbers
- 11. 11 Example: in a 5-bit system +710 = 001112 -710 = 101112 Two ways to represent zero +010 = 000002 -010 = 100002 Not used in modern systems Hardware complexity Two zeros Signed Integers Method 1: Signed magnitude Sign-and-Magnitude: • The most significant bit is the sign. • The rest bits are magnitude.
- 12. 12 Signed Integers Method 2: One’s Complement One’s Complement (): Example: in a 5-bit system +710 = 001112 -710 = 110002 The one's complement representation of a negative binary number is the bitwise NOT of its positive counterpart. +710 + (-710) = 001112 + 110002 = 111112 = 25 - 1
- 13. 13 Signed Integers Method 3: Two’s Complement Two’s Complement (): TC of a negative number can be obtained by the bitwise NOT of its positive counterpart plus one. Binary Decimal Original number 0b00011 3 Step 1: Invert every bit 0b11100 Step 2: Add 1 + 0b00001 Two’s complement 0b11101 -3 Example 1: TC(3)
- 14. 14 Signed Integers Method 3: Two’s Complement Two’s Complement (TC) TC of a negative number can be obtained by the bitwise NOT of its positive counterpart plus one. Example 2: TC(-3) Binary Decimal Original number 0b11101 -3 Step 1: Invert every bit 0b00010 Step 2: Add 1 + 0b00001 Two’s complement 0b00011 3
- 15. Comparison 15 00000/ 10000 0 1 2 3 4 5 6 7 8 01000 00001 00010 00011 00100 00101 00110 00111 9 10 11 12 13 14 15 01001 01010 01011 01100 01101 01110 01111 -8 -7 -6 -5 -4 -3 -2 -1 10111 10110 10101 10100 10011 10010 10001 -15 -14 -13 -12 -11 -10 -9 11000 11111 11110 11101 11100 11011 11010 11001 00000/ 11111 0 1 2 3 4 5 6 7 8 01000 00001 00010 00011 00100 00101 00110 00111 9 10 11 12 13 14 15 01001 01010 01011 01100 01101 01110 01111 -8 -7 -6 -5 -4 -3 -2 -1 11000 11001 11010 11011 11100 11101 11110 -15 -14 -13 -12 -11 -10 -9 10111 10000 10001 10010 10011 10100 10101 10110 -16 00000 0 1 2 3 4 5 6 7 8 01000 00001 00010 00011 00100 00101 00110 00111 9 10 11 12 13 14 15 01001 01010 01011 01100 01101 01110 01111 -8 -7 -6 -5 -4 -3 -2 -1 11001 11010 11011 11100 11101 11110 11111 10000 -15 -14 -13 -12 -11 -10 -9 11000 10001 10010 10011 10100 10101 10110 10111 One’s complement representation Negative = invert all bits of a positive Two’s Complement representation TC = invert all bits, then plus 1 Signed magnitude representation 0 = positive 1 = negative
- 16. Overflow flag for signed numbers 16 When adding signed numbers represented in two’s complement, overflow occurs only in two scenarios: 1. adding two positive numbers but getting a non-positive result, or 2. adding two negative numbers but yielding a non-negative result. Similarly, when subtracting signed numbers, overflow occurs in two scenarios: 1. subtracting a positive number from a negative number but getting a positive result, or 2. subtracting a negative number from a positive number but producing a negative result. Overflow cannot occur when adding operands with different signs or when subtracting operands with the same signs.
- 17. Overflow bit flag for signed numbers 17 -16 00000 0 1 2 3 4 5 6 7 8 01000 00001 00010 00011 00100 00101 00110 00111 9 10 11 12 13 14 15 01001 01010 01011 01100 01101 01110 01111 -8 -7 -6 -5 -4 -3 -2 -1 11001 11010 11011 11100 11101 11110 11111 10000 -15 -14 -13 -12 -11 -10 -9 11000 10001 10010 10011 10100 10101 10110 10111 Overflow +5 An overflow occurs when adding two positive numbers and getting a negative result. 1. On addition, overflow occurs if when adding two positives. 2. Overflow never occurs when adding two numbers with different signs.
- 18. Overflow bit flag for signed numbers 18 -16 00000 0 1 2 3 4 5 6 7 8 01000 00001 00010 00011 00100 00101 00110 00111 9 10 11 12 13 14 15 01001 01010 01011 01100 01101 01110 01111 -8 -7 -6 -5 -4 -3 -2 -1 11001 11010 11011 11100 11101 11110 11111 10000 -15 -14 -13 -12 -11 -10 -9 11000 10001 10010 10011 10100 10101 10110 10111 Overflow -7 An overflow occurs when adding two negative numbers and getting a positive result. On addition, overflow occurs if when adding two negatives.
- 19. Signed or Unsigned 19 CPU does not know the answer at all. Therefore the hardware sets up both the carry flag and the overflow flag. It is software’s (programmers’/compilers’) responsibility to interpret the flags. a = 0b10000 b = 0b10000 c = a + b Are a and b signed or unsigned numbers?
- 20. Signed or unsigned 20 Whether the carry flag or the overflow flag should be used depends on the programmer’s intention. When programming in high-level languages such as C, the compiler automatically chooses to use the carry or overflow flag based on how this integer is declared in source code (“int” or “unsigned int”).
- 21. Signed or Unsigned 21 a = 0b10000 b = 0b10000 c = a + b Are a and b signed or unsigned numbers? uint a; uint b; … c = a + b … C Program Check the carry flag!
- 22. Signed or Unsigned 22 a = 0b10000 b = 0b10000 c = a + b Are a and b signed or unsigned numbers? int a; int b; … c = a + b … C Program Check the overflow flag!
- 23. 23 Signed Integer Representation Method 3: Two’s Complement Expression Result Carry? Overflow? Correct Result? 0100 + 0010 0110 0100 + 0110 1010 1100 + 1110 1010 1100 + 1010 0110 Assume a four-bit system:
- 24. 24 Signed Integer Representation Method 3: Two’s Complement Expression Result Carry? Overflow? Correct Result? 0100 + 0010 0110 No No Yes 0100 + 0110 1010 No Yes No 1100 + 1110 1010 Yes No Yes 1100 + 1010 0110 Yes Yes No Assume a four-bit system:
- 25. Why use Two’s Complement 25 Operation Are signed and unsigned operations the same? Addition Yes Subtraction Yes Multiplication Yes if the product is required to keep the same number of bits as operands Division No Two’s complement simplifies hardware
- 26. Adding two signed integers: (-9) + 6 26 -9 6 -3 01001 10110 10111 flip +1 9 -9 00010 00011 flip +1 3 Two’s Complement 1 0 1 1 1 0 0 1 1 0 1 1 1 0 1 Simple Hardware Adder 23 6 29 + Two’s Complement Counterpart
- 27. Subtracting two signed integers: (-9) - 6 27 -9 6 -15 01001 10110 10111 flip +1 9 -9 Two’s Complement 1 0 1 1 1 0 0 1 1 0 Simple Hardware Subtractor 23 6 17 - 01111 10000 10001 flip +1 15 -15 1 0 0 0 1
- 28. Two’s Complement Simplifies Hardware Implementation 28 In two’s complement, the same hardware works correctly for both signed and unsigned addition/subtraction. If the product is required to keep the same number of bits as operands, unsigned multiplication hardware works correctly for signed numbers. However, this is not true for division.
- 29. 29 Condition Codes 29 C is set upon an unsigned addition if the answer is wrong C is cleared upon an unsigned subtract if the answer is wrong V is set upon a signed addition or subtraction if the answer is wrong Why do we care about these bits? Bit Name Meaning after add or sub N negative result is negative Z zero result is zero V overflow signed overflow C carry unsigned overflow
- 30. Formal Representation for Addition 30 R = X +Y When adding two 32-bit integers X andY, the flags are N = R31 Z is set if R is zero. C is set if the result is incorrect for an unsigned addition V is set if the result is incorrect for a signed addition.
- 31. Formal Representation for Subtraction 31 R = X -Y When subtracting two 32-bit integers X andY, the flags are N = R31 Z is set if R is zero. C is clear if the result is incorrect for an unsigned subtraction V is set if the result is incorrect for an signed subtraction.
- 32. 32 ASCII Dec Hex Char Dec Hex Char Dec Hex Char Dec Hex Char 0 00 NUL 32 20 SP 64 40 @ 96 60 ‘ 1 01 SOH 33 21 ! 65 41 A 97 61 a 2 02 STX 34 22 " 66 42 B 98 62 b 3 03 ETX 35 23 # 67 43 C 99 63 c 4 04 EOT 36 24 $ 68 44 D 100 64 d 5 05 ENQ 37 25 % 69 45 E 101 65 e 6 06 ACK 38 26 & 70 46 F 102 66 f 7 07 BEL 39 27 ’ 71 47 G 103 67 g 8 08 BS 40 28 ( 72 48 H 104 68 h 9 09 HT 41 29 ) 73 49 I 105 69 i 10 0A LF 42 2A * 74 4A J 106 6A j 11 0B VT 43 2B + 75 4B K 107 6B k 12 0C FF 44 2C , 76 4C L 108 6C l 13 0D CR 45 2D - 77 4D M 109 6D m 14 0E SO 46 2E . 78 4E N 110 6E n 15 0F SI 47 2F / 79 4F O 111 6F o 16 10 DLE 48 30 0 80 50 P 112 70 p 17 11 DC1 49 31 1 81 51 Q 113 71 q 18 12 DC2 50 32 2 82 52 R 114 72 r 19 13 DC3 51 33 3 83 53 S 115 73 s 20 14 DC4 52 34 4 84 54 T 116 74 t 21 15 NAK 53 35 5 85 55 U 117 75 u 22 16 SYN 54 36 6 86 56 V 118 76 v 23 17 ETB 55 37 7 87 57 W 119 77 w 24 18 CAN 56 38 8 88 58 X 120 78 x 25 19 EM 57 39 9 89 59 Y 121 79 y 26 1A SUB 58 3A : 90 5A Z 122 7A z 27 1B ESC 59 3B ; 91 5B [ 123 7B { 28 1C FS 60 3C < 92 5C 124 7C | 29 1D GS 61 3D = 93 5D ] 125 7D } American Standard Code for Information Interchange Encoding 128 characters
- 33. ASCII 33 Memory Address Memory Content Letter str + 12 0x00 0 str + 11 0x79 y str + 10 0x6C l str + 9 0x62 b str + 8 0x6D m str + 7 0x65 e str + 6 0x73 s str + 5 0x73 s str + 4 0x41 A str + 3 0x20 space str + 2 0x4D M str + 1 0x52 R str 0x41 A char str[13] = “ARM Assembly”; //The length has to be at least 13 // even though it has 12 letters.The // NULL terminator should be included.
- 34. String Comparison 34 Strings are compared based on their ASCII values “j” < “jar” < “jargon” < “jargonize” “CAT” < “Cat” < “DOG” < “Dog” < “cat” < “dog” “12” < “123” < “2”< “AB” < “Ab” < “ab” < “abc”
- 35. Find out String Length 35 Pointer dereference operator * int strlen (char *pStr){ int i = 0; // loop until pStr[i] is NULL while( pStr[i] ) i++; return i; } Array subscript operator [ ] int strlen (char *pStr){ int i = 0; // loop until *pStr is NULL while( *pStr ) { i++; pStr++; } return i; } Stings are terminated with a null character (NUL,ASCII value 0x00)
- 36. Convert to Upper Case 36 Pointer dereference operator * void toUpper(char *pStr){ for(char *p = pStr; *p; ++p){ if(*p >= ’a’ && *p <= ’z’) *p -= ‘a’ – ‘A’; //or: *p -= 32; } } Array subscript operator [ ] void toUpper(char *pStr){ char c = pStr[0]; for(int i = 0; c; i++, c = pStr[i];) { if(c >= ’a’ && c <= ’z’) pStr[i] -= ‘a’ – ‘A’; // or: pStr[i] -= 32; } } A B C D E F G H I J K L M N O P Q R S T U V W X Y Z 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A a b c d e f g h i j k l m n o p q r s t u v w x y z 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A ‘a’ – ‘A’ = 0x61 – 0x41 = 0x20 = 32
Editor's Notes
- #8: For unsigned numbers, the carry flag is set when adding two numbers and the result is larger than the maximum that can represented. For subtraction, the borrow bit is set when the result is positive, representing no borrowing occurs. The borrow bit is cleared when the result is negative. On the ARM processor, the carry bit and borrow bit are the same flag bit in the status register.
- #9: For unsigned numbers, the carry flag is set when adding two numbers and the result is larger than the maximum that can represented. For subtraction, the borrow bit is set when the result is positive, representing no borrowing occurs. The borrow bit is cleared when the result is negative. On the ARM processor, the carry bit and borrow bit are the same flag bit in the status register.
- #17: For signed numbers represented in two’s complement, an overflow occurs only in two scenarios: Add two positive numbers and get a negative result Add two negative numbers and get a positive result
- #18: For signed numbers represented in two’s complement, an overflow occurs only in two scenarios: Add two positive numbers and get a negative result Add two negative numbers and get a positive result
- #25: Why do we use two’s complement? {{Pause=0.5}} One of the advantages is that two’s complement can simplify the hardware implementation of arithmetic functions. If signed integers are represented in two’s complement, the hardware can ignore the sign of operands for addition or subtraction. If the product is required to keep the same number of bits as operands, the multiplication hardware can also ignore the sign of operands. This property of two’s complement simplifies the hardware design for addition, subtraction and multiplication. Note that this property does not hold true for division.
- #26: {{Pause=1}} We will use a very simple example to show that, the hardware adder for adding unsigned numbers, also works correctly for adding signed numbers. {{Pause=0.5}} Suppose we are adding negative nine and six. {{Pause=0.5}} These two signed numbers are represented in two’s complement in computers. {{Pause=0.5}} Specifically, we can obtain the two’s complement representation of negative nine by flipping all bits and adding one. {{Pause=0.5}} The two’s complement of a positive number is itself. {{Pause=0.5}} Let’s see what will happen if the hardware treats these two inputs as unsigned numbers. If these binary bits represent unsigned numbers, they are 23 and 6, respectively. Therefore, the hardware adds 23 and 6, and produces 29, in decimal, {{Pause=0.3}} or one, one, one, zero, one, in binary. {{Pause=0.5}} If the output represents a signed integer in two’s complement, it actually represents negative 3. This can be proved by inverting all the bits and adding one. The result, negative three, is exactly the sum of the original signed inputs. {{Pause=0.5}} This example shows that, without any modification, the hardware adder designed for adding unsigned numbers, works correctly for adding signed numbers.
- #27: {{Pause=1}} Similarly, the same subtraction hardware works correctly for both signed and unsigned subtraction, even though the sign of input operands is not examined. {{Pause=0.3}} This example subtracts 6 from negative 9. The hardware ignores the sign of the inputs, and subtracts 6 from 23. The result is 17, in decimal, {{Pause=0.3}} or one, zero, zero, zero, one, in binary. If the result represents a signed integer in two’s complement, then the result is negative 15. This is exactly the result of subtracting the original signed integers.