CMOS inverter static Characteristics class

1
CMOS
Digital Integrated
Circuits
Analysis and Design
Chapter 5
MOS Inverters:
Static Characteristics

2
Introduction
• Positive logic convention
– “1” represents high voltage of
VDD
– “0” represents low voltage of 0
• The inverter threshold voltage,
Vth
– The input voltage,
0<Vin<VthBoutput VDD
– The input voltage,
Vth<Vin<VDDBoutput 0

3
General circuit structure of an nMOS inverter
• The driver transistor
– The input voltage
Vin=VGS
– The output voltage
Vout=VDS
– The source and the
substrate are ground,
VSB=0
• The load device
– Terminal current IL,
terminal voltage VL

4
Voltage transfer characteristic (VTC)
• The VTC describing Vout as a function of Vin under DC condition
• Very low voltage level
– Vout=VOH
– nMOS off, no conducting current, voltage drop across the load is very
small, the output voltage is high
• As Vin increases
– The driver transistor starts conducting,
the output voltage starts to decrease
– The critical voltage point, dVout/dVin=-1
• The input low voltage VIL
• The input high voltage VIH
• Determining the noise margins
• Further increase Vin
– Output low voltage VOL, when the input
voltage is equal to VOH
– The inverter threshold voltage Vth
• Define as the point where Vin=Vout

5
Noise immunity and noise margin
• NML=VIL-VOL
• NMH=VOH-VIH
• The transition region, uncertain
region

6
Power and area consideration
• The DC power dissipation
– The product of its power supply voltage and the
amount of current down from the power supply during
steady state or in standby mode
– PDC=VDDIDC=(VDD/2)[IDC(Vin=low)+IDC(Vin=high)]
– In deep submicron technologies
• Subthreshold current Bmore power consumption
• The chip area
– To reduce the area of the MOS transistor
• The gate area of the MOS transistor
• The product of W and L

7
Resistive-load inverter
• Operation mode
– Vin<VT0, cut off
• No current, no voltage drop
across the load resistor
• Vout=VDD
– VT0≤Vin<Vout+VT0, saturation
• Initially, VDS>Vin-VT0
•
• With Vin↑B Vout↓
– Vin≥Vout+VT0, linear
• The output voltage
continues to decrease
•
( )2
0
2
T
in
n
R V
V
k
I −
⋅
=
( )
[ ]
2
0
2
2
out
out
T
in
n
R V
V
V
V
k
I −
⋅
−
⋅
⋅
=

8
Calculation of VOH, VOL
• Calculation of VOH
– Vout=VDD-RLIR
– When Vin is low ⇒ID=IR=0 ⇒VOH=VDD
• Calculation of VOL
– Assume the input voltage is equal to VOH
– Vin-VT0≥Vout ⇒ linear region
–
( )
[ ]
L
n
DD
L
n
T
DD
L
n
T
DD
L
DD
L
n
L
L
n
T
DD
L
L
L
T
DD
n
L
OL
DD
L
out
DD
R
R
k
V
R
k
V
V
R
k
V
V
V
V
R
k
V
R
k
V
V
V
V
V
V
V
k
R
V
V
R
V
V
I
2
1
1
0
2
1
2
2
2
I
I
i.e.
node,
output
for the
KCL
Using
2
0
0
0
0
0
2
0
2
0
0
0
D
R
−








+
−
−
+
−
=
=
⋅
+
⋅








+
−
⋅
−
−
⋅
−
⋅
⋅
=
−
=
−
=

9
Calculation of VIL, and VIH
( )
( ) ( ) ( )
( )
[ ]
( )
( ) ( ) ( )
[ ]
L
n
L
n
DD
T
IH
L
n
DD
IH
in
out
out
out
T
L
n
out
T
n
L
n
out
T
IH
out
T
in
n
L
in
out
out
in
out
T
in
n
in
out
L
out
out
T
in
n
L
out
DD
L
n
T
L
n
T
L
n
DD
IL
in
out
L
n
T
IL
T
in
n
L
T
in
n
in
out
L
T
in
n
R
k
R
k
V
V
V
R
k
V
V
V
V
V
V
V
R
k
V
V
k
R
k
V
V
V
V
V
V
k
R
dV
dV
V
dV
dV
V
V
k
dV
dV
R
V
V
V
V
k
R
-V
V
R
k
VDD
V
R
k
V
R
k
V
V
V
V
R
k
V
V
V
V
k
R
V
V
k
dV
dV
R
V
V
k
1
3
8
3
2
)
(
1
2
2
2
R
V
-
V
riables
unknown va
the
determine
To
1
2
2
1
1
1
2
2
2
1
2
2
region
linear
,
V
-
V
V
1
-
to
equal
is
slope
he
at which t
VTC
on the
points
voltage
two
the
of
larger
the
is
V
2
1
1
2
)
(
1
1
1
1
2
R
V
-
V
region
saturation
,
V
-
V
V
-1
/dV
dV
i.e.
1.
-
to
equal
becomes
VTC
the
of
slope
he
at which t
age
input volt
two
the
of
smaller
the
is
V
,
definition
By
0
2
0
0
L
out
DD
0
0
0
2
0
TO
in
out
IH
2
0
0
0
0
0
2
0
L
out
DD
T0
in
out
in
out
IL
−
⋅
+
=
⋅
=
=






−
⋅








−
−
+
⋅
⋅
=
−
+
=
+
−
⋅
−
⋅
=
−
⋅
−






⋅
−
⋅
−
⋅
⋅
=
⋅
−
−
⋅
−
⋅
⋅
=
<
−
=








−
+
⋅
−
=
=
+
=
−
⋅
=
−
⋅
−
⇒
−
⋅
=
⋅
−
−
⋅
=
>
=

10
VTC for different knRL
• The term knRL plays an important role in determining the shape of
the voltage transfer characteristic
• knRL appears as a critical parameter in expressions for VOL, VIL, and
VIH
• knRL can be adjusted by circuit designer
• VOH is determine primarily by the power supply voltage, VDD
• The adjustment of VOL receives primarily attention than VIL, VIH
• Larger knRL ⇒VOL becomes smaller, larger transition slope

12
Power consumption
• The average power consumption
– When input low, VOL
• The driver cut-off, no steady-state current flow, DC
power consumption is zero
– When input high, VOH
• Both driver MOSFET and the load resistor conduct
a nonzero current
• The output voltage VOL, so the current ID=IR=(VDD-
VOL)/RL
–
L
OL
DD
DD
average
DC
R
V
V
V
P
−
⋅
=
2
)
(

13
Chip area
• The chip area depend on two
parameters
– The W/L ratio of the driver
transistor
• Gate area WxL
– The value of the resistor RL
• Diffused resistor
– Sheet resistance 20 to 100Ω/□
– Very large length-to-width rations
to achieve resistor values on the
order if tens to hundreds of kΩ
• Ploysilicon resistor
– Doped polysilicon (for gate of the
transistor), Rs~20 to 40 Ω/□
– Undoped polysilicon, Rs Rs~10M
Ω/□
– The resistance value can not be
controlled very accurately B large
variation of the VTC
– Low power static random access
memory (SRAM)

15
Inverters with n-type MOSFET load
• The resistive-load inverter
– The large area occupied by the load resistor
• The main advantage of using a MOSFET as
the load device
– Smaller silicon area occupied by the transistor
– Better overall performance
• Enhancement-load nMOS inverter
– The saturated enhancement-load inverter
• A single voltage supply
• A relative simple fabrication process
• VOH=VDD-VT,load
– The linear enhancement-type load
• VOH=VDD
• Higher noise margins
• Two separate power supply voltage (drawback)
– Both type suffer from relatively high stand-by
(DC) power dissipation
• Not used in any large-scale digital applications

16
Depletion-load nMOS inverter
• Slightly more complicated
– Channel implant to adjust the
threshold voltage
• Advantages
– Sharp VTC transition better
noise margins
– Single power supply
– Smaller overall layout area
– Reduce standby (leakage)
current
• The circuit diagram
– Consisting
• A nonlinear load resistor,
depletion MOSFET, VT0,load<0
• A nonideal switch (driver) ,
enhancement MOSFET,
VT0,load>0
– The load transistor
• VGS=0, always on
–
( )
( )
[ ] ( )
( ) ( ) ( )
[ ]
2
,
,
,
2
,
,
2
,
,
,
,
0
,
2
2
region
linear
in the
operates
r
transisto
load
The
level,
tage
output vol
larger
For
2
2
region
saturation
in
is
r
transisto
load
The
small,
is
tage
output vol
When the
2
2
out
DD
out
DD
out
load
T
load
n
load
D
T,load
DD
out
out
load
T
load
n
out
load
T
load
n
load
D
T,load
DD
out
F
out
F
load
T
load
T
V
V
V
V
V
V
k
I
V
V
V
V
V
k
V
V
k
I
V
V
V
V
r
V
V
−
−
−
⋅
⋅
=
+
>
⋅
=
−
⋅
=
+
<
−
+
+
= φ
φ

17
Calculation of VOH, VOL, VIL, ViH
( ) ( ) ( )
[ ]
( )
[ ] ( )
[ ]
( ) ( )
2
,
2
0
0
2
,
2
0
2
,
,
,
0
2
2
2
region
saturation
load
region,
linear
driver
assume,
low
output
the
calculate
To
0
2
2
current,
drain
zero
region
linear
load
off,
driver
an
smaller th
is
When
OL
load
T
driver
load
T
OH
T
OH
OL
OL
load
T
load
OL
OL
T
OH
driver
DD
OH
in
OL
OH
DD
OH
DD
OH
load
T
load
n
load
D
DD
OH
T
in
V
V
k
k
V
V
V
V
V
V
V
k
V
V
V
V
k
V
V
V
V
V
V
V
V
V
V
k
I
V
V
V
V
⋅








−
−
−
−
=
−
⋅
=
−
⋅
−
⋅
⋅
→
→
⇒
=
=
=
−
−
−
⋅
⋅
=
=
→
→
⇒

18
Calculation of VOH, VOL, VIL, VIH
( ) ( ) ( ) ( )
[ ]
( )
( ) ( )
( )
( )
[ ]
out
load
T
DD
out
driver
load
T
IL
in
out
out
load
T
out
DD
out
load
T
out
DD
out
load
T
out
load
T
load
T
in
driver
in
out
DD
out
DD
out
load
T
load
T
in
driver
IL
V
V
V
V
k
k
V
V
-
/dV
dV
dV
dV
V
V
dV
dV
V
V
dV
dV
V
V
k
V
V
k
V
V
V
V
V
V
V
k
V
V
k
V
,
0
,
,
,
,
0
2
,
2
0
1
sbustitute
2
2
2
2
respect to
with
sides
both
al
Differenti
2
2
2
region
linear
load
the
region,
saturation
driver
The
of
n
Calculatio
+
−
⋅








+
=
=






















−
−
−








−
−
+








−
⋅
=
−
⋅
−
−
−
⋅
⋅
=
−
⋅
⇒
⇒
( )
[ ] ( )
[ ]
( ) ( )
[ ]
( )
[ ]
out
F
out
load
T
out
load
T
out
load
T
driver
load
out
T
IH
in
out
in
out
out
load
T
out
load
T
load
in
out
out
in
out
T
in
out
driver
in
out
load
T
load
out
out
T
in
driver
IH
V
dV
dV
dV
dV
V
V
k
k
V
V
V
-
/dV
dV
dV
dV
dV
dV
V
V
k
dV
dV
V
dV
dV
V
V
V
k
V
V
V
k
V
V
V
V
k
V
+
=








⋅
−
⋅








+
+
=
=








⋅








⋅
−
⋅
=














−








+
+
⋅
−
⋅
=
−
⋅
−
⋅
⋅
⇒
⇒
φ
γ
2
2
2
1
sbustitute
respect to
with
sides
both
al
Differenti
2
2
2
region
saturation
load
the
region,
linear
driver
The
of
n
Calculatio
,
,
,
0
,
,
0
2
,
2
0

19
VTC of depletion load inverters
• The general shape of the
inverter VTC, and ultimately,
the noise margins, are
determined by
– The threshold voltage of the
driver and the load
• Set by the fabrication process
– The driver-to-load ratio
kR=(kdriver/kload)
• Determined by the (W/L)
ratios of the driver and the
load transistor
• One important observation
– A sharp VTC transition and
larger noise margins can be
obtained with relative small
driver-to-load ratios
• Much small area occupation

20
Design of depletion-load inverters
• The designable parameters in the inverter circuit are
– The power supply voltage VDD
• Being determined by other external constrains
• Determining the output level high VOH=VDD
– The threshold voltages of the driver and the load
• Being determined by the fabrication process
– The (W/L) ratios of the driver and the load transistor
•
• Since the channel doping densities are not equal
– The channel electron mobilities are not equal
– K’n,load≠k’n,driver
• The actual sizes of the driver and the load transistor are
usually determined by other constrains
– The current-drive capability
– The steady state power dissipation
– The transient switching speed
( )
( )
load
driver
R
load
load
n
driver
driver
n
R
OL
OL
T
OH
OL
load
T
load
driver
R
L
W
L
W
k
L
W
k
L
W
k
k
V
V
V
V
V
V
k
k
k












=






⋅
′






⋅
′
=
−
−
=
= ,
,
2
,
,
2
0
2
,

21
Power consideration
• The steady-state DC power consumption
– Input voltage low
• The driver off, Vout=VOH=VDD
• No DC power dissipation
– Input voltage high, Vin≈VDD and Vout=VOL
•
( ) ( )
[ ]
( )
[ ]
( )
[ ]2
,
2
0
2
,
2
2
50%
other
the
during
high
and
time
operation
50%
low
level
age
input volt
the
Assume
2
2
2
OL
load
T
load
DD
DC
OL
OL
T
OH
driver
OL
load
T
load
DD
in
DC
V
V
k
V
P
V
V
V
V
K
V
V
K
V
V
I
−
⋅
⋅
=
−
⋅
−
⋅
⋅
=
−
⋅
=
=

22
Area consideration
• Figure (a)
– Sharing a common n+
diffusion region
• Saving silicon area
– Depletion mode
• Threshold voltage adjusted by
a donor implant into the
channel
– (W/L)driver>(W/L)load, ratio
about 4
• Figure (b)
– Buried contact
• Reducing area
• For connecting the gate and
the source of the load
transistor
– The polysilicon gate of the
depletion mode transistor
makes a direct ohmic with
the n+ source diffusion
– The contact window on the
intermediate diffusion area
can be omitted

26
CMOS inverter
• Complementary push-pull
– High input BnMOS driver, pMOS load
– Low input BpMOS driver, nMOS load
• Two important advantages
– Virtually negligible steady state power dissipation
– VTC exhibits a full output voltage swing between 0V and VDD, transition is very
sharp
• Latch up problem
– Formation of two parasitic bipolar transistors
– Preventing
• Guard rings

27
Circuit operation
• Region A: Vin<VT0,n
– nMOS off, pMOS on B ID,n=ID,p=0,
Vout=VOH=VDD
• Region B: Vin>VT0,n
– nMOS saturation, the output
voltagedecreases
– The critical voltage VIL, (dVout/dVin)=-1
is located within this region
– As the output further decreases
BpMOS enter saturation, boundary
of region C
• Region C:
– If nMOS saturation B VDS,n≥VGS,n-
VT0,n ⇔ Vout ≥Vin-VT0,n
– If pMOS saturation B VDS,n≤VGS,p-
VT0,p ⇔ Vout ≤Vin-VT0,p
– Both of these conditions for device
saturation are illustrated graphically as
shaded areas
• Region D: Vout<Vin-VT0,p
– The criical point VIH
• Region E: Vin>VDD+VT0,p
– Vout=VOL=0

28
Circuit operation
• The nMOS and the pMOS transistors an be
seen as nearly ideal switches
– The current drawn from the power supply in both
these steady state points region A and region E
• Nearly equal to zero
• The only current Breverse biased S, D leakage current
– The CMOS inverter can drive any load
• Interconnect capacitance
• Fan-out logic gates
• Either by supplying current to the load, or by sinking current
from the load

29
The steady-state input-out voltage characteristics

30
Calculation of VIL, VIH
( ) ( )
[ ]
( ) ( ) ( ) ( )
[ ]
( ) ( ) ( ) ( )
( ) ( )
p
n
R
R
n
T
R
DD
p
T
out
IL
DD
p
T
IL
out
p
n
T
IL
n
in
out
IL
in
in
out
DD
out
DD
out
in
out
p
T
DD
in
p
n
T
in
n
DD
out
DD
out
p
T
DD
in
p
n
T
in
n
p
DS
P
DS
p
T
p
GS
p
n
T
n
GS
n
k
k
k
k
V
k
V
V
V
V
V
V
V
V
k
V
V
k
-
)
/dV
and (dV
V
V
dV
dV
V
V
V
V
dV
dV
V
V
V
k
V
V
k
V
V
V
V
V
V
V
k
V
V
k
V
V
V
V
k
V
V
k
=
+
+
−
+
=
−
+
−
⋅
=
−
⋅
=
=














⋅
−
−
−
+








⋅
−
−
⋅
=
−
⋅
−
−
−
⋅
−
−
⋅
⋅
=
−
⋅
−
⋅
−
⋅
⋅
=
−
⋅
where
1
2
2
1
ng
substituti
2
2
2
2
2
2
linear
pMOS
,
saturation
nMOS
,
0
,
0
,
0
.
0
,
0
,
0
2
,
0
2
,
0
2
,
,
,
0
,
2
,
0
,
( )
[ ] ( )
( )
[ ] ( )
( ) ( )
( ) ( )
( )
R
n
T
out
R
p
T
DD
IH
p
T
DD
IH
p
out
n
T
IH
n
in
out
IH
in
p
T
DD
in
p
in
out
out
out
in
out
n
T
in
n
p
T
DD
in
p
out
out
n
T
in
n
p
T
p
GS
p
n
DS
n
DS
n
T
n
GS
n
k
V
V
k
V
V
V
V
V
V
k
V
V
V
k
-
)
/dV
(dV
V
V
V
V
V
k
dV
dV
V
V
dV
dV
V
V
k
V
V
V
k
V
V
V
V
k
V
V
k
V
V
V
V
k
+
+
⋅
+
+
=
−
−
⋅
=
+
+
−
⋅
=
=
−
−
⋅
=














⋅
−
+








⋅
−
⋅
−
−
⋅
=
−
⋅
−
⋅
⋅
−
⋅
=
−
⋅
−
⋅
⋅
1
2
2
1
and
substiting
2
2
2
2
2
2
saturation
pMOS
linear,
nMOS
,
0
,
0
,
0
,
0
,
0
,
0
2
,
0
2
,
0
2
,
0
,
2
,
,
,
0
,

31
Calculation of Vth
( ) ( )
( ) ( )
( )
( )
( ) ( )
,p
T
th
,n
T
th
th
in
R
p
T
DD
R
n
T
th
p
T
DD
n
p
n
T
n
p
p
T
DD
in
p
n
T
in
n
p
T
p
GS
p
n
T
n
GS
n
out
in
out
in
th
-V
V
-V
V
V
V
k
V
V
k
V
V
V
V
k
k
V
k
k
Vin
V
V
V
k
V
V
k
V
V
k
V
V
k
V
V
V
V
V
0
0
,
0
,
0
,
0
,
0
2
,
0
2
,
0
2
,
0
,
2
,
0
,
and
between
value
any
attain
actually
can
tage
output vol
the
,
If
1
1
1
1
2
2
2
2
mode
saturation
in
are
istor
both trans
,
For
inverter
the
of
e
performanc
DC
the
zing
characteri
parameter
imporant
an
as
emerges
voltage
hreshold
inverter t
the
n
transitio
VTC
sharp
very
and
margins
noise
large
exhibits
inverter
CMOS
the
Since
as
defined
is
voltage
reshold
inveter th
The
=








+
+
⋅
+
=
+
⋅
+
=








+
⋅
−
−
⋅
=
−
⋅
−
⋅
=
−
⋅
=
=
=

32
Threshold voltage
• The Region C of VTC
– Completely vertical
• If the channel length modulation effect is neglected, i.e. if λ=0
– Exhibits a finite slope
• If λ>0
• Fig 5.22 shows the variation of the inversion (switching) threshold
voltage Vth as function of the transconductance ratio kR

33
VTC and power supply current
• If input voltage is either
smaller than VT0,n, or
larger than VDD+VT0,p
– Does not draw any
significant current from the
power supply
– Except for small leakage
current and subthreshold
currents
• During low-to-high and
high-to-low transitions
– Regions B, C, and D
– The current being drawn
from the power source
– Reaching its peak value
when Vin=Vth (both
saturation mode)

34
Design of CMOS inverters
( ) ( )
IL
MH
L
IH
DD
IH
OH
H
IL
OL
IL
L
DD
IH
IL
n
T
DD
IH
n
T
DD
IL
R
,p
T
,n
T
n
p
n
p
p
n
ox
ox
p
p
n
n
p
OX
p
n
OX
n
p
n
inverter
symmertric
p
n
,p
T
,n
T
T
n
T
DD
p
T
VDD
ideal
p
n
DD
ideal
th
n
T
th
th
p
T
DD
p
n
R
th
p
T
DD
n
T
th
R
V
N
NM
V
V
V
V
NM
V
V
V
NM
V
V
V
V
V
V
V
V
V
k
V
V
L
W
L
W
s
V
cm
s
V
cm
L
W
L
W
pMOS
nMOS
, C
t
L
W
L
W
L
W
C
L
W
C
k
k
k
k
V
V
V
V
V
V
k
k
V
V
V
V
V
V
V
k
k
k
V
V
V
V
V
k
=
=
−
=
−
=
=
−
=
=
+
−
⋅
=
+
⋅
=
=
=






≈






⇒
⋅
⋅
≈
=


















⋅






⋅
=






⋅






⋅
=
=








⇒
=
=








+
+
=








⇒
⋅
=








−
+
+
=
=
⇒
−
+
−
=
,
,
2
5
8
1
,
2
3
8
1
1
and
ith
inverter w
CMOS
symmetric
a
For
5
.
2
/
580
/
230
and
for
value
same
the
have
assume
1
setting
by
stics
characteri
output
-
input
symmetric
complely
achieve
can
we
5
.
0
5
.
0
5.73
in
5.74
ng
substituti
s
2
1
as
defined
is
inverter
ideal
an
of
voltage
threshold
switching
The
1
,
0
,
0
0
0
2
2
0
0
0
2
,
0
,
0
,
2
,
0
,
0
,
0
,
0
µ
µ
µ
µ
µ
µ

36
Supply voltage scaling in CMOS inverters
• The static characteristics of the CMOS
inverter allow significant variation of supply
voltage without affecting the functionality of
the basic inverter
• The CMOS inverter will continue to operate
correctly with a supply voltage limit value
–
– Correct inverter operation will be sustained if
at least one of the transistors remains in
conduction, for any given voltage
– The exact shape of the VTC near e limit
value is essentially determined by
subthreshold conduction properties
• If the power supply voltage is reduced
below the sum of the two threshold
– The VTC will contain a region in which none
of the transistors is conducting
– The output voltage level is determine by the
previous state of the output
– The VTC exhibits a hysteresis behavior
p
T
n
T
DD V
V
V ,
0
,
0
min
+
=

37
Power and area consideration
• Power consideration
– DC power dissipation of the circuit is almost negligible
– The drain current
• Source and drain pn junction reverse leakage current
• In short channel leakage current
• Subthreshold current
– However, that the CMOS inverter does conduct a significant amount of current
during a switching event
• Area consideration

CMOS inverter static Characteristics class

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CMOS inverter static Characteristics class