VLSI- Unit II

VLSI Design
Techniques
UNIT II
Inverters and Logic
Gates

VLSI Design Techniques Slide 2
2
Outline
 nMOS and CMOS Inverters
 Stick Diagram
 Inverter Ratio
 DC and Transient Characteristics
 Switching Times
 Super Buffers
 Driving Large Capacitance loads
 CMOS logic Structures
 Transmission gates
 Static CMOS Design
 Dynamic CMOS Design

1 0
0 1
•Inverter : Basic requirement for
producing a complete range of
Logic circuits
R
Vss
R
Vo
VDD

Vdd
Vss
Vo
Vin
R Pull-Up
Pull Down
Basic Inverter: Transistor with source
connected to ground and a load resistor
connected from the drain to the positive
Supply rail
Output is taken from the drain and
control input connected between gate
and ground
Resistors are not easily formed in silicon
- they occupy too much area
Transistors can be used as the pull-up
device

Vdd
Vss
Vo
Vin
D
S
D
S
• Pull-Up is always on – Vgs = 0; depletion
• Pull-Down turns on when Vin > Vt
NMOS Depletion Mode Transistor Pull - Up
• With no current drawn from outputs, Ids
for both transistors is equal
Vt
V0
Vdd
Vi
Non-zero output

Vo
VDD
VDD
Vin
Vinv
• Point where Vo = Vin is called Vinv
Decreasing
Zpu/Zpd
Increasing
Zpu/Zpd
• Transfer Characteristics and Vinv can be shifted by altering ratio
of pull-up to Pull down impedances

NMOS Depletion Mode Inverter
Characteristics
 Dissipation is high since rail to rail current
flows when Vin = Logical 1
 Switching of Output from 1 to 0 begins when
Vin exceeds Vt of pull down device
 When switching the output from 1 to 0, the
pull up device is non-saturated initially and
this presents a lower resistance through
which to charge capacitors (Vds < Vgs – Vt)

NMOS Enhancement Mode Transistor Pull - Up
Vss
Vo
Vin
D
S
D
S
Vdd
Vgg
Vt (pull down)
V0
Vdd
Vt (pull up)
Non zero output
Vin
• Dissipation is high since current flows when Vin = 1
• Vout can never reach Vdd (effect of channel)
• Vgg can be derived from a switching source (i.e. one phase of a clock, so
that dissipation can be significantly reduced
• If Vgg is higher than Vdd, and extra supply rail is required

When cascading logic devices care must be taken
to preserve integrity of logic levels
i.e. design circuit so that Vin = Vout = Vinv
Cascading NMOS Inverters
Determine pull – up to pull-down ratio for driven inverter

Assume equal margins around inverter; Vinv = 0.5 Vdd
Assume both transistors in saturation, therefore: Ids = K (W/L) (Vgs – Vt)2/2
Depletion mode transistor has gate connected to source, i.e. Vgs = 0
Ids = K (Wpu/Lpu) (-Vtd)2/2
Ids = K (Wpd/Lpd) (Vinv – Vt)2/2
Enhancement mode device Vgs = Vinv, therefore
Assume currents are equal through both channels (no current drawn by load)
(Wpd/Lpd) (Vinv – Vt)2 = (Wpu/Lpu) (-Vtd)2
Convention Z = L/W
Vinv = Vt – Vtd / (Zpu/Zpd)1/2
Substitute in typical values Vt = 0.2 Vdd ; Vtd = -0.6 Vdd ; Vinv = 0.5 Vdd
This gives Zpu / Zpd = 4:1 for an nmos inverter directly driven
by another inverter

Vdd Vdd
A B C
Inverter 1 Inverter 2
Vin1 Vout2
Pull-Up to Pull-Down Ratio for an nMOS inverter driven
through 1 or more pass transistors
It is often the case that two inverters are connected via a series of
switches (Pass Transistors)
We are concerned that connection of transistors in series will degrade
the logic levels into
Inverter 2. The driven inverter can be designed to deal with this.
(Zpu/Zpd >= 8/1)

Complimentary Transistor Pull – Up (CMOS)
Vdd
Vss
V
o
Vin
Vout
Vin
Vdd
Vss
Vtn Vtp
Logic 0 Logic 1
P on
N off
Both On
N on
P off

Vout
Vin
Vdd
Vss
Vtn Vtp
P on
N off
Both On
N on
P off
1 2 3 4 5
1: Logic 0 : p on ; n off
5: Logic 1: p off ; n on
2: Vin > Vtn.
Vdsn large – n in saturation
Vdsp small – p in resistive
Small current from Vdd to Vss
4: same as 2 except reversed p and n
3: Both transistors are in saturation
Large instantaneous current flows

CMOS INVERTER CHARACTERISTICS
Current through n-channel pull-down transistor
 2
2
tn
in
n
n V
V
I 


Current through p-channel pull-up transistor
 
 2
2
tp
DD
in
p
p V
V
V
I 




At logic threshold, In = Ip
   
 
   
 
 
tp
DD
tn
p
n
p
n
in
tp
DD
in
tn
in
p
n
tp
DD
in
p
tn
in
n
tp
DD
in
p
tn
in
n
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V





































1
2
2
2
2
2
2
p
n
p
n
tn
tp
DD
in
V
V
V
V








1
If n = p and Vtp = –Vtn
2
DD
in
V
V 
n
n
n
p
p
p
L
W
L
W 


Mobilities are unequal : µn = 2.5 µp
Z = L/W
Zpu/Zpd = 2.5:1 for a symmetrical CMOS
inverter

CMOS Inverter Characteristics
 No current flow for either logical 1 or logical 0 inputs
 Full logical 1 and 0 levels are presented at the
output
 For devices of similar dimensions the p – channel is
slower than the n – channel device

DC Characteristics of a CMOS Inverter
 A complementary CMOS
inverter consists of a p-type
and an n-type device
connected in series.
 The DC transfer characteristics
of the inverter are a function of
the output voltage (Vout) with
respect to the input voltage
(Vin).
 The MOS device first order
Shockley equations describing the
transistors in cut-off, linear and
saturation modes can be used to
generate the transfer characteristics
of a CMOS inverter.
 Plotting these equations for both
the n- and p-type devices produces
the traces below.

DC Characteristics of a CMOS Inverter
 The DC transfer characteristic curve is determined by plotting the
common points of Vgs intersection after taking the absolute value
of the p-device IV curves, reflecting them about the x-axis and
superimposing them on the n-device IV curves.
 We basically solve for Vin(n-type) = Vin(p-type) and Ids(n-type)=Ids(p-type)
 The desired switching point must be designed to be 50 % of
magnitude of the supply voltage i.e. VDD/2.
 Analysis of the superimposed n-type and p-type IV curves results
in five regions in which the inverter operates.

CMOS Inverter DC Characteristics

CMOS Inverter Transfer
Characteristics
nMOS in sat
pMOS in sat
Vout =Vin-Vtp
A
C
B
D E
Vtp Vtn
VDD
0
VDD/2 VDD+Vtp VDD
Both in sat
Output
Voltage
Vout =Vin-Vtn

 Region A occurs when
– The n-device is in cut-off (Idsn =0).
– p-device is in linear region,
– Idsn = 0 therefore -Idsp = 0
– Vdsp = Vout – VDD, but Vdsp =0 leading to an output of Vout =
VDD.
 Region B occurs when the condition Vtn leq Vin le VDD/2 is met.
– Here p-device is in its non-saturated region Vds neq 0.
– n-device is in saturation
 Saturation current Idsn is obtained by setting Vgs = Vin resulting
in the equation:
 2
2
tn
un
n
dsn V
V
I 


0 in tn
V V
 
CMOS Inverter Transfer
Characteristics

CMOS Inverter Transfer Characteristics
 In region B Idsp is governed by voltages Vgs and Vds described by:
 Region C has that both n- and p-devices are in saturation.
 Saturation currents for the two devices are:
   
DD
out
ds
DD
in
gs V
V
V
V
V
V 


 and
   
    
 







 
























 






2
2
:
that
Recall
2
2
2
2
DD
out
DD
out
tp
DD
in
p
tn
in
n
dsp
dsn
DD
out
DD
out
tp
DD
in
p
dsp
V
V
V
V
V
V
V
V
V
I
I
V
V
V
V
V
V
V
I



 
  tn
in
tn
in
n
dsn
DD
tp
in
tp
DD
in
p
dsp
V
V
V
V
I
V
V
V
V
V
V
I









;
2
AND
;
2
2
2



CMOS Inverter Transfer Characteristics
 Region D is defined by the inequality
 p-device is in saturation while n-device is in its non-saturation
region.
 Equating the drain currents allows us to solve for Vout.
tp
DD
in
DD
V
V
V
V



2
 
  tn
in
out
out
tn
in
n
dsn
DD
tp
in
tp
DD
in
p
dsp
V
V
V
V
V
V
I
V
V
V
V
V
V
I
























;
2
AND
;
2
2
2



CMOS Inverter Charateristics
 In Region E the input condition satisfies:
 The p-type device is in cut-off: Idsp=0
 The n-type device is in linear mode
 Vgsp = Vin –VDD and this is a more positive value
compared to Vtp.
 Vout = 0
tp
DD
in V
V
V 


CMOS Inverter Switching
Characteristics
 Define:
– Rise time tr = time required for a node to charge
from the 10% point to 90% point
– Fall time tf = time required for a node to
discharge from 90% to 10% point
– Delay time td = delay from the 50% point on the
input to the 50% point on the output
– Falling delay tdf = delay time with output falling
– Rising delay tdr = delay time with output rising

CMOS Inverter Switching
Characteristics

Pass Transistors
 Use n-transistor as “switches”
 “Threshold problem”
– Transistor switches off when
Vgs < Vt
– VDD input -> VDD-Vt output
 Special gate needed to “restore”
values
IN:
VDD
A:
VDD
OUT:
VDD-Vtn

Transmission Gates
 Complementary transistors - n and p
 No threshold problem
 Cost: extra transistor, extra control input
 Not a perfect conductor!
A
A’
A
A’

Stick Diagrams
 Key idea: "Stick figure cartoon" of a layout
 Useful for planning layout
– relative placement of transistors
– assignment of signals to layers
– connections between cells
– cell hierarchy

Stick Diagrams – Notations
Metal 1
poly
ndiff
pdiff
Can also draw
in shades of
gray/line style.
Similarly for contacts, via, tub etc..

Stick Diagrams – Some rules
Rule 1.
When two or more ‘sticks’ of the same type cross or
touch each other that represents electrical contact.

Rule 2.
When two or more ‘sticks’ of different type cross or
touch each other there is no electrical contact.
(If electrical contact is needed we have to show the connection
explicitly).

Rule 3.
When a poly crosses diffusion it represents a
transistor.
Note: If a contact is shown then it is not a transistor.

Rule 4.
In CMOS a demarcation line is drawn to avoid
touching of p-diff with n-diff. All pMOS must lie on one
side of the line and all nMOS will have to be on the
other side.

Stick Diagrams

How to draw Stick Diagrams

Example - Stick Diagrams
Circuit Diagram. Pull-Down Network
(The easy part!)
Alternatives - Pull-up Network
Complete Stick Diagram

Example - Stick Diagrams

Basic Design Rules
1. Size Rules
2. Separation Rules
3. Overlap Rules
Basic nMOS Design Rules
Diffusion Region Width
Polysilicon Region Width
Diffusion-Diffusion Spacing
Poly-Poly Spacing
Polysilicon Gate Extension
Contact Extension
Metal Width
2
2
3
2
2

3

Size and Separation Rules
Incorrectly and Correctly Formed Channels
Diffusion
Short
Poly
Incorrectly formed
Channel
Correctly formed
Metal
Diffusion Poly

Overlap Rules for Contact cuts
( a ) ( b )

Layout of Basic Devices
 nMOS Inverter
 CMOS Inverter
 nMOS NAND Gate
 CMOS NAND Gate
 nMOS NOR Gate
 CMOS NOR Gate
Complicated devices are constructed by using basic devices

A CMOS Inverter

A CMOS NAND Gate

A CMOS NOR Gate

Additional Fabrication Factors
 Scaling
 Parasitic Effects
 Yield Statistics and Fabrication Costs
 Delay Computation
 Noise and Crosstalk
 Power Dissipation

Mini Summary
 The three types of materials are insulators, conductors and
semiconductors
 A VLSI chip consists of several layers of different materials on
a silicon wafer.
 Each layer is defined by a mask
 VLSI fabrication process patterns each layer using a mask
 Complex VLSI circuits can be developed using basic VLSI
devices
 Design rules must be followed to allow proper fabrication
 Several factors such as scaling, parasitic effects, yield
statistics and fabrication costs, delay computation, noise and
crosstalk and power dissipation play a key role in fabrication
of VLSI chips

Supper Buffer
 Given a large capacitance load Cload
– How many stages are needed to minimize the delay?
– How to size the inverters?
Supper Buffer
Cload
1
2 N
1
Cg Cd Cg 2Cg
Cd 2Cd NCg NCd Cload
Equiv INV
N: number of inverter stages
: optimal stage scale factor

Supper Buffer (Cont.)
where
– Cg: the input capacitance of the first stage inverter.
– Cd: the drain capacitance of the first stage inverter.
– Each inverter is scaled up by a factor of  per
stage.
– Cload = N+1Cg
– All inverters have identical delay of
0(Cd+Cg)/(Cd+Cg) which 0 is per gate delay for
Equiv INV in ring oscillator circuit with load
capacitance = Cg+Cd

CMOS Inverter Driving a Lumped
Capacitance Load
 CMOS Inverter can be viewed as a single transistor
either charging the Cload or discharging the Cload
– Vin is assumed to switch abruptly
– If Vin switches high, the NMOS Tx discharges
Cload while the PMOS Tx turns OFF
– If Vin switches low, the PMOS Tx charges
Cload while the NMOS Tx turns OFF
 Cload is comprised of
– Cgate due to the gate capacitance of receiving
circuits
– Cwire of the interconnect metal
– Cdiffusion of the inverter output junctions
 Transient Response:
– Approximate as a simple RC network where R is
given as an equivalent resistance of the NMOS
and PMOS devices and C is given as the total
lumped Cload capacitance

Delay Time Derivation: NMOS Discharging Cload
 Assume Vin switches abruptly from VOL to VOH (VOL =
0 and VOH = VDD for CMOS)
 We are interested in the delay time for Vout to fall
from VOH to the 50% point, i.e. to the value 0.5 x (VOH
+ VOL), = ½ VDD for CMOS
– For Vout between VOH and VOH – VTN, the NMOS
is in saturation
• Integrate Cload dv = I dt between to and
t1’
• IDS = ½ kn (Vin – VTN)2
• t1’ – to = 2 Cload VTN/kn (VOH – VTN)2
– For Vout between VOH – VTN and VOL, the NMOS
is in the linear region
• Integrate Cload dv = I dt between t1’
and t1
• IDS = kn VDS (VGS – VTN – ½ VDS)

CMOS Technology Logic Circuit
Structures
 Many different logic circuits utilizing CMOS technology have been invented and used in
various applications. These can be divided into three types or families of circuits:
– Complementary Logic
• Standard CMOS
• Clocked CMOS (C2MOS)
• BICMOS (CMOS logic with Bipolar driver)
– Ratio Circuit Logic
• Pseudo-NMOS
• Saturated NMOS Load
• Saturated PMOS Load
• Depletion NMOS Load (E/D)
• Source Follower Pull-up Logic (SFPL)
– Dynamic Logic:
• CMOS Domino Logic
• NP Domino Logic (also called Zipper CMOS)
• NORA Logic
• Cascade voltage Switch Logic (CVSL)
• Sample-Set Differential Logic (SSDL)
• Pass-Transistor Logic

Standard CMOS Logic
 CMOS Complementary Logic Circuits:
– inverter
– 2-input NAND
– 2-NOR showing position of poly
gates
– complex logic gate
[A(B+C)+(DE)]’ showing position
of poly gates by ordering of
device inputs
 Each logic function is duplicated for
both pull-down and pull-up logic tree
– pull-down tree gives the zero
entries of the truth table, i.e.
implements the negative of the
given function Z
– pull-up tree is the dual of the pull-
down tree, i.e. implements the
true logic with each input
negative-going
 Advantages: low power, high noise
margins, design ease, functionality
 Disadvantage: high input capacitance
reduces the ultimate performance

AOI (AND-OR-INVERT) CMOS Gate
 AOI complex CMOS gate can be used to directly implement a sum-of-
products Boolean function
 The pull-down N-tree can be implemented as follows:
– Product terms yield series-connected NMOS transistors
– Sums are denoted by parallel-connected legs
– The complete function must be an inverted representation
 The pull-up P-tree is derived as the dual of the N-tree

OAI (OR-AND-INVERT) CMOS Gate
 An Or-And-Invert (OAI) CMOS gate is similar to the AOI gate except that it is
an implementation of product-of-sums realization of a function
 The N-tree is implemented as follows:
– Each product term is a set of parallel transistors for each input in the term
– All product terms (parallel groups) are put in series
– The complete function is again assumed to be an inverted representation
 The P-tree can be implemented as the dual of the N-tree
 Note: AO and OA gates (non-inverted function representation) can be
implemented directly on the P-tree if inverted inputs are available

Clock-CMOS (C2MOS)
 Static CMOS: the output of a static logic
gate is valid so long as the input value
are valid and the circuit has stabilized
 However, logic delays are due to the
“rippling” through the circuits
– Not reference to any specific time
base
– So on, Clock CMOS, or C2MOS is
proposed
 C2MOS concept: non-overlapping clock
– But in physical signal, the clocks may
overlap slightly during a transition
    0

 t
t 

   
t
V
t DD 
 


Clock signals

C2MOS Networks
 C2MOS is composed of a static logic circuit with tri-state
output network (made up of FETs M1 and M2) that is
controlled by and
– When , both M1 and M2 are active, and become to
a standard static logic gate
– When , both M1 and M2 are cutoff, so the output is
a Hi-Z state
 
1


0


Structure of a C2MOS gate

BICMOS Logic
 BICMOS Logic is typically comprised of CMOS logic feeding a bipolar drive
– 2-input NAND is shown below
 N-tree pull down logic must be inserted twice:
– once in the actual CMOS logic circuit
– again in the base current path for the pull-down NPN transistor (N1 and N2)
 N3 holds the pull-down NPN off when the output is pulling high
 The circuit in (a) contains a VBE drop on the output up-level (VOH = VDD – VBE)
 VOL is a VCEsat which is a few hundred mV above ground
 Feedback provided by the inverter in (b) pulls output VOH all the way to VDD

Pseudo-nMOS
 Adding a single pFET to otherwise nFET-only circuit
produces a logic family that is called pseudo-nMOS
– Less transistor than CMOS
– For N inputs, only requires (N+1) FETs
– Pull-up device: pFET is biased active since the
grounded gate gives VSGp = VDD
– Pull-down device: nFET logic array acts as a large
switch between the output f and ground
– However, since the pFET is always biased on, VOL
can never achieve the ideal value of 0 V
 A simple inverter using pseudo-nMOS
 
   2
2
2
2
2
Tp
DD
p
OL
OL
Tn
DD
n
V
V
V
V
V
V 





     2
2
Tp
DD
n
p
Tn
DD
Tn
DD
OL V
V
V
V
V
V
V 







Pseudo-nMOS inverter
General structure of a
pseudo-nMOS logic gate

Source-Follower Pull-Up Logic,
SFPL
Related to pseudo-nMOS logic
– Improvement: inputs control pMOS pull-up
Inputs fed to parallel source follower
Select ratio of Nload to other transistors
Any input on causes parallel source-follower output to
rise
pMOS pull-up to turn on

Parallel Source Follower For SFPL
b
a
d
c
Nload
parallel source-follower output

SFPL Circuit
b
a
d
c
z

SFPL Nor Gate Operation
1.Any input on causes parallel source-follower output to
rise
2.Causes pMOS pull-up to turn off
3.Allows smaller nMOS pull-down network
4.Reduces output drain capacitance
5.Faster gate
6.Good for high fan-in gates

NMOS Logic Design
 MOS transistors (both PMOS and NMOS) can be
combined with resistive loads to create single
channel logic gates
 The circuit designer is limited to altering circuit
topology and the width-to-length (W/L) ratio since
the other factors are dependent upon processing
parameters

NMOS Inverter with a Resistive Load
 The resistor R is used
to “pull” the output
high
 MS is the switching
transistor used to “pull”
the output low
 The size of R and the
W/L ratio of MS are the
design factors that
need to be chosen

Static Design of the NMOS
Saturated Load Inverter
Schematic for a NMOS
saturated load inverter
Cross-section for a NMOS
saturated load inverter

NMOS Saturated Load Inverter
Design Strategy
 Given VDD, VL, and the power level, find IDD from VDD and
power
 Assume MS off, and find high output voltage level VH
 Use the value of VH for the gate voltage of MS and
calculate (W/L)S of the switching transistor based on the
design values of IDD and VL
 Find (W/L)L (load transistor) based on IDD and VL
 Check the operating region assumptions of MS and ML for
vo = VL
 Verify design with a SPICE simulations

PMOS Logic
 PMOS logic circuits predated NMOS logic circuit, but
were replaced since they operate at slower speeds
Resistive Load Saturated Load Linear Load Depletion-Mode
Load
Pseudo PMOS

Comparison of Load Devices
 The saturated load devices have the poorest fall time
since they have the lowest load current delivery
 The saturated load devices also reach zero current
before the output reaches 2.5 V
 The linear load device is faster than the saturated
load device, but about equal to the resistive load
speed.
 The fastest PLH is for the pseudo NMOS device as a
result of the PMOS device

Dynamic Logic Circuits *
 Dynamic logic is temporary (transient) in that output levels will remain valid only for
a certain period of time
– Static logic retains its output level as long as power is applied
 Dynamic logic is normally done with charging and selectively discharging
capacitance (i.e. capacitive circuit nodes)
– Precharge clock to charge the capacitance
– Evaluate clock to discharge the capacitance depending on condition of logic
inputs
 Advantages over static logic:
– Avoids duplicating logic twice as both N-tree and P-tree, as in standard CMOS
– Typically can be used in very high performance applications
– Very simple sequential memory circuits; amenable to synchronous logic
– High density achievable
– Consumes less power (in some cases)
 Disadvantages compared to static logic:
– Problems with clock synchronization and timing
– Design is more difficult

NMOS Dynamic Logic Basic Circuit
 The basic dynamic logic gate concept is
shown at left (top)
– the pass transistor MP is an NMOS
device, but could also be implemented
with a transmission gate TG
– Cx represents the equivalent capacitance
of the input gate of the second NMOS
device (part of an inverter or logic gate)
as well as the PN junction capacitance of
MP’s drain (source)
– When clock CK goes high, MP is turned
on and allows the input voltage Vin to be
placed on capacitor Cx
• Vin could be a high (“1”) or a low (“0”)
voltage
– When CK goes low, MP is turned off,
trapping the charge on Cx

Dynamic NMOS Logic: Transfer “1”
Event
 Operation for a 1 or a 0:
– If Vin is high (say VOH), then
MP will allow current to flow
into Cx, charging it up to Vdd
– Vtn (assume CK up level is
Vdd)
– If Vin is low (say GND), then
MP will allow current to flow
out of Cx, discharging it to
GND

Dynamic NMOS Logic: Transfer “0”
Event
 Due to leakage from the drain
(source) of MP, Cx can only retain
the charge Q for a given period of
time (called soft node)
– If MP is NMOS, Cx will
discharge to GND
– If MP is PMOS, Cx will
discharge to VDD
– If MP is a TG, Cx could
discharge in either direction

Leakage and Subthreshold Current in
Dynamic Pass Gate
 Charge can leak off the storage capacitor Cx mainly from two sources:
– PN junction leakage of the NMOS drain (source) junction
– Subthreshold current (IOFF) through MP when its gate is down at zero volts
 One can solve for the maximum amount of time t that charge can be retained on Cx using
the differential equation C dv/dt = I, where
– I is the total of the reverse PN junction leakage and the IOFF current
– C is the total load capacitance due to gate, junction, wire, and poly capacitance
– the maximum allowable V in order to preserve the logic “1” level is known
• Typically V ~ Vdd – Vtn – ½ Vdd = ½ Vdd – Vtn
 The minimum frequency of operation can be found from f ~ 1/(2 t)

Dynamic Bootstrapping Technique
 Bootstrapping is a technique that is
sometimes used to charge up a transistor gate
to a voltage higher than Vdd when that
transistor has to drive a line to the full Vdd
 At left is a NMOS bootstrap driver often used
in memory circuits to drive a highly capacitive
word line
 Operation:
– When Vin = high, M1 is on holding Vout
low while M3 charges Vx to Vdd – Vt.
Thus, Cboot is charged to Vdd – Vt – VOL
– When Vin goes low, turning M1 off, M2
starts charging Vout high. If Cboot > Cs,
most of the increase in Vout is “booted” to
Vx, raising the voltage at Vx to well above
Vdd.

Dynamic Latches with a Single Clock
 Dynamic latches eliminate dc feedback leg by storing data on gate capacitance of inverter (or
logic gate) and switching charge in or out with a transmission gate
– Minimum frequency of operation is typically of the order of 50-100 KHz so as not to lose
data due to junction or gate leakage from the node
– Can be clocked at high frequency since very little delay in latch elements
 Examples:
– (a) or (b) show simple transmission gate latch concept
– (c ) tri-state inverter dynamic latch holds data on gate when clk is high
– (d) and (e) dynamic D register

Dynamic Registers with Two Phase Clocks
 Dynamic register with pass gates and two phase
clocking is shown
– Clocks phi1 and phi2 are non-overlapping
– When phi1 is high & phi2 is zero,
• 1st pass gate is closed and D data
charges gate capacitance C1 of 1st
inverter
• 2nd pass gate is open trapping prior
charge on C2
– When phi1 is low and phi2 is high,
• 1st pass gate opens trapping D data on
C1
• 2nd pass gate closes allowing C2 to
charge with inverted D data
 If clock skew or sloppy rise/fall time clock buffers
cause overlap of phi1 and phi2 clocks,
– Both pass gates can be closed at the same
time causing mixing of old and new data and
therefore loss of data integrity!

Two Phase Dynamic Registers (Compact
Form)
 Compact implementation of of two phase
dynamic registers shown at left using a tri-
state buffer form.
– Transmission gate and inverter
integrated into one circuit
– Two versions:
• Pass devices closest to output
• Inverter devices closest to output
 Two phase dynamic registers and logic is
often preferred over single phase because
– Due to finite rise and fall times, the CLK
and CLK’ are not truly non-overlapping
– Clock skew often is a problem due to the
fact that CLK’ is usually generated from
CLK using an inverter circuit and also
due to the practical problem of
distributing clock lines without any skew

Dynamic CMOS Logic Gate
 In dynamic CMOS logic a single clock  can be
used to accomplish both the pre-charge and
evaluation operations
– When  is low, PMOS pre-charge
transistor Mp charges Vout to Vdd, since it
remains in its linear region during final pre-
charge
• During this time the logic inputs A1 …
B2 are active; however, since Me is
off, no charge will be lost from Vout
– When  goes high again, Mp is turned off
and the NMOS evaluate transistor Me is
turned on, allowing for Vout to be
selectively discharged to GND depending
on the logic inputs
• If A1 … B2 inputs are such that a
conducting path exists between Vout
and Me, then Vout will discharge to 0
• Otherwise, Vout remains at Vdd

Dynamic CMOS Logic Circuits
 Dynamic CMOS Logic circuits require a
clock to precharge the output node and
then to pull down the logic tree (assuming
the logic inputs provide a path for current
to flow)
– Precharge Phase: clock is down
turning on the P precharge transistor;
N pull-down transistor is off. Output
capacitance CN charges to Vdd.
– Evaluation Phase: clock goes high
turning on the N pull down transistor
and turning off the P precharge
transistor. If logic inputs are such
that neg Z is true, then output
capacitance CN discharges to
ground.
– No dc current flows during either the
precharge or the evaluate phase.
– Power is dynamic and is given by
P = CN Vdd
2 f  where CN represents
an equivalent total capacitance on
the output, f = clock frequency, 
=logic repetition rate

Cascading Problem in Dynamic CMOS
Logic
 If several stages of the previous CMOS dynamic logic circuit are
cascaded together using the same clock , a problem in evaluation
involving a built-in “race condition” will exist
 Consider the two stage dynamic logic circuit below:
– During pre-charge, both Vout1 and Vout2 are pre-charged to Vdd
– When  goes high to begin evaluate, all inputs at stage 1 require
some finite time to resolve, but during this time charge may
erroneously be discharged from Vout2
– The result is an error in the output of the 2nd stage Vout2

Cascaded Dynamic CMOS Logic Gates:
Evaluate Problem
 With simple cascading of dynamic CMOS
logic stages, a problem arises in the evaluate
cycle:
– The pre-charged high voltage on Node
N2 in stage 2 may be inadvertently
(partially) discharged by logic inputs to
stage 2 which have not yet reached final
correct (low) values from the stage 1
evaluation operation.
– Can not simply cascade dynamic CMOS
logic gates without preventing unwanted
bleeding of charge from pre-charged
nodes
 Possible Solutions:
– two phase clocks
– use of inverters to create Domino Logic
– NP Domino Logic
– Zipper/NORA logic

Domino CMOS Logic
Static inverter serves to buffer the
logic part of the circuit from its
output load
– =0
• X precharges to VDD, and
Vout = 0.
– =1
• X remains high, and Vout
remains low.
• X discharges to 0, and
Vout changes from 0 to 1.

VD
D
nMO
S
Logic
Vout
VD
D
inpu
ts
X
 precharge
evaluate
1
t

Domino CMOS Logic (Cont.)

VDD
nMOS
Logic
inputs
VDD
nMOS
Logic
X1
VDD
nMOS
Logic
X2 X3
t
t
X1
t
precharge
evaluate
t
X2
X3
 evaluate
teval
Max number gates limited:
total propagation delay < teval

Domino CMOS Logic (Cont.)
– The problem in cascading conventional dynamic CMOS occurs
when one or more inputs make a 1 to 0 transition during
evaluation.
– Domino circuits can fix the above problem
• During the evaluation, each buffer output can make at most
one transition (from 0 to 1), and thus each input of all
subsequent logic stages can also make at most one (0 to 1)
transition.
X3

VDD
nMOS
Logic
inputs
VDD
nMOS
Logic
X1
VDD
nMOS
Logic
X2

Domino CMOS Logic
The Limitations
– The static CMOS and domino gates can be used
together.
– The limitation: the number of inverting static
logic stages in cascade must be even, to let the
inputs of next domino stage can have only 0 to 1
transitions during the evaluation.
– Can implement only non-inverting logic
– Due to precharge use, can suffer from charge
sharing during the evaluation which may cause
erroneous outputs.

NP Domino Logic (NORA Logic)
 An elegant solution to the dynamic CMOS logic “erroneous
evaluation” problem is to use NP Domino Logic (also called NORA
logic) as shown below.
– Alternate stages of N logic with stages of P logic
 Inverter outputs can be used to feed other N-blocks from N-blocks,
or to feed other P-blocks from P-blocks.

NORA CMOS Logic (NP-Domino
Logic)
– Advantages
• An Inverter is not required at the output of stages
• Allow pipelined system architecture
– Disadvantages: Also suffer from charge sharing and leakage
VDD VDD VDD

nMOS
Logic
pMOS
Logic
nMOS
Logic
 
to nMOS stage to pMOS stage
nMOS stage
precharge
pMOS stage
pre-discharge
all stages
evaluate
nMOS stage
precharge
pMOS stage
pre-discharge
all stages
evaluate


NORA CMOS Logic (NP-Domino Logic)
Examples
VDD VDD VDD
  
– =L: nMOS precharges to H, and pMOS pre-discharges
to L.
– =L→H: All cascaded nMOS and pMOS logic stages
evaluate one after the other.

Zipper CMOS Dynamic Logic
 Zipper CMOS logic is a scheme for
improving charge leakage and charge
sharing problems
 Pre-charge transistors receive a
slightly modified clock where the clock
pulse (during pre-charge off time)
holds the pre-charge transistor at
weak conduction in order to provide a
trickle pre-charge current during the
evaluation phase
– PMOS pre-charge transistor
gates are held at Vdd - |Vtp|
– NMOS pre-charge transistor
gates are held at Vtn above GND

Cascade Voltage Switch Logic,
CVSL
Requires both true and complement versions of inputs
–Recall that pass-gate logic requires both
true and complement control variables
Uses two, complementary nMOS pull-down networks
Each has a pMOS pull-up transistor
pMOS pull-ups cross-coupled

CVSL Circuit
b
~b
a
~d
c
e
d
~c
~e
~a
f
~f

CVSL Positive Feedback
1.One of the two nMOS pull-down networks
pulls either f or ~f low
2.If f goes low, it turns on the pMOS pull-up transistor for
the ~f totem pole,
3.causing ~f to go high,
4.turning off the pMOS pull-up transistor
for the f totem pole,
5.causing f to go low: positive feedback

CVSL Characteristics
Slower than fully-complementary CMOS logic
– During switching, pMOS pull-up partially on
at same time as nMOS pull-down network
The two nMOS pull-down networks afford
opportunities to minimize logic
– Common sub-expression elimination
– Other optimizations
Can optimize multiple-input Xor

Criteria for Pseudo nMOS Logic
Fully-complementary CMOS logic
– Immune to noise
– Virtually zero static power
– Many stages required for high fan-in functions
Pseudo nMOS logic
– Good for high fan-in Nor function
• ROM
• PLA
• Adder carry look-ahead

Criteria for Clocked CMOS and
Pass-Gate Logic
Clocked CMOS logic
– Mitigates “hot electron” effects
Pass-gate logic
– Fast, if few pass gates in series
– Good for complex functions
– Small area, low power

Criteria for CMOS Domino Logic
Use for high speed or low power
Appreciate that precharge phase
subtracts from cycle time
Run circuit simulations carefully
– Back-annotate from layout
– Include noise effects on power and ground lines

Criteria for
Cascade Voltage Switch Logic, CVSL
Cascade Voltage Switch Logic, CVSL
– Potentially fast
– Large area
– Complex
– Susceptible to noise
Overall rules of thumb
– If gate resembles inverter, it will be fast
– Pass gates, if few stages, will be fast

Remember Cascode Voltage Switch
Logic
Cascode voltage Switch logic
Adv:
• no static power dissipation compared to pseudo-NMOS radioed
circuits
• differential signaling
Disadv:
• potentially large diffusion capacitance (slowing things down)
How can we cut down the diffusion capacitance?

Differential Split-Level Circuits
Adv: The reference voltage (VDD/2+Vt) limits the swing on the
internal diffusion nodes (X) to 0-VDD/2  reduces parasitic delay
Disadv:
• Introduces series resistance does not help the delay much
• Brings static power back into the picture

Sense Amplifiers
Function:
 Senses small differential input signals and magnify them
into larger out signals  reduces delay
 Commonly used in memory in which differential bit lines
have huge capacitances

Sense Amplifiers

Sample Set Differential Logic (SSDL)
During sample, when Ф is low:
• Both the precharge and evaluation transistors are ON 
static current consumed
• One of the internal nodes (X or Xbar) is precharged high;
contention on the other
During set, when Ф is high:
• Precharge and evaluation transistors are OFF
• Sense amplifier turns on pulling the lower of the two nodes to
the ground

CMOS Pass-Transistor Logic: XOR
 The XOR circuit shown at top-left contains
a PMOS pull-up arrangement configured
like a latch
– If XOR is true, the upper internal node
goes high to VDD – VT while the lower
internal node goes low to GND, thus
causing the cross-coupled PMOS load
devices to latch and pull the upper
internal node all the way to VDD.
– If XOR is false, the opposite happens
– The inverters provide both true and
complement outputs

Static v.s. Dynamic
 Static Logic Gates
– Valid logic levels are steady-state operating points
– Outputs are generated in response to input voltage levels
after a certain time delay, and it can preserve its output
levels as long as there is power.
– All gate output nodes have a conducting path to VDD or GND,
except when input changes are occurring.
 Dynamic Logic Gates
– The operation depends on temporary storage of charge in
parasitic node capacitances.
– The stored charge does not remain indefinitely, so must
be updated or refreshed. This requires establishment of an
update or recharge path to the capacitance frequently
enough to preserve valid voltage levels.

Static v.s. Dynamic (Cont..)
 Advantages of Dynamic Logic Gates
– Allow implementation of simple sequential circuits
with memory functions.
– Use of common clock signals throughout the
system enables the synchronization of various
circuit blocks.
– Implementation of complex circuits requires a
smaller silicon area than static circuits.
– Often consumes less dynamic power than static
designs, due to smaller parasitic capacitances.

Dynamic CMOS Logic Circuits
 A dynamic logic gate uses clocking and charge
storage properties of MOSFETs to implement
logic operations
– Provide a synchronized data flow
– Result is valid only for a short period of time
– Less transistors, and may be faster than
static cascades
 Based on the circuit
– The clock drives a complementary pair of
transistors Mn and Mp
– An nFET array between the output node
and ground to perform the logic function
– When , it is called precharge phase
– When , it is called evaluation phase
1


0


Basic dynamic logic gate


VLSI- Unit II

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VLSI- Unit II