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lecture for the Date on 25 and tomorrow _04.ppt

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ArunK950324

The document is a lecture on DC and transient response in CMOS VLSI design, covering topics such as transistor operations, DC response, logic levels, noise margins, and delay estimation. It provides detailed explanations of how transistor size, voltage supply, and operating regions impact performance metrics like current and capacitance. It also includes activities, visual aids, and examples to illustrate key concepts in CMOS inverter behavior and design.

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4: DC and Transient Response Slide 1 CMOS VLSI Design EE466: VLSI Design Lecture 05: DC and transient response – CMOS Inverters
4: DC and Transient Response Slide 2 CMOS VLSI Design Outline  DC Response  Logic Levels and Noise Margins  Transient Response  Delay Estimation
4: DC and Transient Response Slide 3 CMOS VLSI Design Activity 1) If the width of a transistor increases, the current will increase decrease not change 2) If the length of a transistor increases, the current will increase decrease not change 3) If the supply voltage of a chip increases, the maximum transistor current will increase decrease not change 4) If the width of a transistor increases, its gate capacitance will increase decrease not change 5) If the length of a transistor increases, its gate capacitance will increase decrease not change 6) If the supply voltage of a chip increases, the gate capacitance of each transistor will increase decrease not change
4: DC and Transient Response Slide 4 CMOS VLSI Design Activity 1) If the width of a transistor increases, the current will increase decrease not change 2) If the length of a transistor increases, the current will increase decrease not change 3) If the supply voltage of a chip increases, the maximum transistor current will increase decrease not change 4) If the width of a transistor increases, its gate capacitance will increase decrease not change 5) If the length of a transistor increases, its gate capacitance will increase decrease not change 6) If the supply voltage of a chip increases, the gate capacitance of each transistor will increase decrease not change
4: DC and Transient Response Slide 5 CMOS VLSI Design DC Response  DC Response: Vout vs. Vin for a gate  Ex: Inverter – When Vin = 0 -> Vout = VDD – When Vin = VDD -> Vout = 0 – In between, Vout depends on transistor size and current – By KCL, must settle such that Idsn = |Idsp| – We could solve equations – But graphical solution gives more insight Idsn Idsp Vout VDD Vin
4: DC and Transient Response Slide 6 CMOS VLSI Design Transistor Operation  Current depends on region of transistor behavior  For what Vin and Vout are nMOS and pMOS in – Cutoff? – Linear? – Saturation?
4: DC and Transient Response Slide 7 CMOS VLSI Design nMOS Operation Cutoff Linear Saturated Vgsn < Vgsn > Vdsn < Vgsn > Vdsn > Idsn Idsp Vout VDD Vin
4: DC and Transient Response Slide 8 CMOS VLSI Design nMOS Operation Cutoff Linear Saturated Vgsn < Vtn Vgsn > Vtn Vdsn < Vgsn – Vtn Vgsn > Vtn Vdsn > Vgsn – Vtn Idsn Idsp Vout VDD Vin
4: DC and Transient Response Slide 9 CMOS VLSI Design nMOS Operation Cutoff Linear Saturated Vgsn < Vtn Vgsn > Vtn Vdsn < Vgsn – Vtn Vgsn > Vtn Vdsn > Vgsn – Vtn Idsn Idsp Vout VDD Vin Vgsn = Vin Vdsn = Vout
4: DC and Transient Response Slide 10 CMOS VLSI Design nMOS Operation Cutoff Linear Saturated Vgsn < Vtn Vin < Vtn Vgsn > Vtn Vin > Vtn Vdsn < Vgsn – Vtn Vout < Vin - Vtn Vgsn > Vtn Vin > Vtn Vdsn > Vgsn – Vtn Vout > Vin - Vtn Idsn Idsp Vout VDD Vin Vgsn = Vin Vdsn = Vout
4: DC and Transient Response Slide 11 CMOS VLSI Design pMOS Operation Cutoff Linear Saturated Vgsp > Vgsp < Vdsp > Vgsp < Vdsp < Idsn Idsp Vout VDD Vin
4: DC and Transient Response Slide 12 CMOS VLSI Design pMOS Operation Cutoff Linear Saturated Vgsp > Vtp Vgsp < Vtp Vdsp > Vgsp – Vtp Vgsp < Vtp Vdsp < Vgsp – Vtp Idsn Idsp Vout VDD Vin
4: DC and Transient Response Slide 13 CMOS VLSI Design pMOS Operation Cutoff Linear Saturated Vgsp > Vtp Vgsp < Vtp Vdsp > Vgsp – Vtp Vgsp < Vtp Vdsp < Vgsp – Vtp Idsn Idsp Vout VDD Vin Vgsp = Vin - VDD Vdsp = Vout - VDD Vtp < 0
4: DC and Transient Response Slide 14 CMOS VLSI Design pMOS Operation Cutoff Linear Saturated Vgsp > Vtp Vin > VDD + Vtp Vgsp < Vtp Vin < VDD + Vtp Vdsp > Vgsp – Vtp Vout > Vin - Vtp Vgsp < Vtp Vin < VDD + Vtp Vdsp < Vgsp – Vtp Vout < Vin - Vtp Idsn Idsp Vout VDD Vin Vgsp = Vin - VDD Vdsp = Vout - VDD Vtp < 0
4: DC and Transient Response Slide 15 CMOS VLSI Design I-V Characteristics  Make pMOS is wider than nMOS such that n = p Vgsn5 Vgsn4 Vgsn3 Vgsn2 Vgsn1 Vgsp5 Vgsp4 Vgsp3 Vgsp2 Vgsp1 VDD -VDD Vdsn -Vdsp -Idsp Idsn 0
4: DC and Transient Response Slide 16 CMOS VLSI Design Current vs. Vout, Vin Vin5 Vin4 Vin3 Vin2 Vin1 Vin0 Vin1 Vin2 Vin3 Vin4 Idsn, |Idsp| Vout VDD
4: DC and Transient Response Slide 17 CMOS VLSI Design Load Line Analysis Vin5 Vin4 Vin3 Vin2 Vin1 Vin0 Vin1 Vin2 Vin3 Vin4 Idsn, |Idsp| Vout VDD  For a given Vin: – Plot Idsn, Idsp vs. Vout – Vout must be where |currents| are equal in Idsn Idsp Vout VDD Vin
4: DC and Transient Response Slide 18 CMOS VLSI Design Load Line Analysis Vin0 Vin0 Idsn, |Idsp| Vout VDD  Vin = 0
4: DC and Transient Response Slide 19 CMOS VLSI Design Load Line Analysis Vin1 Vin1 Idsn, |Idsp| Vout VDD  Vin = 0.2VDD
4: DC and Transient Response Slide 20 CMOS VLSI Design Load Line Analysis Vin2 Vin2 Idsn, |Idsp| Vout VDD  Vin = 0.4VDD
4: DC and Transient Response Slide 21 CMOS VLSI Design Load Line Analysis Vin3 Vin3 Idsn, |Idsp| Vout VDD  Vin = 0.6VDD
4: DC and Transient Response Slide 22 CMOS VLSI Design Load Line Analysis Vin4 Vin4 Idsn, |Idsp| Vout VDD  Vin = 0.8VDD
4: DC and Transient Response Slide 23 CMOS VLSI Design Load Line Analysis Vin5 Vin0 Vin1 Vin2 Vin3 Vin4 Idsn, |Idsp| Vout VDD  Vin = VDD
4: DC and Transient Response Slide 24 CMOS VLSI Design Load Line Summary Vin5 Vin4 Vin3 Vin2 Vin1 Vin0 Vin1 Vin2 Vin3 Vin4 Idsn, |Idsp| Vout VDD
4: DC and Transient Response Slide 25 CMOS VLSI Design DC Transfer Curve  Transcribe points onto Vin vs. Vout plot Vin5 Vin4 Vin3 Vin2 Vin1 Vin0 Vin1 Vin2 Vin3 Vin4 Vout VDD C Vout 0 Vin VDD VDD A B D E Vtn VDD /2 VDD +Vtp
4: DC and Transient Response Slide 26 CMOS VLSI Design Operating Regions  Revisit transistor operating regions C Vout 0 Vin VDD VDD A B D E Vtn VDD /2 VDD +Vtp Region nMOS pMOS A B C D E
4: DC and Transient Response Slide 27 CMOS VLSI Design Operating Regions  Revisit transistor operating regions C Vout 0 Vin VDD VDD A B D E Vtn VDD /2 VDD +Vtp Region nMOS pMOS A Cutoff Linear B Saturation Linear C Saturation Saturation D Linear Saturation E Linear Cutoff
4: DC and Transient Response Slide 28 CMOS VLSI Design Beta Ratio  If p / n  1, switching point will move from VDD/2  Called skewed gate  Other gates: collapse into equivalent inverter Vout 0 Vin VDD VDD 0.5 1 2 10 p n    0.1 p n   
4: DC and Transient Response Slide 29 CMOS VLSI Design Noise Margins  How much noise can a gate input see before it does not recognize the input? Indeterminate Region NML NMH Input Characteristics Output Characteristics VOH VDD VOL GND VIH VIL Logical High Input Range Logical Low Input Range Logical High Output Range Logical Low Output Range
4: DC and Transient Response Slide 30 CMOS VLSI Design Logic Levels  To maximize noise margins, select logic levels at VDD Vin Vout VDD p/n > 1 Vin Vout 0
4: DC and Transient Response Slide 31 CMOS VLSI Design Logic Levels  To maximize noise margins, select logic levels at – unity gain point of DC transfer characteristic VDD Vin Vout VOH VDD VOL VIL VIH Vtn Unity Gain Points Slope = -1 VDD - |Vtp | p/n > 1 Vin Vout 0
4: DC and Transient Response Slide 32 CMOS VLSI Design Transient Response  DC analysis tells us Vout if Vin is constant  Transient analysis tells us Vout(t) if Vin(t) changes – Requires solving differential equations  Input is usually considered to be a step or ramp – From 0 to VDD or vice versa
4: DC and Transient Response Slide 33 CMOS VLSI Design Inverter Step Response  Ex: find step response of inverter driving load cap 0 ( ) ( ) ) ( o i ut n out V t t t V t V d d t     Vin(t) Vout(t) Cload Idsn(t)
4: DC and Transient Response Slide 34 CMOS VLSI Design Inverter Step Response  Ex: find step response of inverter driving load cap 0 0 ( ) ( ) ( ) ( ) ou DD in t out u t t V d d t t t V t V V t      Vin(t) Vout(t) Cload Idsn(t)
4: DC and Transient Response Slide 35 CMOS VLSI Design Inverter Step Response  Ex: find step response of inverter driving load cap 0 0 ( ( ) ) ( ( ) ) DD D o i D o t n ut u V t u t t V V d d t t V V t t      Vin(t) Vout(t) Cload Idsn(t)
4: DC and Transient Response Slide 36 CMOS VLSI Design Inverter Step Response  Ex: find step response of inverter driving load cap 0 0 ( ) ( ) ( ) ( ( ) ) DD DD loa d ou i d t o n ut sn V V u t t V t t V t V d dt C t I t      0 ( ) DD t out ou ds t DD t n I t V V V V V V t t            Vin(t) Vout(t) Cload Idsn(t)
4: DC and Transient Response Slide 37 CMOS VLSI Design Inverter Step Response  Ex: find step response of inverter driving load cap 0 0 ( ) ( ) ( ) ( ( ) ) DD DD loa d ou i d t o n ut sn V V u t t V t t V t V d dt C t I t        0 2 2 0 2 ) ) ( ( ) ( DD DD t DD out out out out D t n t ds D I V t t V V V V V V V V V t V t V t                         Vin(t) Vout(t) Cload Idsn(t)
4: DC and Transient Response Slide 38 CMOS VLSI Design Inverter Step Response  Ex: find step response of inverter driving load cap 0 0 ( ) ( ) ( ) ( ( ) ) DD DD loa d ou i d t o n ut sn V V u t t V t t V t V d dt C t I t        0 2 2 0 2 ) ) ( ( ) ( DD DD t DD out out out out D t n t ds D I V t t V V V V V V V V V t V t V t                         Vout (t) Vin (t) t0 t Vin(t) Vout(t) Cload Idsn(t)
4: DC and Transient Response Slide 39 CMOS VLSI Design Delay Definitions  tpdr:  tpdf:  tpd:  tr:  tf: fall time
4: DC and Transient Response Slide 40 CMOS VLSI Design Delay Definitions  tpdr: rising propagation delay – From input to rising output crossing VDD/2  tpdf: falling propagation delay – From input to falling output crossing VDD/2  tpd: average propagation delay – tpd = (tpdr + tpdf)/2  tr: rise time – From output crossing 0.2 VDD to 0.8 VDD  tf: fall time – From output crossing 0.8 VDD to 0.2 VDD
4: DC and Transient Response Slide 41 CMOS VLSI Design Delay Definitions  tcdr: rising contamination delay – From input to rising output crossing VDD/2  tcdf: falling contamination delay – From input to falling output crossing VDD/2  tcd: average contamination delay – tpd = (tcdr + tcdf)/2
4: DC and Transient Response Slide 42 CMOS VLSI Design Simulated Inverter Delay  Solving differential equations by hand is too hard  SPICE simulator solves the equations numerically – Uses more accurate I-V models too!  But simulations take time to write (V) 0.0 0.5 1.0 1.5 2.0 t(s) 0.0 200p 400p 600p 800p 1n tpdf = 66ps tpdr = 83ps Vin Vout
4: DC and Transient Response Slide 43 CMOS VLSI Design Delay Estimation  We would like to be able to easily estimate delay – Not as accurate as simulation – But easier to ask “What if?”  The step response usually looks like a 1st order RC response with a decaying exponential.  Use RC delay models to estimate delay – C = total capacitance on output node – Use effective resistance R – So that tpd = RC  Characterize transistors by finding their effective R – Depends on average current as gate switches
4: DC and Transient Response Slide 44 CMOS VLSI Design Effective Resistance  Shockley models have limited value – Not accurate enough for modern transistors – Too complicated for much hand analysis  Simplification: treat transistor as resistor – Replace Ids(Vds, Vgs) with effective resistance R • Ids = Vds/R – R averaged across switching of digital gate  Too inaccurate to predict current at any given time – But good enough to predict RC delay
4: DC and Transient Response Slide 45 CMOS VLSI Design RC Delay Model  Use equivalent circuits for MOS transistors – Ideal switch + capacitance and ON resistance – Unit nMOS has resistance R, capacitance C – Unit pMOS has resistance 2R, capacitance C  Capacitance proportional to width  Resistance inversely proportional to width k g s d g s d kC kC kC R/k k g s d g s d kC kC kC 2R/k
4: DC and Transient Response Slide 46 CMOS VLSI Design RC Values  Capacitance – C = Cg = Cs = Cd = 2 fF/m of gate width – Values similar across many processes  Resistance – R  6 K*m in 0.6um process – Improves with shorter channel lengths  Unit transistors – May refer to minimum contacted device (4/2 ) – Or maybe 1 m wide device – Doesn’t matter as long as you are consistent
4: DC and Transient Response Slide 47 CMOS VLSI Design Inverter Delay Estimate  Estimate the delay of a fanout-of-1 inverter 2 1 A Y 2 1
4: DC and Transient Response Slide 48 CMOS VLSI Design Inverter Delay Estimate  Estimate the delay of a fanout-of-1 inverter C C R 2C 2C R 2 1 A Y C 2C Y 2 1
4: DC and Transient Response Slide 49 CMOS VLSI Design Inverter Delay Estimate  Estimate the delay of a fanout-of-1 inverter C C R 2C 2C R 2 1 A Y C 2C C 2C C 2C R Y 2 1
4: DC and Transient Response Slide 50 CMOS VLSI Design Inverter Delay Estimate  Estimate the delay of a fanout-of-1 inverter C C R 2C 2C R 2 1 A Y C 2C C 2C C 2C R Y 2 1 d = 6RC
4: DC and Transient Response Slide 51 CMOS VLSI Design Example: 3-input NAND  Sketch a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R).
4: DC and Transient Response Slide 52 CMOS VLSI Design Example: 3-input NAND  Sketch a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R).
4: DC and Transient Response Slide 53 CMOS VLSI Design Example: 3-input NAND  Sketch a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R). 3 3 2 2 2 3
4: DC and Transient Response Slide 54 CMOS VLSI Design 3-input NAND Caps  Annotate the 3-input NAND gate with gate and diffusion capacitance. 2 2 2 3 3 3
4: DC and Transient Response Slide 55 CMOS VLSI Design 3-input NAND Caps  Annotate the 3-input NAND gate with gate and diffusion capacitance. 2 2 2 3 3 3 3C 3C 3C 3C 2C 2C 2C 2C 2C 2C 3C 3C 3C 2C 2C 2C
4: DC and Transient Response Slide 56 CMOS VLSI Design 3-input NAND Caps  Annotate the 3-input NAND gate with gate and diffusion capacitance. 9C 3C 3C 3 3 3 2 2 2 5C 5C 5C
4: DC and Transient Response Slide 57 CMOS VLSI Design Elmore Delay  ON transistors look like resistors  Pullup or pulldown network modeled as RC ladder  Elmore delay of RC ladder R1 R2 R3 RN C1 C2 C3 CN     nodes 1 1 1 2 2 1 2 ... ... pd i to source i i N N t R C R C R R C R R R C            
4: DC and Transient Response Slide 58 CMOS VLSI Design Example: 2-input NAND  Estimate worst-case rising and falling delay of 2- input NAND driving h identical gates. h copies 2 2 2 2 B A x Y
4: DC and Transient Response Slide 59 CMOS VLSI Design Example: 2-input NAND  Estimate rising and falling propagation delays of a 2- input NAND driving h identical gates. h copies 6C 2C 2 2 2 2 4hC B A x Y
4: DC and Transient Response Slide 60 CMOS VLSI Design Example: 2-input NAND  Estimate rising and falling propagation delays of a 2- input NAND driving h identical gates. h copies 6C 2C 2 2 2 2 4hC B A x Y R (6+4h)C Y pdr t 
4: DC and Transient Response Slide 61 CMOS VLSI Design Example: 2-input NAND  Estimate rising and falling propagation delays of a 2- input NAND driving h identical gates. h copies 6C 2C 2 2 2 2 4hC B A x Y R (6+4h)C Y   6 4 pdr t h RC  
4: DC and Transient Response Slide 62 CMOS VLSI Design Example: 2-input NAND  Estimate rising and falling propagation delays of a 2- input NAND driving h identical gates. h copies 6C 2C 2 2 2 2 4hC B A x Y
4: DC and Transient Response Slide 63 CMOS VLSI Design Example: 2-input NAND  Estimate rising and falling propagation delays of a 2- input NAND driving h identical gates. h copies 6C 2C 2 2 2 2 4hC B A x Y pdf t  (6+4h)C 2C R/2 R/2 x Y
4: DC and Transient Response Slide 64 CMOS VLSI Design Example: 2-input NAND  Estimate rising and falling propagation delays of a 2- input NAND driving h identical gates. h copies 6C 2C 2 2 2 2 4hC B A x Y          2 2 2 2 6 4 7 4 R R R pdf t C h C h RC           (6+4h)C 2C R/2 R/2 x Y
4: DC and Transient Response Slide 65 CMOS VLSI Design Delay Components  Delay has two parts – Parasitic delay • 6 or 7 RC • Independent of load – Effort delay • 4h RC • Proportional to load capacitance
4: DC and Transient Response Slide 66 CMOS VLSI Design Contamination Delay  Best-case (contamination) delay can be substantially less than propagation delay.  Ex: If both inputs fall simultaneously 6C 2C 2 2 2 2 4hC B A x Y R (6+4h)C Y R   3 2 cdr t h RC  
4: DC and Transient Response Slide 67 CMOS VLSI Design 7C 3C 3C 3 3 3 2 2 2 3C 2C 2C 3C 3C Isolated Contacted Diffusion Merged Uncontacted Diffusion Shared Contacted Diffusion Diffusion Capacitance  we assumed contacted diffusion on every s / d.  Good layout minimizes diffusion area  Ex: NAND3 layout shares one diffusion contact – Reduces output capacitance by 2C – Merged uncontacted diffusion might help too
4: DC and Transient Response Slide 68 CMOS VLSI Design Layout Comparison  Which layout is better? A VDD GND B Y A VDD GND B Y

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lecture for the Date on 25 and tomorrow _04.ppt

  • 1. 4: DC and Transient Response Slide 1 CMOS VLSI Design EE466: VLSI Design Lecture 05: DC and transient response – CMOS Inverters
  • 2. 4: DC and Transient Response Slide 2 CMOS VLSI Design Outline  DC Response  Logic Levels and Noise Margins  Transient Response  Delay Estimation
  • 3. 4: DC and Transient Response Slide 3 CMOS VLSI Design Activity 1) If the width of a transistor increases, the current will increase decrease not change 2) If the length of a transistor increases, the current will increase decrease not change 3) If the supply voltage of a chip increases, the maximum transistor current will increase decrease not change 4) If the width of a transistor increases, its gate capacitance will increase decrease not change 5) If the length of a transistor increases, its gate capacitance will increase decrease not change 6) If the supply voltage of a chip increases, the gate capacitance of each transistor will increase decrease not change
  • 4. 4: DC and Transient Response Slide 4 CMOS VLSI Design Activity 1) If the width of a transistor increases, the current will increase decrease not change 2) If the length of a transistor increases, the current will increase decrease not change 3) If the supply voltage of a chip increases, the maximum transistor current will increase decrease not change 4) If the width of a transistor increases, its gate capacitance will increase decrease not change 5) If the length of a transistor increases, its gate capacitance will increase decrease not change 6) If the supply voltage of a chip increases, the gate capacitance of each transistor will increase decrease not change
  • 5. 4: DC and Transient Response Slide 5 CMOS VLSI Design DC Response  DC Response: Vout vs. Vin for a gate  Ex: Inverter – When Vin = 0 -> Vout = VDD – When Vin = VDD -> Vout = 0 – In between, Vout depends on transistor size and current – By KCL, must settle such that Idsn = |Idsp| – We could solve equations – But graphical solution gives more insight Idsn Idsp Vout VDD Vin
  • 6. 4: DC and Transient Response Slide 6 CMOS VLSI Design Transistor Operation  Current depends on region of transistor behavior  For what Vin and Vout are nMOS and pMOS in – Cutoff? – Linear? – Saturation?
  • 7. 4: DC and Transient Response Slide 7 CMOS VLSI Design nMOS Operation Cutoff Linear Saturated Vgsn < Vgsn > Vdsn < Vgsn > Vdsn > Idsn Idsp Vout VDD Vin
  • 8. 4: DC and Transient Response Slide 8 CMOS VLSI Design nMOS Operation Cutoff Linear Saturated Vgsn < Vtn Vgsn > Vtn Vdsn < Vgsn – Vtn Vgsn > Vtn Vdsn > Vgsn – Vtn Idsn Idsp Vout VDD Vin
  • 9. 4: DC and Transient Response Slide 9 CMOS VLSI Design nMOS Operation Cutoff Linear Saturated Vgsn < Vtn Vgsn > Vtn Vdsn < Vgsn – Vtn Vgsn > Vtn Vdsn > Vgsn – Vtn Idsn Idsp Vout VDD Vin Vgsn = Vin Vdsn = Vout
  • 10. 4: DC and Transient Response Slide 10 CMOS VLSI Design nMOS Operation Cutoff Linear Saturated Vgsn < Vtn Vin < Vtn Vgsn > Vtn Vin > Vtn Vdsn < Vgsn – Vtn Vout < Vin - Vtn Vgsn > Vtn Vin > Vtn Vdsn > Vgsn – Vtn Vout > Vin - Vtn Idsn Idsp Vout VDD Vin Vgsn = Vin Vdsn = Vout
  • 11. 4: DC and Transient Response Slide 11 CMOS VLSI Design pMOS Operation Cutoff Linear Saturated Vgsp > Vgsp < Vdsp > Vgsp < Vdsp < Idsn Idsp Vout VDD Vin
  • 12. 4: DC and Transient Response Slide 12 CMOS VLSI Design pMOS Operation Cutoff Linear Saturated Vgsp > Vtp Vgsp < Vtp Vdsp > Vgsp – Vtp Vgsp < Vtp Vdsp < Vgsp – Vtp Idsn Idsp Vout VDD Vin
  • 13. 4: DC and Transient Response Slide 13 CMOS VLSI Design pMOS Operation Cutoff Linear Saturated Vgsp > Vtp Vgsp < Vtp Vdsp > Vgsp – Vtp Vgsp < Vtp Vdsp < Vgsp – Vtp Idsn Idsp Vout VDD Vin Vgsp = Vin - VDD Vdsp = Vout - VDD Vtp < 0
  • 14. 4: DC and Transient Response Slide 14 CMOS VLSI Design pMOS Operation Cutoff Linear Saturated Vgsp > Vtp Vin > VDD + Vtp Vgsp < Vtp Vin < VDD + Vtp Vdsp > Vgsp – Vtp Vout > Vin - Vtp Vgsp < Vtp Vin < VDD + Vtp Vdsp < Vgsp – Vtp Vout < Vin - Vtp Idsn Idsp Vout VDD Vin Vgsp = Vin - VDD Vdsp = Vout - VDD Vtp < 0
  • 15. 4: DC and Transient Response Slide 15 CMOS VLSI Design I-V Characteristics  Make pMOS is wider than nMOS such that n = p Vgsn5 Vgsn4 Vgsn3 Vgsn2 Vgsn1 Vgsp5 Vgsp4 Vgsp3 Vgsp2 Vgsp1 VDD -VDD Vdsn -Vdsp -Idsp Idsn 0
  • 16. 4: DC and Transient Response Slide 16 CMOS VLSI Design Current vs. Vout, Vin Vin5 Vin4 Vin3 Vin2 Vin1 Vin0 Vin1 Vin2 Vin3 Vin4 Idsn, |Idsp| Vout VDD
  • 17. 4: DC and Transient Response Slide 17 CMOS VLSI Design Load Line Analysis Vin5 Vin4 Vin3 Vin2 Vin1 Vin0 Vin1 Vin2 Vin3 Vin4 Idsn, |Idsp| Vout VDD  For a given Vin: – Plot Idsn, Idsp vs. Vout – Vout must be where |currents| are equal in Idsn Idsp Vout VDD Vin
  • 18. 4: DC and Transient Response Slide 18 CMOS VLSI Design Load Line Analysis Vin0 Vin0 Idsn, |Idsp| Vout VDD  Vin = 0
  • 19. 4: DC and Transient Response Slide 19 CMOS VLSI Design Load Line Analysis Vin1 Vin1 Idsn, |Idsp| Vout VDD  Vin = 0.2VDD
  • 20. 4: DC and Transient Response Slide 20 CMOS VLSI Design Load Line Analysis Vin2 Vin2 Idsn, |Idsp| Vout VDD  Vin = 0.4VDD
  • 21. 4: DC and Transient Response Slide 21 CMOS VLSI Design Load Line Analysis Vin3 Vin3 Idsn, |Idsp| Vout VDD  Vin = 0.6VDD
  • 22. 4: DC and Transient Response Slide 22 CMOS VLSI Design Load Line Analysis Vin4 Vin4 Idsn, |Idsp| Vout VDD  Vin = 0.8VDD
  • 23. 4: DC and Transient Response Slide 23 CMOS VLSI Design Load Line Analysis Vin5 Vin0 Vin1 Vin2 Vin3 Vin4 Idsn, |Idsp| Vout VDD  Vin = VDD
  • 24. 4: DC and Transient Response Slide 24 CMOS VLSI Design Load Line Summary Vin5 Vin4 Vin3 Vin2 Vin1 Vin0 Vin1 Vin2 Vin3 Vin4 Idsn, |Idsp| Vout VDD
  • 25. 4: DC and Transient Response Slide 25 CMOS VLSI Design DC Transfer Curve  Transcribe points onto Vin vs. Vout plot Vin5 Vin4 Vin3 Vin2 Vin1 Vin0 Vin1 Vin2 Vin3 Vin4 Vout VDD C Vout 0 Vin VDD VDD A B D E Vtn VDD /2 VDD +Vtp
  • 26. 4: DC and Transient Response Slide 26 CMOS VLSI Design Operating Regions  Revisit transistor operating regions C Vout 0 Vin VDD VDD A B D E Vtn VDD /2 VDD +Vtp Region nMOS pMOS A B C D E
  • 27. 4: DC and Transient Response Slide 27 CMOS VLSI Design Operating Regions  Revisit transistor operating regions C Vout 0 Vin VDD VDD A B D E Vtn VDD /2 VDD +Vtp Region nMOS pMOS A Cutoff Linear B Saturation Linear C Saturation Saturation D Linear Saturation E Linear Cutoff
  • 28. 4: DC and Transient Response Slide 28 CMOS VLSI Design Beta Ratio  If p / n  1, switching point will move from VDD/2  Called skewed gate  Other gates: collapse into equivalent inverter Vout 0 Vin VDD VDD 0.5 1 2 10 p n    0.1 p n   
  • 29. 4: DC and Transient Response Slide 29 CMOS VLSI Design Noise Margins  How much noise can a gate input see before it does not recognize the input? Indeterminate Region NML NMH Input Characteristics Output Characteristics VOH VDD VOL GND VIH VIL Logical High Input Range Logical Low Input Range Logical High Output Range Logical Low Output Range
  • 30. 4: DC and Transient Response Slide 30 CMOS VLSI Design Logic Levels  To maximize noise margins, select logic levels at VDD Vin Vout VDD p/n > 1 Vin Vout 0
  • 31. 4: DC and Transient Response Slide 31 CMOS VLSI Design Logic Levels  To maximize noise margins, select logic levels at – unity gain point of DC transfer characteristic VDD Vin Vout VOH VDD VOL VIL VIH Vtn Unity Gain Points Slope = -1 VDD - |Vtp | p/n > 1 Vin Vout 0
  • 32. 4: DC and Transient Response Slide 32 CMOS VLSI Design Transient Response  DC analysis tells us Vout if Vin is constant  Transient analysis tells us Vout(t) if Vin(t) changes – Requires solving differential equations  Input is usually considered to be a step or ramp – From 0 to VDD or vice versa
  • 33. 4: DC and Transient Response Slide 33 CMOS VLSI Design Inverter Step Response  Ex: find step response of inverter driving load cap 0 ( ) ( ) ) ( o i ut n out V t t t V t V d d t     Vin(t) Vout(t) Cload Idsn(t)
  • 34. 4: DC and Transient Response Slide 34 CMOS VLSI Design Inverter Step Response  Ex: find step response of inverter driving load cap 0 0 ( ) ( ) ( ) ( ) ou DD in t out u t t V d d t t t V t V V t      Vin(t) Vout(t) Cload Idsn(t)
  • 35. 4: DC and Transient Response Slide 35 CMOS VLSI Design Inverter Step Response  Ex: find step response of inverter driving load cap 0 0 ( ( ) ) ( ( ) ) DD D o i D o t n ut u V t u t t V V d d t t V V t t      Vin(t) Vout(t) Cload Idsn(t)
  • 36. 4: DC and Transient Response Slide 36 CMOS VLSI Design Inverter Step Response  Ex: find step response of inverter driving load cap 0 0 ( ) ( ) ( ) ( ( ) ) DD DD loa d ou i d t o n ut sn V V u t t V t t V t V d dt C t I t      0 ( ) DD t out ou ds t DD t n I t V V V V V V t t            Vin(t) Vout(t) Cload Idsn(t)
  • 37. 4: DC and Transient Response Slide 37 CMOS VLSI Design Inverter Step Response  Ex: find step response of inverter driving load cap 0 0 ( ) ( ) ( ) ( ( ) ) DD DD loa d ou i d t o n ut sn V V u t t V t t V t V d dt C t I t        0 2 2 0 2 ) ) ( ( ) ( DD DD t DD out out out out D t n t ds D I V t t V V V V V V V V V t V t V t                         Vin(t) Vout(t) Cload Idsn(t)
  • 38. 4: DC and Transient Response Slide 38 CMOS VLSI Design Inverter Step Response  Ex: find step response of inverter driving load cap 0 0 ( ) ( ) ( ) ( ( ) ) DD DD loa d ou i d t o n ut sn V V u t t V t t V t V d dt C t I t        0 2 2 0 2 ) ) ( ( ) ( DD DD t DD out out out out D t n t ds D I V t t V V V V V V V V V t V t V t                         Vout (t) Vin (t) t0 t Vin(t) Vout(t) Cload Idsn(t)
  • 39. 4: DC and Transient Response Slide 39 CMOS VLSI Design Delay Definitions  tpdr:  tpdf:  tpd:  tr:  tf: fall time
  • 40. 4: DC and Transient Response Slide 40 CMOS VLSI Design Delay Definitions  tpdr: rising propagation delay – From input to rising output crossing VDD/2  tpdf: falling propagation delay – From input to falling output crossing VDD/2  tpd: average propagation delay – tpd = (tpdr + tpdf)/2  tr: rise time – From output crossing 0.2 VDD to 0.8 VDD  tf: fall time – From output crossing 0.8 VDD to 0.2 VDD
  • 41. 4: DC and Transient Response Slide 41 CMOS VLSI Design Delay Definitions  tcdr: rising contamination delay – From input to rising output crossing VDD/2  tcdf: falling contamination delay – From input to falling output crossing VDD/2  tcd: average contamination delay – tpd = (tcdr + tcdf)/2
  • 42. 4: DC and Transient Response Slide 42 CMOS VLSI Design Simulated Inverter Delay  Solving differential equations by hand is too hard  SPICE simulator solves the equations numerically – Uses more accurate I-V models too!  But simulations take time to write (V) 0.0 0.5 1.0 1.5 2.0 t(s) 0.0 200p 400p 600p 800p 1n tpdf = 66ps tpdr = 83ps Vin Vout
  • 43. 4: DC and Transient Response Slide 43 CMOS VLSI Design Delay Estimation  We would like to be able to easily estimate delay – Not as accurate as simulation – But easier to ask “What if?”  The step response usually looks like a 1st order RC response with a decaying exponential.  Use RC delay models to estimate delay – C = total capacitance on output node – Use effective resistance R – So that tpd = RC  Characterize transistors by finding their effective R – Depends on average current as gate switches
  • 44. 4: DC and Transient Response Slide 44 CMOS VLSI Design Effective Resistance  Shockley models have limited value – Not accurate enough for modern transistors – Too complicated for much hand analysis  Simplification: treat transistor as resistor – Replace Ids(Vds, Vgs) with effective resistance R • Ids = Vds/R – R averaged across switching of digital gate  Too inaccurate to predict current at any given time – But good enough to predict RC delay
  • 45. 4: DC and Transient Response Slide 45 CMOS VLSI Design RC Delay Model  Use equivalent circuits for MOS transistors – Ideal switch + capacitance and ON resistance – Unit nMOS has resistance R, capacitance C – Unit pMOS has resistance 2R, capacitance C  Capacitance proportional to width  Resistance inversely proportional to width k g s d g s d kC kC kC R/k k g s d g s d kC kC kC 2R/k
  • 46. 4: DC and Transient Response Slide 46 CMOS VLSI Design RC Values  Capacitance – C = Cg = Cs = Cd = 2 fF/m of gate width – Values similar across many processes  Resistance – R  6 K*m in 0.6um process – Improves with shorter channel lengths  Unit transistors – May refer to minimum contacted device (4/2 ) – Or maybe 1 m wide device – Doesn’t matter as long as you are consistent
  • 47. 4: DC and Transient Response Slide 47 CMOS VLSI Design Inverter Delay Estimate  Estimate the delay of a fanout-of-1 inverter 2 1 A Y 2 1
  • 48. 4: DC and Transient Response Slide 48 CMOS VLSI Design Inverter Delay Estimate  Estimate the delay of a fanout-of-1 inverter C C R 2C 2C R 2 1 A Y C 2C Y 2 1
  • 49. 4: DC and Transient Response Slide 49 CMOS VLSI Design Inverter Delay Estimate  Estimate the delay of a fanout-of-1 inverter C C R 2C 2C R 2 1 A Y C 2C C 2C C 2C R Y 2 1
  • 50. 4: DC and Transient Response Slide 50 CMOS VLSI Design Inverter Delay Estimate  Estimate the delay of a fanout-of-1 inverter C C R 2C 2C R 2 1 A Y C 2C C 2C C 2C R Y 2 1 d = 6RC
  • 51. 4: DC and Transient Response Slide 51 CMOS VLSI Design Example: 3-input NAND  Sketch a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R).
  • 52. 4: DC and Transient Response Slide 52 CMOS VLSI Design Example: 3-input NAND  Sketch a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R).
  • 53. 4: DC and Transient Response Slide 53 CMOS VLSI Design Example: 3-input NAND  Sketch a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R). 3 3 2 2 2 3
  • 54. 4: DC and Transient Response Slide 54 CMOS VLSI Design 3-input NAND Caps  Annotate the 3-input NAND gate with gate and diffusion capacitance. 2 2 2 3 3 3
  • 55. 4: DC and Transient Response Slide 55 CMOS VLSI Design 3-input NAND Caps  Annotate the 3-input NAND gate with gate and diffusion capacitance. 2 2 2 3 3 3 3C 3C 3C 3C 2C 2C 2C 2C 2C 2C 3C 3C 3C 2C 2C 2C
  • 56. 4: DC and Transient Response Slide 56 CMOS VLSI Design 3-input NAND Caps  Annotate the 3-input NAND gate with gate and diffusion capacitance. 9C 3C 3C 3 3 3 2 2 2 5C 5C 5C
  • 57. 4: DC and Transient Response Slide 57 CMOS VLSI Design Elmore Delay  ON transistors look like resistors  Pullup or pulldown network modeled as RC ladder  Elmore delay of RC ladder R1 R2 R3 RN C1 C2 C3 CN     nodes 1 1 1 2 2 1 2 ... ... pd i to source i i N N t R C R C R R C R R R C            
  • 58. 4: DC and Transient Response Slide 58 CMOS VLSI Design Example: 2-input NAND  Estimate worst-case rising and falling delay of 2- input NAND driving h identical gates. h copies 2 2 2 2 B A x Y
  • 59. 4: DC and Transient Response Slide 59 CMOS VLSI Design Example: 2-input NAND  Estimate rising and falling propagation delays of a 2- input NAND driving h identical gates. h copies 6C 2C 2 2 2 2 4hC B A x Y
  • 60. 4: DC and Transient Response Slide 60 CMOS VLSI Design Example: 2-input NAND  Estimate rising and falling propagation delays of a 2- input NAND driving h identical gates. h copies 6C 2C 2 2 2 2 4hC B A x Y R (6+4h)C Y pdr t 
  • 61. 4: DC and Transient Response Slide 61 CMOS VLSI Design Example: 2-input NAND  Estimate rising and falling propagation delays of a 2- input NAND driving h identical gates. h copies 6C 2C 2 2 2 2 4hC B A x Y R (6+4h)C Y   6 4 pdr t h RC  
  • 62. 4: DC and Transient Response Slide 62 CMOS VLSI Design Example: 2-input NAND  Estimate rising and falling propagation delays of a 2- input NAND driving h identical gates. h copies 6C 2C 2 2 2 2 4hC B A x Y
  • 63. 4: DC and Transient Response Slide 63 CMOS VLSI Design Example: 2-input NAND  Estimate rising and falling propagation delays of a 2- input NAND driving h identical gates. h copies 6C 2C 2 2 2 2 4hC B A x Y pdf t  (6+4h)C 2C R/2 R/2 x Y
  • 64. 4: DC and Transient Response Slide 64 CMOS VLSI Design Example: 2-input NAND  Estimate rising and falling propagation delays of a 2- input NAND driving h identical gates. h copies 6C 2C 2 2 2 2 4hC B A x Y          2 2 2 2 6 4 7 4 R R R pdf t C h C h RC           (6+4h)C 2C R/2 R/2 x Y
  • 65. 4: DC and Transient Response Slide 65 CMOS VLSI Design Delay Components  Delay has two parts – Parasitic delay • 6 or 7 RC • Independent of load – Effort delay • 4h RC • Proportional to load capacitance
  • 66. 4: DC and Transient Response Slide 66 CMOS VLSI Design Contamination Delay  Best-case (contamination) delay can be substantially less than propagation delay.  Ex: If both inputs fall simultaneously 6C 2C 2 2 2 2 4hC B A x Y R (6+4h)C Y R   3 2 cdr t h RC  
  • 67. 4: DC and Transient Response Slide 67 CMOS VLSI Design 7C 3C 3C 3 3 3 2 2 2 3C 2C 2C 3C 3C Isolated Contacted Diffusion Merged Uncontacted Diffusion Shared Contacted Diffusion Diffusion Capacitance  we assumed contacted diffusion on every s / d.  Good layout minimizes diffusion area  Ex: NAND3 layout shares one diffusion contact – Reduces output capacitance by 2C – Merged uncontacted diffusion might help too
  • 68. 4: DC and Transient Response Slide 68 CMOS VLSI Design Layout Comparison  Which layout is better? A VDD GND B Y A VDD GND B Y