lect00_introducao of Very large scale Integration Tech .ppt
- 1. Introduction to CMOS VLSI Design Introduction Manoel E. de Lima David Harris - Harvey Mudd College
- 2. CMOS VLSI Design 0: Introduction Slide 2 Introduction Integrated circuits: many transistors on one chip. Very Large Scale Integration (VLSI): very many Complementary Metal Oxide Semiconductor – Fast, cheap, low power transistors Today: How to build your own simple CMOS chip – CMOS transistors – Building logic gates from transistors – Transistor layout and fabrication Rest of the course: How to build a good CMOS chip
- 3. CMOS VLSI Design WHY VLSI DESIGN? Money, technology, civilization
- 4. CMOS VLSI Design Annual Sales 1018 transistors manufactured in 2003 100 million for every human on the planet 0 50 100 150 200 1982 1984 1986 1988 1990 1992 1994 1996 1998 2000 2002 Year Global Semiconductor Billings (Billions of US$)
- 5. CMOS VLSI Design Digression: Silicon Semiconductors Modern electronic chips are built mostly on silicon substrates Silicon is a Group IV semiconducting material crystal lattice: covalent bonds hold each atom to four neighbors Si Si Si Si Si Si Si Si Si http://onlineheavytheory.net/silicon.html
- 6. CMOS VLSI Design 0: Introduction Slide 6 Silicon Lattice Transistors are built on a silicon substrate Silicon is a Group IV material Forms crystal lattice with bonds to four neighbors Si Si Si Si Si Si Si Si Si
- 7. CMOS VLSI Design 0: Introduction Slide 7 Dopants Silicon is a semiconductor Pure silicon has no free carriers and conducts poorly Adding dopants increases the conductivity Group V: extra electron (n-type) Group III: missing electron, called hole (p-type) As Si Si Si Si Si Si Si Si B Si Si Si Si Si Si Si Si - + + -
- 8. CMOS VLSI Design 0: Introduction Slide 8 p-n Junctions A junction between p-type and n-type semiconductor forms a diode. Current flows only in one direction p-type n-type anode cathode
- 9. CMOS VLSI Design A Brief History Invention of the Transistor Vacuum tubes ruled in first half of 20th century Large, expensive, power-hungry, unreliable 1947: first point contact transistor (3 terminal devices) Shockley, Bardeen and Brattain at Bell Labs
- 10. CMOS VLSI Design A Brief History, contd.. 1958: First integrated circuit Flip-flop using two transistors Built by Jack Kilby (Nobel Laureate) at Texas Instruments Robert Noyce (Fairchild) is also considered as a co-inventor smithsonianchips.si.edu/ augarten/ Kilby’s IC
- 11. CMOS VLSI Design A Brief History, contd. First Planer IC built in 1961 2003 Intel Pentium 4 processor (55 million transistors) 512 Mbit DRAM (> 0.5 billion transistors) 53% compound annual growth rate over 45 years No other technology has grown so fast so long Driven by miniaturization of transistors Smaller is cheaper, faster, lower in power! Revolutionary effects on society
- 12. CMOS VLSI Design 1970’s processes usually had only nMOS transistors Inexpensive, but consume power while idle 1980s-present: CMOS processes for low idle power MOS Integrated Circuits Intel 1101 256-bit SRAM Intel 4004 4-bit Proc
- 13. CMOS VLSI Design Moore’s Law 1965: Gordon Moore plotted transistor on each chip Fit straight line on semilog scale Transistor counts have doubled every 26 months Year Transistors 4004 8008 8080 8086 80286 Intel386 Intel486 Pentium Pentium Pro Pentium II Pentium III Pentium 4 1,000 10,000 100,000 1,000,000 10,000,000 100,000,000 1,000,000,000 1970 1975 1980 1985 1990 1995 2000 Integration Levels SSI: 10 gates MSI: 1000 gates LSI: 10,000 gates VLSI: > 10k gates http://www.intel.com/technology/silicon/mooreslaw/
- 14. CMOS VLSI Design Transistor Types Bipolar transistors npn or pnp silicon structure Small current into very thin base layer controls large currents between emitter and collector Base currents limit integration density Metal Oxide Semiconductor Field Effect Transistors nMOS and pMOS MOSFETS Voltage applied to insulated gate controls current between source and drain Low power allows very high integration First patent in the ’20s in USA and Germany Not widely used until the ’60s or ’70s
- 15. CMOS VLSI Design 0: Introduction Slide 15 nMOS Transistor Four terminals: gate, source, drain, body Gate – oxide – body stack looks like a capacitor – Gate and body are conductors – SiO2 (oxide) is a very good insulator – Called metal – oxide – semiconductor (MOS) capacitor – Even though gate is no longer made of metal n+ p Gate Source Drain bulk Si SiO2 Polysilicon n+
- 16. CMOS VLSI Design 0: Introduction Slide 16 nMOS Operation Body is commonly tied to ground (0 V) When the gate is at a low voltage: – P-type body is at low voltage – Source-body and drain-body diodes are OFF – No current flows, transistor is OFF n+ p Gate Source Drain bulk Si SiO2 Polysilicon n+ D 0 S
- 17. CMOS VLSI Design 0: Introduction Slide 17 nMOS Operation Cont. When the gate is at a high voltage: – Positive charge on gate of MOS capacitor – Negative charge attracted to body – Inverts a channel under gate to n-type – Now current can flow through n-type silicon from source through channel to drain, transistor is ON n+ p Gate Source Drain bulk Si SiO2 Polysilicon n+ D 1 S
- 18. CMOS VLSI Design 0: Introduction Slide 18 pMOS Transistor Similar, but doping and voltages reversed – Body tied to high voltage (VDD) – Gate low: transistor ON – Gate high: transistor OFF – Bubble indicates inverted behavior SiO2 n Gate Source Drain bulk Si Polysilicon p+ p+
- 19. CMOS VLSI Design 0: Introduction Slide 19 Power Supply Voltage GND = 0 V In 1980’s, VDD = 5V VDD has decreased in modern processes – High VDD would damage modern tiny transistors – Lower VDD saves power VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …
- 20. CMOS VLSI Design 0: Introduction Slide 20 Transistors as Switches We can view MOS transistors as electrically controlled switches Voltage at gate controls path from source to drain g s d g = 0 s d g = 1 s d g s d s d s d nMOS pMOS OFF ON ON OFF
- 21. CMOS VLSI Design Transistors Level Symbol Switch Conditions Strong 1 1 P-switch gate=0, source=Vdd Weak 1 1 N-switch gate=1, source=Vdd Strong 0 0 N-switch gate=1, source=Vss Weak 0 0 P-switch gate=0, source=Vss High impedance Z N-switch gate=0, or P-switch gate=1 0: Introduction Slide 21 Input 0 Output Good 0 Input 1 Output poor 1 Input 0 Output poor 0 Input 1 Output good 1
- 22. CMOS VLSI Design 0: Introduction Slide 22 Input 0 Output Good 0 Input 1 Output poor 1 Input 0 Output poor 0 Input 1 Output good 1
- 23. CMOS VLSI Design 0: Introduction Slide 23 CMOS Inverter A Y 0 1 VDD A Y GND A Y
- 24. CMOS VLSI Design 0: Introduction Slide 24 CMOS Inverter A Y 0 1 0 VDD A=1 Y=0 GND ON OFF A Y
- 25. CMOS VLSI Design 0: Introduction Slide 25 CMOS Inverter A Y 0 1 1 0 VDD A=0 Y=1 GND OFF ON A Y
- 26. CMOS VLSI Design CMOS Inverter Vin Vout Vdd Vss Cload Q1 Q2 Id 1- Vin = Vdd Análise do circuito: Vdd=+5V 0V Vout Roff Ron Cálculo de Vout Vdd = Ids(Roff+Ron) => Vdd = Ids.Roff+Ids.Ron => Vdd = Ids.Roff+Vout => Vout = Vdd-Ids.Roff 0V Ids Ron < 1 Kohms Roff 1010Kohms Ids é pequeno, mas Roff é bastante grande
- 27. CMOS VLSI Design CMOS Inverter • Note que Vh = 5V, VL = 0V, e que Ids = 0A. • Isto significa que não existe praticamente dissipação de potência.
- 28. CMOS VLSI Design CMOS Inverter +5V GND Vih=´1´ R +5V GND Out Iol Iil In Vol(max) Vil(max) Tempo (seg) Tensão(V) Vil(max) Nível ´0´ Capacitor carregado (´1´) Transistor conduz Ron 1 K Transistor não conduz Ron 1 K
- 29. CMOS VLSI Design CMOS Inverter Vin Vout Vdd Vss Cload Q1 Q2 Id 2- Vin = 0V Análise do circuito: Vdd=+5V 0V Vout Ron Roff Cálculo de Vout Vdd = Ids(Roff+Ron) => Vdd = Ids.Roff+Ids.Ron => Vdd = Vout+Ids.Ron => Vout = Vdd-Ids.Ron Vdd=5V Ids Ron < 1 Kohms Roff 1010Kohms Ids é muito pequeno
- 30. CMOS VLSI Design CMOS Inverter • Note que Vh = 5V, VL = 0V, e que Ids = 0A. • Isto significa que não existe praticamente dissipação de potência.
- 31. CMOS VLSI Design CMOS Inverter +5V GND Vil=0 R +5V GND Out Ioh Iih In Voh(min) Vih(min) Tempo (seg) Tensão(V) Vih(min) Nível ´1´ Capacitor X Transistor não conduz Roff 1010 Transistor conduz Ron 1 K
- 32. CMOS VLSI Design 0: Introduction Slide 32 CMOS NAND Gate A B Y 0 0 0 1 1 0 1 1 A B Y
- 33. CMOS VLSI Design 0: Introduction Slide 33 CMOS NAND Gate A B Y 0 0 1 0 1 1 0 1 1 A=0 B=0 Y=1 OFF ON ON OFF
- 34. CMOS VLSI Design 0: Introduction Slide 34 CMOS NAND Gate A B Y 0 0 1 0 1 1 1 0 1 1 A=0 B=1 Y=1 OFF OFF ON ON
- 35. CMOS VLSI Design 0: Introduction Slide 35 CMOS NAND Gate A B Y 0 0 1 0 1 1 1 0 1 1 1 A=1 B=0 Y=1 ON ON OFF OFF
- 36. CMOS VLSI Design 0: Introduction Slide 36 CMOS NAND Gate A B Y 0 0 1 0 1 1 1 0 1 1 1 0 A=1 B=1 Y=0 ON OFF OFF ON
- 37. CMOS VLSI Design Lógica Combinacional Porta NAND saída A 0 1 0 1 1 B 1 1 0 A B P P N N Vcc (‘1’) GND (‘0’) saída Vcc GND A B Saída Saída GND A B C n A B C n Vcc Porta NAND de n-entradas (A+B) (A B) Dual Lógico
- 38. CMOS VLSI Design 0: Introduction Slide 38 CMOS NOR Gate A B Y 0 0 1 0 1 0 1 0 0 1 1 0 A B Y
- 39. CMOS VLSI Design Lógica Combinacional Porta NOR A B N N P Vcc (‘1’) GND (‘0’) saída P Vcc GND A B saída Saída Vcc n A B C A B C n GND saída A 0 1 0 1 0 B 1 0 0 (A B) (A+B) Dual Lógico
- 40. CMOS VLSI Design 0: Introduction Slide 40 3-input NAND Gate Y pulls low if ALL inputs are 1 Y pulls high if ANY input is 0 A B Y C
- 41. CMOS VLSI Design 0: Introduction Slide 41 Summary MOS Transistors are stack of gate, oxide, silicon Can be viewed as electrically controlled switches Build logic gates out of switches