EC6601 VLSI Design CMOS Fabrication
- 1. Academic Year 2018-19 EC6601 VLSI Design CMOS Fabrication By Mrs.R.Chitra, AP/ECE, Ramco Institute of Technology, Rajapalayam.
- 2. CMOS VLSI Design 2 Introduction to IC Introduction to CMOS circuits MOS transistor theory, processing technology Introduction: How to build your own simple CMOS chip CMOS transistors Building logic gates from transistors Transistor layout and fabrication Course Topics
- 3. CMOS VLSI Design 3 An integrated circuit (IC), sometimes called a chip or microchip, is a semiconductorwafer on which thousands or millions of tiny resistors, capacitors, and transistors are fabricated. An IC can function as an amplifier, oscillator, timer, counter, computer memory, or microprocessor. Introduction
- 4. CMOS VLSI Design 4 A particular IC is categorized as either linear (analog) or digital, depending on its intended application. Linear ICs have continuously variable output that depends on the input signal level. As the term implies, the output signal level is a linear function of the input signal level. Linear ICs are used as AF and RF amplifiers. The operational amplifier(op amp) is a common device in these applications. Digital ICs operate at only a few defined levels or states, rather than over a continuous range of signal amplitudes. These devices are used in computers, computer networks, modems, and frequency counters. The fundamental building blocks of digital ICs are logic gates, which work with binary data, that is, signals that have only two different states, called low (logic 0) and high (logic 1). Types of IC
- 5. CMOS VLSI Design 5 Processors • CPU, DSP, Controllers Memory chips • RAM, ROM, EEPROM Analog • Mobile communication, audio/video processing Programmable • PLA, FPGA Embedded systems • Used in cars, factories • Network cards System-on-chip (SoC) IC Products
- 6. CMOS VLSI Design 6 First digital Computer The Vacuum tube and transistor
- 7. CMOS VLSI Design 7 The lineage of VLSI technology began in 1833, when Michael Faraday first recorded the semiconductor effect. The next remarkable achievement was made by Russell Ohl in 1940, who discovered the p-n junction effects in silicon that lead to the development of junction transistors. In 1947, the semiconductor technology entered a new phase when, John Bardeen and Walter Brattain (Bell labs) invented the revolutionary semiconductor device called Point-Contact Transistor. Bell Labs named the first type of transistor as "Type A" transistor. A Brief History
- 8. CMOS VLSI Design 8
- 9. CMOS VLSI Design 9 1958: First integrated circuit • Flip-flop using two transistors • Built by Jack Kilby at Texas Instruments 2003 • Intel Pentium 4 µprocessor (55 million transistors) • 512 Mbit DRAM (> 0.5 billion transistors) 53% compound annual growth rate over 45 years • No other technology has grown so fast so long Driven by miniaturization of transistors • Smaller is cheaper, faster, lower in power! • Revolutionary effects on society A Brief History
- 10. CMOS VLSI Design 10 Bipolar transistors • npn or pnp silicon structure • Small current into very thin base layer controls large currents between emitter and collector • Power dissipated by base currents even when the circuit is not switching. • Base currents limit integration density In 1960s, Metal Oxide Semiconductor Field Effect Transistors began to enter • nMOS and pMOS MOSFETS • Voltage applied to insulated gate controls current between source and drain • Low power allows very high integration Transistor Types
- 11. CMOS VLSI Design 11 The MOSFET is a core of integrated circuit The MOSFET works by electronically varying the width of a channel along which charge carriers flow (electrons or holes). The charge carriers enter the channel at source and exit via the drain. The width of the channel is controlled by the voltage on an electrode is called gate which is located between source and drain. Advantages of MOSFET is that they draw almost zero control current while idle. MOS Integrated Circuits
- 12. CMOS VLSI Design 12 Integration: Integrated Circuits ∗ multiple devices on one substrate How large is Very Large? ∗ SSI (small scale integration) ∗ 7400 series, 10-100 transistors ∗ MSI (medium scale) ∗ 74000 series 100-1000 ∗ LSI 1,000-10,000 transistors ∗ VLSI > 10,000 transistors ∗ ULSI/SLSI (some disagreement) VLSI:Very Large Scale Integration
- 13. Integration Improves the Design • Lower parasitic, higher clocking speed • Lower power • Physically small Integration Reduces Manufacturing Costs • (almost) no manual assembly • About $1-5billion/fab • Typical Fab ≈1 city block, a few hundred people • Packaging is largest cost • Testing is second largest cost •For low volume ICs, Design Cost may swamp all manufacturing cost Why VLSI?
- 14. CMOS VLSI Design 14 ∗ Gordon Moore: co-founder of Intel ∗ 1965: Gordon Moore plotted transistor on each chip ∗ Fit straight line on semilog scale ∗ Transistor counts have doubled every 18 months Moore’s Law
- 15. CMOS VLSI Design 15 Many other factors grow exponentially ∗ Ex: clock frequency, processor performance Manufacturers introduce a new process generation (called a technology node) every 2-3 years with 30% smaller feature size to pack twice as many transistors in the same area. Obviously, this scaling cannot go on forever because transistor cannot be smaller than atoms. Corollaries
- 16. CMOS VLSI Design 16 A semiconductor is a material that, under certain conditions will conduct, and under other conditions will not. Those conditions can be controlled by electricity. Most semiconductors can be imagined as a switch which can be configured to perform logic operations. Circuits that do not have semiconductors will always be stable - once turned on, a specific amount of power will flow at all times, and nothing else will happen. If you change the input, then every component of the circuit will change proportionally. If you want a circuit to change its behavior on its own, this requires a semiconductor, usually a transistor. Why are semiconductors used in integrated circuits?
- 17. CMOS VLSI Design 17 Si has great affinity for oxygen. So, it will form silicon dioxide (SiO2). This is an excellent insulating and dielectric material. Also, it has very good masking properties. Si has a larger band-gap (0.7eV) than Ge (0.2eV). Silicon is widely encountered in nature in the form of sand, from which it is extracted by reduction with carbon. In contrast, Ge is not so easily found in nature Ge has one major advantage over Si. Ge has higher electron and hole mobilities and because of this Ge devices can function up to a higher frequency than Si devices. Why we prefer Silicon over Germinium?
- 18. CMOS VLSI Design 18 ∗ Silicon is a semiconductor ∗ Pure silicon has no free carriers and conducts poorly ∗ Adding dopants increases the conductivity ∗ Group V: extra electron (n-type) ∗ Group III: missing electron, called hole (p-type) Dopants As SiSi Si SiSi Si SiSi B SiSi Si SiSi Si SiSi - + + -
- 19. CMOS VLSI Design 19 ∗ Four terminals: gate, source, drain, body ∗ Gate – oxide – body stack looks like a capacitor ∗ Gate and body are conductors ∗ SiO2 (oxide) is a very good insulator ∗ Called metal – oxide – semiconductor (MOS) capacitor ∗ Even though gate is no longer made of metal nMOS Transistor n+ p GateSource Drain bulk Si SiO2 Polysilicon n+
- 20. CMOS VLSI Design 20 ∗ Similar, but doping and voltages reversed ∗ Body tied to high voltage (VDD) ∗ Gate low: transistor ON ∗ Gate high: transistor OFF ∗ Bubble indicates inverted behavior pMOS Transistor SiO2 n GateSource Drain bulk Si Polysilicon p+ p+
- 21. CMOS VLSI Design 21 ∗ Body is commonly tied to ground (0 V) ∗ When the gate is at a low voltage: ∗ P-type body is at low voltage ∗ Source-body and drain-body diodes are OFF ∗ No current flows, transistor is OFF nMOS Operation n+ p GateSource Drain bulk Si SiO2 Polysilicon n+ D 0 S
- 22. CMOS VLSI Design 22 ∗ When the gate is at a high voltage: ∗ Positive charge on gate of MOS capacitor ∗ Negative charge attracted to body ∗ Inverts a channel under gate to n-type ∗ Now current can flow through n-type silicon from source through channel to drain, transistor is ON nMOS Operation Cont. n+ p GateSource Drain bulk Si SiO2 Polysilicon n+ D 1 S
- 23. CMOS VLSI Design 23 Modes of operation of nMOS Transistor:
- 24. CMOS VLSI Design 24 Cut-off region Linear region Saturation region Behaviour of nMOS with differetnt Voltages:
- 25. CMOS VLSI Design 25 Cut-off region
- 26. CMOS VLSI Design 26 Linear region
- 27. CMOS VLSI Design 27 Saturation region
- 28. CMOS VLSI Design 28 ∗ We can view MOS transistors as electrically controlled switches ∗ Voltage at gate controls path from source to drain Transistors as Switches g s d g = 0 s d g = 1 s d g s d s d s d nMOS pMOS OFF ON ON OFF
- 29. CMOS VLSI Design 29 In 1963 CMOS Circuit Configuration was invented which combines p-channel and n- channel MOS transistors in a complementary symmetric circuit configuration, which drew close to zero power in standby mode. CMOS
- 30. CMOS VLSI Design 30 CMOS transistors are fabricated on silicon wafer Lithography process similar to printing press On each step, different materials are deposited or etched Easiest to understand by viewing both top and cross- section of wafer in a simplified manufacturing process CMOS Fabrication
- 31. CMOS VLSI Design 31 ∗ Typically use p-type substrate for nMOS transistors ∗ Requires n-well for body of pMOS transistors Inverter Cross-section n+ p substrate p+ n well A Y GND VDD n+ p+ SiO2 n+ diffusion p+ diffusion polysilicon metal1 nMOS transistor pMOS transistor
- 32. CMOS VLSI Design 32 ∗ Substrate must be tied to GND and n-well to VDD ∗ Metal to lightly-doped semiconductor forms poor connection (used for Schottky Diode) ∗ Use heavily doped well and substrate contacts / taps Well and Substrate Taps n+ p substrate p+ n well A Y GND VDD n+p+ substrate tap well tap n+ p+
- 33. CMOS VLSI Design 33 ∗ Transistors and wires are defined by masks ∗ Cross-section taken along dashed line Inverter Mask Set GND VDD Y A substrate tap well tap nMOS transistor pMOS transistor
- 35. CMOS VLSI Design 35 ∗ Six masks ∗ n-well ∗ Polysilicon ∗ n+ diffusion ∗ p+ diffusion ∗ Contact ∗ Metal Detailed Mask Views Metal Polysilicon Contact n+ Diffusion p+ Diffusion n well
- 36. CMOS VLSI Design 36 ∗ The structure consists of p-type substrate in which n- type devices are formed by masking and diffusion. ∗ To form p-type device, a deep well is diffused in to p-type substrate. ∗ Start with blank wafer n-well process Fabrication Steps p substrate
- 37. CMOS VLSI Design 37 ∗ Grow SiO2 on top of Si wafer ∗ Oxidation process is done by high purity H2O or O2 exposed to 900 – 1200⁰C in oxidation furnace. Oxidation p substrate SiO2
- 38. CMOS VLSI Design 38 ∗ Photolithography is a process to form patterns or images. It is dervied from Greek words: Photo (light), lithos(stone), graphe (picture). This is literally means carving pictures in stone using light. ∗ Spin on photoresist ∗ Photoresist is a light-sensitive organic polymer ∗ Softens where exposed to light Photoresist p substrate SiO2 Photoresist
- 39. CMOS VLSI Design 39 ∗ Expose photoresist to UV rays through n-well mask ∗ Strip off exposed photoresist Lithography: Masking p substrate SiO2 Photoresist
- 40. CMOS VLSI Design 40 Removal of SiO2 using Acid Etching ∗Etch oxide with hydrofluoric acid (HF) ∗ Seeps through skin and eats bone; nasty stuff!!! ∗Only attacks oxide where resist has been exposed Etch p substrate SiO2 Photoresist
- 41. CMOS VLSI Design 41 ∗ Strip off remaining photoresist ∗ Use mixture of acids called piranha etch ∗ Necessary so resist doesn’t melt in next step Strip Photoresist p substrate SiO2
- 42. CMOS VLSI Design 42 Formation of n-well using diffusion or ion implantation Diffusion ∗ Place wafer in furnace with arsenic gas ∗ Heat until As atoms diffuse into exposed Si Ion Implanatation ∗ Beam of As ions which accelerated through electric filed and Blasted into wafer (substarte) ∗ Ions blocked by SiO2, only enter exposed Si n-well n well SiO2
- 43. CMOS VLSI Design 43 ∗ Strip off the remaining oxide using HF ∗ Back to bare wafer with n-well ∗ Subsequent steps involve similar series of steps Strip Oxide p substrate n well
- 44. CMOS VLSI Design 44 ∗ Deposit very thin layer of gate oxide ∗ < 20 Å (6-7 atomic layers) ∗ Chemical Vapor Deposition (CVD) of silicon layer ∗ Place wafer in furnace with Silane gas (SiH4) & heated to grow poly Si layer a process called Chemical Vapor Deposition. Deposition of Polysilicon & SiO2 Thin gate oxide Polysilicon p substrate n well
- 45. CMOS VLSI Design 45 ∗ Use same lithography process to pattern polysilicon ∗ Except the two small regions required for forming the Gates of nMOS and pMOS ∗ Remamining layer is stripped off Polysilicon Patterning p substrate Thin gate oxide Polysilicon n well
- 46. CMOS VLSI Design 46 ∗ Use oxide and masking to expose where n+ dopants should be diffused or implanted ∗ N-diffusion forms nMOS source, drain, and n-well contact N-diffusion p substrate n well
- 47. CMOS VLSI Design 47 ∗ Pattern oxide and form n+ regions N-diffusion (cont.) p substrate n well n+ Diffusion
- 48. CMOS VLSI Design 48 ∗ Historically dopants were diffused ∗ Usually ion implantation today ∗ But regions are still called diffusion N-diffusion (cont.) n well p substrate n+n+ n+
- 49. CMOS VLSI Design 49 ∗ Strip off oxide to complete patterning step N-diffusion (cont.) n well p substrate n+n+ n+
- 50. CMOS VLSI Design 50 ∗ Similar set of steps, form p+ diffusion regions for pMOS source and drain and substrate contact P-Diffusion p+ Diffusion p substrate n well n+n+ n+p+p+p+
- 51. CMOS VLSI Design 51 ∗ Now we need to wire together the devices ∗ Cover chip with thick field oxide ∗ Etch oxide where contact cuts are needed Contacts p substrate Thick field oxide n well n+n+ n+p+p+p+ Contact
- 52. CMOS VLSI Design 52 ∗ Sputter on copper / aluminum over whole wafer ∗ Pattern to remove excess metal, leaving wires Metalization Metal
- 53. CMOS VLSI Design 53 CMOS Inverter A Y 0 1 1 0 VDD A=0 Y=1 GND OFF ON A Y
- 54. CMOS VLSI Design 54 CMOS NAND Gate A B Y 0 0 1 0 1 1 1 0 1 1 1 0 A=1 B=1 Y=0 ON OFF OFF ON
- 55. CMOS VLSI Design 55 CMOS NOR Gate A B Y 0 0 1 0 1 0 1 0 0 1 1 0 A B Y
- 56. CMOS VLSI Design 56 ∗ Y pulls low if ALL inputs are 1 ∗ Y pulls high if ANY input is 0 3-input NAND Gate A B Y C
- 57. CMOS VLSI Design 57 ∗ Compound gates can do any inverting function ∗ Ex: Compound Gates (AND-AND-OR-INVERT, AOI22)Y A B C D= +g g A B C D A B C D A B C D A B C D B D Y A C A C A B C D B D Y (a) (c) (e) (b) (d) (f)
- 58. CMOS VLSI Design 58 ∗ Example: O3AI ( )Y A B C D= + + g A B Y C D DC B A
- 59. CMOS VLSI Design 59 ∗ MOS Transistors are stack of gate, oxide, silicon ∗ Can be viewed as electrically controlled switches ∗ Build logic gates out of switches Summary
- 60. CMOS VLSI Design 60 ∗ Jan Rabaey, Anantha Chandrakasan, B.Nikolic, “Digital Integrated Circuits: A Design Perspective”, Second Edition, Prentice Hall of India, 2003. ∗ M.J. Smith, “Application Specific Integrated Circuits”, Addisson Wesley, 1997. ∗ N.Weste, K.Eshraghian, “Principles of CMOS VLSI Design”, Second Edition, Addision Wesley 1993. References:
Editor's Notes
- #6: Datapath is the “computational unit” of a processor Digital Signal Processing (DSP) chips are used all over the place: audio, image processing, satellite applications, etc. Memory performance always behind CPU speed, greater need for more capacity, bandwidth Network processors: low-cost, versatile, fast designs needed for the increasing internet applications, protocols, etc.