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- 1. VLSI DESIGN UNIT-4 INTRODUCTION TO MOS TECHNOLOGIES
- 2. INTRODUCTION TO INTEGRATED CIRCUIT What is an Integrated Circuit? An integrated circuit (IC) is a small semiconductor-based electronic device consisting of fabricated transistors, resistors and capacitors. Integrated circuits are the building blocks of most electronic devices and equipment. An integrated circuit is also known as a chip or microchip An IC can be a function as an amplifier, oscillator, timer, counter, computer memory, or microprocessor. Why ICs? • Size • Speed • Power • Complexity Smaller size of IC components yields higher speed and low power consumption Integration reduces manufacturing costs
- 3. Invention of the Transistor: Vacuum tubes ruled in first half of 20th century Large, expensive, power-hungry, unreliable In 1940-The initial invention that made Integrated circuits (ICs) possible. In 1945-Bell Labs established a group to develop a semiconductor replacement for the vacuum tube. The group led by William B. Shockley, Walter H. Brattain and John Bardeen and others. 1947- William B. Shockley, Walter H. Brattain and John Bardeen succeeded in creating an amplifying circuit utilizing a point contact ‘’Transfer resistance’’ device that later becomes known as a ‘’Transistor”. In 1951- William Shockley developed the junction transistor, a more practical form of the transistor. In 1954- The transistor was an essential components of the telephone system and transistor first appeared in hearing aids followed bye radios INTRODUCTION TO INTEGRATED CIRCUIT
- 4. INTRODUCTION TO INTEGRATED CIRCUIT
- 5. Invention of the ICs: 1957: Robert Noyce leaves Shockley Labs to form Fairchild with Jean Hoerni and Gordon Moore. 1958: Hoerni invents technique for diffusing impurities into Si to build planar transistors using a SiO2 insulator. In 1958-Jack Kilby and Robert at Texas Instrument had built a simple Oscillator IC with five integrated components ( Resistor, Capacitors, Distributed capacitors and Transistors) 1959: Robert Noyce develops first true IC using planar transistors, back-to-back PN junctions for isolation, diode-isolated Si resistors and SiO2 insulation with evaporated metal wiring on top. INTRODUCTION TO INTEGRATED CIRCUIT
- 6. INTRODUCTION TO INTEGRATED CIRCUIT First IC Jack Kilby Texas Instruments 1958
- 7. In 1960-Epitaxial Deposition developed: Bell Labs developed the techniques of Epitaxial Deposition whereby a single crystal layer of material on a crystalline substrate. Epitaxial Deposition is wisely used in bipolar and sub-micron CMOS Fabrication. In 1960- First MOSFET Fabricated- Kahng at Bell Labs Fabricates the first MOSFET. In 1961 First commercial ICs, Fairchild and Texas Instruments both introduce commercial ICs. In 1962- Transistor Transistor logic Invented In 1962- Radio Corporation of America(RCA) develops fabricating multipurpose logic block comprising 16 MOS FETs on a single chip. This is the first MOS transistor In 1962, RCA was fabricating multipurpose logic block comprising 16 MOS FETs on a single chip In mid-1965, only two companies were producing MOS ICs, ---> P-MOS,NMOS,CMOS INTRODUCTION TO INTEGRATED CIRCUIT
- 8. Fairchild bipolar RTL Flip-Flop: This device, developed by Robert Noyce in the late 1960s, was the first commercially available integrated circuit (it was a Flip-Flop). Courtesy: Fairchild Semiconductor. RCA 16-transistor MOSFET IC The first planar IC (Fairchild bipolar RTL Flip-Flop) INTRODUCTION TO INTEGRATED CIRCUIT
- 9. Introduction to IC Technology Moore’s Law: Gordon E. Moore was the cofounder of Intel Corporation 1965 - Observed trends in industry - of transistors on ICs vs release dates. Moore’s Law states the number of transistors per chip would grow exponentially (double every 18 months). Moore’s Law states that transistor density on integrated circuits doubles every two years.
- 10. Introduction to IC Technology
- 12. Introduction to IC Technology
- 13. SCALE OF INTEGRATION Classification of ICs on basis of chip sizes: Integrated Circuits can be classified based on its integration scale. An integration scale denotes the number of components fitted into a standard Integrated Circuit. Generation of ICs • Small scale integration(SSI) • Medium scale integration(MSI) • Large scale integration(LSI) • Very large scale integration(VLSI) • Ultra large scale integration(ULSI) • Giant scale integration(GSI)
- 15. SCALE OF INTEGRATION • Minimum feature size • Number of gates • Power dissipation • Gate delay • Die size • Testing • Reliability • Production cost Transistor modeling: The transistor models are characterized by a figure of merit that depends on performance, level of integration and cost. These are further influenced by a member of other factors including. Speed and Power : Smaller size of IC components yields higher peed and lower power consumption due to smaller parasitic resistances, capacitances and inductances. Lower power consumption ripple effect =>less heat =>cheaper power supplies => reduced system cost.
- 16. From the graph we can conclude that GaAs technology is better but still it is not used because of growing difficulties of GaAs crystal. CMOS looks to be a better option compared to nMOS since it consumes a lesser power. BiCMOS technology is also used in places where high driving capability is required and from the graph it confirms that, BiCMOS consumes more power compared to CMOS. SCALE OF INTEGRATION
- 17. INTRODUCTION TO VLSI Why VLSI? Integration: Integrated circuits • Multiple devices (components like digital or Analog) on one substrate Integration improves the design • Compactness: Less area, physically smaller • Higher speed: Lower parasitic (reduced interconnection length) • Lower power consumption • Higher reliability: Improved on-chip interconnects Integration significantly reduces manufacturing cost Very Large-Scale Integration (VLSI): Is the process of integrating or embedding hundreds of thousands of transistors on a single silicon semiconductor microchip. VLSI technology was conceived in the late 1970s when advanced level computer processor microchips were under development.
- 18. VLSI Applications VLSI is an implementation technology for electronic circuitry - Analogue or Digital Microprocessors Like Personal computers, Microcontrollers and Workstations Memory – DRAM, SRAM, RAM, ROM, EEPROM Special Purpose Processors - ASICS (CD players, DSP applications) Signal Processing (DSP chips, Data Acquisition Systems) Transaction processing (Bank ATMs) Medical Electronics (Artificial eye, Implants) Multimedia Voice and Data Communication like Mobile communication, Audio/Video processing Commercial Electronics Automobiles
- 19. Metal-Oxide-Semiconductor (MOS) and Related VLSI Technology MOS Technology ( Si-Technology) Bipolar CMOS BiCMOS SOI SiGe GaAs Junction Isolated Dielectric Isolated Oxide Isolated MOS CMOS PMOS (Al Gate) NMOS Al Gate Si Gate Al Gate Si Gate Si and Ge Si For RF For High Speed
- 20. Semiconductor Review Create by doping a pure Silicon crystal Diffuse impurity into semiconductor alters the crystal structure Changes the concentration of carriers • Electrons • Holes More doping -> more carriers available n-type semiconductor (n or n+) Majority carrier: electrons Typical impurity: Phosphorus Arsenic (Column V), Arsenic, Antimony p-type semiconductor (p or p+) Majority carrier: holes Typical impurity: Boron (Column III), Indium, Gallium Dopants are usually implanted into the semiconductor using implant technology followed by thermal process to diffuse the dopants. n n+ p p+
- 21. Semiconductor Review Insulator - Silicon Dioxide (SiO2) Used to insulate transistor gates (thin oxide) Used to insulate layers of wires (field oxide) Can be grown on Silicon or Chemically Deposited Polysilicon - polycrystalline silicon Key material for transistor gates Also used for short wires Added by chemical deposition Metal - Aluminum ore recently Copper) Used for wires Multiple layers common Added by vapor deposition or “sputtering”
- 22. Basic MOS Transistors MOS: Metal Oxide Semiconductor Four terminals: Gate, Source, Drain, Body MOS Transistor is a majority carrier device, Current is a conducting channel between source and drain. • Modulated by voltage applied to the gate (voltage controlled device) Two Types of MOS Transistor • PMOS Transistor • NMOS Transistor NMOS Transistor: Majority carriers are electrons (greater mobility), p-substrate doped (positively doped) • Free electrons move from Source to Drain • Current direction is from Drain to Source PMOS Transistor: Majority carriers are holes (less mobility), n-substrate (negatively doped) • Free holes move from Source to Drain • Current direction is from Source to Drain.
- 23. MOS Transistor Structure Polysilicon Gate SiO2 Insulator n+ n+ p substrate channel Source Drain n transistor G S D SB L W G S D substrate connected to GND p+ p+ n substrate channel Source Drain p transistor G S D SB Polysilicon Gate SiO2 Insulator L W G substrate connected to VDD
- 24. MOS Transistor Structure Carriers always flow from the Source to Drain Mode of operation depends on Vg, Vd, Vs • Vgs = Vg – Vs • Vgd = Vg – Vd • Vds = Vd – Vs Source and drain are symmetric diffusion terminals • By convention, source is terminal at lower voltage • Hence Vds ≥ 0
- 25. MOS Transistor Structure NMOS Transistor: NMOS device are formed in a p-type substrate of moderate doping level. The source and drain regions are formed by diffusing n-type impurities through suitable masks into these areas to give the desired n-impurity concentration and give rise to depletion regions which extend mainly in the more lightly doped p-region.
- 26. NMOS Transistor Operations modes NMOS Transistor operation modes are • The Enhancement mode • Depletion mode NMOS Enhancement mode : An NMOS transistor that has no conducting channel region at zero gate bias (Vgs=0) is called enhancement type ( Enhancement mode) MOSFET.
- 27. NMOS Transistor Operations modes NMOS Depletion mode: If a conducting channel already exist at zero gate bias (Vgs=0) the device is called a depletion type (Depletion mode) MOSFET.
- 28. NMOS Transistor Operations Modes There are three regions of operation in the n- Channel MOSFET • Cutoff mode • Linear mode • Saturation mode Vgs = 0 : Cutoff mode • Transistor OFF • Majority carrier in channel (holes) • No current from source to drain 0 < Vgs < Vt : Depletion region • Electric field repels majority carriers (holes) • Depletion region forms - no carriers in channel • No current flows (except for leakage current)
- 29. NMOS Transistor Operations modes Vgs > Vt , VDS=0: Transistor ON • Electric field attracts minority carriers (electrons) • Inversion region forms in channel • Depletion region insulates channel from substrate • Current can now flow from drain to source! Vgs > Vt , VDS <VGS -VT : Linear (Active, Triode) mode • Combined electric fields shift channel and depletion region • Current flow dependent on VGS, VDS • For VDS>0, a current proportional to VDS flows from source to drain • Behaves like a voltage-controlled resistance
- 30. NMOS Transistor Operations modes Vgs > Vt , VDS >VGS -VT : Saturated mode • Channel ends before reaching the drain • Channel “pinched off” • Electrons drift, usually reaching the drift velocity limit, across the depletion region to the drain • Drift due to high E-field produced by the potential VDS-VD(SAT) between the drain and the end of the channel
- 31. NMOS Transistor Operations modes If increase the drain voltage substantially (VDS >VDSsat , VDSsat is called the saturation voltage) The drain voltage becomes large enough that the gate to substrate potential at the drain is smaller than an threshold. The point at which the inversion layer density becomes very small (essentially zero) at the drain end is termed pinch-off Therefore the channel thickness at this end goes to zero. It is call this pinch-off.
- 32. NMOS IDS-VDS Characteristics For VGS < VT , ID = 0 As VDS increases at a fixed VGS , ID increases in the triode region due to the increased lateral field, but at a decreasing rate since the inversion layer density is decreasing Once pinch off is reached, further VDS increases only increase ID due to the formation of the high field region The device starts in triode, and moves into saturation at higher
- 33. PMOS TRANSISTOR PMOS Transistor: Similar NMOS, p-channel device (n- and p-type regions reversed.) • Body tied to high voltage (VDD) • Gate low: Transistor ON • Gate high: Transistor OFF • Bubble indicates inverted behavior p+ p+ n substrate channel Source Drain p transistor G S D SB Polysilicon Gate SiO2 Insulator L W G substrate connected to VDD
- 34. PMOS Transistor Operation Opposite of N-Transistor Vgs >> Vt : Transistor OFF • Majority carrier in channel (electrons) • No current from source to drain (Ids=0) 0 > Vgs > Vt : Depletion region • Electric field repels majority carriers (electrons) • Depletion region forms - no carriers in channel • No current flows (except for leakage current) Vgs < Vt , VDS=0: Transistor ON • Electric field attracts minority carriers (holes) • Inversion region forms in channel • Depletion layer insulates channel from substrate • Current can now flow from source to drain!
- 35. PMOS Transistor Modes of Operation Vgs <Vt , VDS >VGS -VT : Linear (Active) mode • Combined electric fields shift channel and depletion region • Current flow dependent on VGS, VDS Vgs < Vt , VDS <VGS -VT : Saturation mode • Channel “pinched off” • Current still flows due to hole drift • Current flow dependent on VGS
- 36. NMOS fabrication process There are a large number and variety of basic fabrication steps used in the production of modern MOS ICs. The same process can be used for the designed of NMOS or PMOS or CMOS devices. The gate material could be either metal or poly-silicon . The most commonly used substrate is bulk silicon or silicon-on-sapphire (SOS). In order to avoid the presence of parasitic transistors, variations are brought in the techniques that are used to isolate the devices in the wafer. Basic Key words in fabrication • Photolithography– Pattern setting • Implantation – Add dopants to silicon • Deposition– Add new layers (metals, oxides) • Etching – take away sections of layers • Oxidation– for gate oxides - need native oxide
- 37. The fabrication steps are as follows: Step1: Processing is carried out on a thin wafer cut from a single crystal of silicon of high purity into which the required p-impurities are introduced as the crystal is grown. Such wafers are typically 75 to 150 mm in diameter and 0.4 mm thick and are doped with, say, boron to impurity concentrations of 1015 /cm3 to 1016 /cm3, giving resistivity in the approximate range 25 ohm cm to 2 ohm cm. NMOS fabrication process
- 38. Step2: A layer of silicon dioxide (Si02), typically 1 µm thick, is grown all over the surface of the wafer to protect the surface, act as a barrier to dopants during processing, and provide a generally insulating substrate on to which other layers may be deposited and patterned. NMOS fabrication process
- 39. Step3: The surface is now covered with a photoresist which is deposited onto the wafer and spun to achieve an even distribution of the required thickness. NMOS fabrication process
- 40. Step4: The photoresist layer is then exposed to ultraviolet light through a mask which defines those regions into which diffusion is to take place together with transistor channels. Assume, for example, that those areas exposed to ultraviolet radiation are polymerized (hardened), but that the areas required for diffusion are shielded by the mask and remain unaffected. NMOS fabrication process
- 41. Step5: These areas are subsequently readily etched away together with the underlying silicon dioxide so that the wafer surface is exposed in the window defined by the mask. NMOS fabrication process
- 42. Step6: The remaining photoresist is removed and a thin layer of Si02 (0.1 µm typical) is grown over the entire chip surface and then polysilicon is deposited on top of this to form the gate structure. NMOS fabrication process
- 43. Step7: Further photoresist coating and masking allows the polysilicon to be patterned (as shown in Step 6) and then the thin oxide is removed to expose areas into which n-type impurities are to be diffused to form the source and drain. NMOS fabrication process
- 44. Step8: Thick oxide (Si02) is grown over all again and is then masked with photoresist and etched to expose selected are of the polysilicon gate and the drain and source areas where connections (i.e. contact cuts) are to be made. NMOS fabrication process
- 45. NMOS fabrication process • Step9: The whole chip then has metal (aluminum) deposited over its surface to a thickness typically of I µm. This metal layer is then masked and etched to form the required interconnection pattern.
- 46. CMOS FABRICATION For less power dissipation requirement CMOS Technology is used for implementing transistors. If we require a faster circuit then transistors are implemented over IC using BJT. Fabrication of CMOS transistors as IC’s can be done in three different methods. • The p-well Process • The n-well Process • The twin-Tub Process The N-well / P-well technology, where n-type diffusion is done over a p-type substrate or p-type diffusion is done over n-type substrate respectively. The Twin well technology, where NMOS and PMOS transistor are developed over the wafer by simultaneous diffusion over an epitaxial growth base, rather than a substrate.
- 47. CMOS P-Well process steps The P-Well process steps are as follows : Noting that the basic processing steps are of the same nature as those used for NMOS Mask 1 - Defines the areas in which the deep p-well diffusions are to take place. Mask 2 - Defines the thinox regions, namely those areas where the thick oxide is to be stripped and thin oxide grown to accommodate p- and n-transistors and wires. Mask 3 - Used to pattern the polysilicon layer which is deposited after the thin oxide. Mask 4 - A p-plus mask is now used (to be in effect "Anded" with Mask 2) to define all areas where p-diffusion is to take place.
- 48. Mask 5 - This is usually performed using the negative form of the p- plus mask and defines those areas where n-type diffusion is to take place. Mask 6 - Contact cuts are now defined. Mask 7 - The metal layer pattern is defined by this mask. Mask 8 - An overall passivation (over glass) layer is now applied and Mask 8 is needed to define the openings for access to bonding pads. CMOS P-Well process steps
- 49. CMOS P-Well process steps
- 50. CMOS P-Well process steps
- 52. CMOS N-Well Process steps
- 55. CMOS Twin-Tub Process A logical extension of the p-well and n-well approaches is the twin-tub fabrication process Here the process start with a substrate of high resistivity n-type material and then create both n-well and p-well regions. Through this process it is possible to preserve the performance of n-transistors without compromising the p-transistors. Doping control is more readily achieved and some relaxation in manufacturing tolerances results. Twin tub has following steps Tub formation Thin oxide construction Gate formation Source and drain implantations Contact cut definition Metallization
- 59. BICMOS Technology A known deficiency of MOS technology lies in the limited load driving capabilities of MOS transistors. This is due to the limited current sourcing and current sinking abilities associated with both p- and n-transistors. Bipolar transistors provide higher gain and have generally better noise and high frequency characteristics than MOS transistors and BiCMOS gates could be an effective way of speeding up VLSI circuits. What is BiCMOS? BiCMOS technology combines Bipolar and CMOS transistors onto a single integrated circuit where the advantages of both can be utilized.
- 61. BiCMOS npn Transistor The production of npn bipolar transistors with good performance characteristics can be achieved by extending the standard n-well CMOS processing to include further masks to add two additional layers such as the • n+ subcollector • p+ base layers. The npn transistors is formed in an n- well and the additional p+ base region is located in the well to form the p-base region of the transistor. The second additional layer, the buried n+ subcollector (BCCD), is added to reduce the n-well (collector) resistance and thus improve the quality of the bipolar transistor.
- 62. The plan view of a BiCMOS npn Transistor is BiCMOS npn Transistor
- 63. BiCMOS npn Transistor The cross-sectional view of a BiCMOS npn transistor is
- 64. BICMOS Fabrication in an n-well Process The basic process steps used are those already outlined for CMOS but with additional process steps and additional masks defining: • The p+ base region; • n+ collector area; and • The buried sub collector (BCCD).
- 65. Applications of BiCMOS Technology • Full custom ICs • ALU’s, Barrel Shifters • SRAM, DRAM • Microprocessor, Controller • Semi custom ICs • Register, Flip flop ,Standard cells • Adders, mixers, ADC, DAC • Gate arrays • Flash A/D Converters • System-on-Chip Technology • And many mixed signal applications Applications of BiCMOS Technology
- 66. Basic Electrical Properties of MOS Drain-to-source Current (Ids) versus Voltage (Vds) Relationships: The MOS transistors are voltage controlled device. A voltage on the gate terminal induces a charge in the channel that exist between source and drain. The charge then move from source to drain under the influence of electric field generated by voltage Vds applied between drain and source. The charge induced is dependent on the gate to source voltage Vgs , the current Ids is dependent on both Vgs and Vds. The relationship between these parameters can be developed Consider a typical structure of NMOS Transistor in shown in Fig.2.1 The drain to source current Ids is given by
- 67. Drain-to-source Current (Ids) versus Voltage (Vds) Relationships
- 68. Drain-to-source Current (Ids) versus Voltage (Vds) Relationships
- 69. Drain-to-source Current (Ids) versus Voltage (Vds) Relationships
- 70. The Non-saturated Region: When device is operated in non-saturated region the IR drop in the channel is same throughout the channel and can be taken as average value as Vds/2. Where Vds is voltage difference between gate and channel assuming substrate connected to channel. In non-saturated region , the effective gate voltage Vg is given by Threshold Voltage (Vt): Threshold voltage needed to invert the charge under the gate and establish the channel. The charge gets induced into the channel due to gate voltage and if Eg is the average electric filed from gate to channel • The The total induced charge for the area of WL is given by Drain-to-source Current (Ids) versus Voltage (Vds) Relationships
- 71. Drain-to-source Current (Ids) versus Voltage (Vds) Relationships
- 72. Drain-to-source Current (Ids) versus Voltage (Vds) Relationships
- 73. Drain-to-source Current (Ids) versus Voltage (Vds) Relationships
- 74. The Saturated Region: The device enters in saturation when Vds = Vgs – Vt because at this point the IR drop in the channel equals the effective gate channel voltage. The current through the channel remains fairly constant for any further increase in Vds Drain-to-source Current (Ids) versus Voltage (Vds) Relationships
- 75. Typical characteristics for NMOS transistors Typical characteristics NMOS transistors are shown in Fig.2.2
- 76. Typical characteristics for NMOS transistors
- 77. Typical characteristics for PMOS transistors are similar, with suitable reversal of polarity. Following expressions summarizes currents in the three regions Drain-to-source Current (Ids) versus Voltage (Vds) Relationships
- 78. Aspects of MOS Transistor Threshold Voltage (Vt): The gate structure of MOS transistor consists of charge stored in the dielectric layers, surface to surfaces and in the substrate itself. The threshold voltage decided by the structural details of gate-channel structure For switching an enhancement mode MOS transistor from the OFF to the ON state necessitates applying sufficient gate voltage to neutralize these charges and enable the underlying silicon to undergo an inversion due to the electric field from the gate. For switching an depletion mode NMOS transistor from the ON to the OFF state consists in applying enough voltage to the gate to add to the stored charge and invert the 'n' implant region to 'p'. Threshold Voltage (Vt): Threshold voltage is defined as gate voltage for which to surface invert (channel creation) the charge under the gate and establish the channel. • VGS<Vt: No channel implies no current flow possible. • VGS>Vt: Existence the channel implies possible current flow.
- 79. Aspects of MOS Transistor Threshold Voltage (Vt) Threshold Voltage is a function of • Gate conductor material • Gate insulator material • Gate insulator thickness • Impurity at the silicon-insulating surface • Voltage between the source and substrate (VSB) • Temperature
- 80. Threshold Voltage Work functions The threshold voltage Vt may be expressed as: where QB = The charge per unit area in the depletion layer beneath the oxide QSS = charge density at Si:Si02 interface Ꜫꜫ C0 = capacitance per unit gate area ᶲms = work function difference between gate and Si ᶲfN = Fermi level potential between inverted surface and bulk Si.
- 81. To evaluate Vt each term is determined as follows: Threshold Voltage Work functions
- 82. The threshold voltage depends on the Source-to-Bulk voltage (VSB) The body effects :The body effects (body bias) is the potential difference between Source and Bulk (substrate) voltage (VSB) . • If the source to body voltage VSB is non-zero, the corrective term must be applied to Vt • Increasing VSB causes the channel to be depleted of charge carriers and thus the threshold voltage is raised Threshold Voltage Work functions
- 83. Threshold Voltage Work functions
- 84. Transconductance (gm): Transconductance expresses the relationship between output current Ids and the input voltage Vgs and is defined as • To find an expression for gm in terms of circuit and transistor parameters, consider that the charge in channel Qc is such that • where is transit time. Thus change in current MOS Transistor Transconductance (gm) Output Conductance (gds)
- 85. MOS Transistor Transconductance (gm) Output Conductance (gds)
- 86. It is possible to increase the gm, of a MOS device by increasing its width. This will also increase the input capacitance and area occupied. A reduction in the channel length results in an increase in ω0 owing to the higher gm. The gain of the MOS device decreases owing to the strong degradation of the output resistance = 1lgds The output conductance gds can be expressed by For the MOS devices, strong dependence on the channel length demonstrated as MOS Transistor Transconductance (gm) Output Conductance (gds)
- 87. MOS Transistor Figure of Merit (ω0) Figure of merit (ω0): Figure of merit is measure of frequency response and switching performance. Figure of merit is defined as Figure of merit depends on • Carrier mobility • Gate voltage (above threshold) • Inversely as the square of channel length A high speed switching circuit requires a high gm as possible
- 88. The mobility µ describes the case with carriers drift. The mobility may be vary in a number of ways. Primary mobility varies according to the charge carrier , whether electrons or holes. The other factor deciding the mobility is orientation of crystal. For example electron mobility on a (100) oriented n-type inversion layer surface (µn) is larger than that on a ( 111) oriented surface, it is three times of hole mobility on a (111) oriented p-type inversion layer. Surface mobility is also a function of gate voltage (Vgs - Vt). The choice of (100) oriented p-type substrate in which the inversion layer will have a surface carrier mobility µm= 650 cm2 /V- sec at room temperature. Would most suited for a fast NMOS circuit . This surface carrier mobility (µs) is still quit less than bulk mobility(µ). MOS Transistor Figure of Merit (ω0)
- 89. The Pass Transistor MOS transistors to be used as switches in series with lines carrying logic levels in a way that is similar to the use of relay contacts. This application of the MOS device is called the pass transistor. Pass transistor Logic (PTL) involves NMOS or PMOS transistor to transfer the logic values from one node of a circuit to another node under the control of a MOS gate voltage. Pass transistor chain can be used in design of regular array based structure such as Multiplexers, PLAs and ROMs etc.
- 90. The Pass Transistor The pass transistor is an NMOS used as a switch-like element to connect logic and storage. • The voltage on the gate, Vg, determines whether the pass transistor is “open” or “closed” as a switch. • If Vg = H, it is “closed” and connects Vout to Vin. • If Vg = L, it is “open” and Vout is not connected to Vin. • Consider Vin = L and Vin = H with Vg = H. With Vin = L, the pass transistor is much like a pull-down transistor in an inverter or NAND gate. So Vout becomes L. But, • for Vin = H, the output becomes the effective source of the NMOS. When VGS = VDD-VOUT =VTn , the NMOS cuts off. The H level is VOUT = VDD-VTn. • The output remains high impedance state when gate voltage is zero Vin Vout Vg Vg = 1 Vg = 0
- 91. The Pass Transistors • NMOS Transistors pass a strong 0 but a weak 1 • PMOS Transistors pass a strong 1 but a weak 0 This is the reason that N-Channel transistors are used in the pull-down network and P-Channel in the pull-up network of a CMOS gate.
- 92. NMOS Transistors in Series/Parallel Primary inputs drive both gate and source/drain terminals NMOS switch closes when the gate input is high Remember - NMOS transistors pass a strong 0 but a weak 1
- 93. PMOS Transistors in Series/Parallel Primary inputs drive both gate and source/drain terminals PMOS switch closes when the gate input is low Remember - PMOS transistors pass a strong 1 but a weak 0
- 94. THE NMOS INVERTER Basic Inverter: The basic inverter circuit requires a transistor with source connected to ground and a load resistor connected from the drain to the positive supply rail VDD· The output is taken from the drain and the control input applied between gate and ground. Resistors are not conveniently produced on the silicon substrate, they occupy excessively large areas so that some other form of load resistance is required. A convenient way to solve this problem is to use a depletion mode transistor as the load, as shown in Figure
- 97. NMOS Inverter with enhancement load NMOS Inverter with Depletion load THE NMOS INVERTER Depletion mode : Channel exists even with zero gate voltage This inverter consist of two enhancement- only NMOS transistors Pull-Up Pull-Down
- 98. NMOS Inverter with Depletion load: With no current drawn from the output, the currents Ids for both transistors must be equal. • The gate is connected to the source so it is always on and only the characteristic curve Vgs = 0 is relevant. • In this configuration the depletion mode device is called the Pull-Up (P.U.) and the enhancement mode device the Pull-Down (P.D.) transistor. • To obtain the inverter transfer characteristic superimpose the Vgs = 0 depletion mode characteristic curve on the family of curves for the enhancement mode device, • That maximum voltage across the enhancement mode device corresponds to minimum voltage across the depletion mode transistor. THE NMOS INVERTER
- 99. Voltage Transfer Characteristic NMOS Inverter with depletion load
- 100. Note that as Vin(=Vgs p.d. transistor) exceeds the p.d. threshold voltage current begins to flow. The output voltage Vout thus decreases and the subsequent increases in Vin will cause the p.d. transistor to come out of saturation and become resistive. Note that the p.u. transistor is initially resistive as the p.d. turns on. During transition, the slope of the transfer characteristic determines the gain: The point at which Vout = Vin, is denoted as Vinv and it will be noted that the transfer characteristics and Vinv can be shifted by variation of the ratio of pull-up to pulldown resistances (denoted Zp.ulZp.d. where Z is determined by the length to width ratio of Voltage Transfer Characteristic NMOS Inverter with depletion load
- 101. Determination of Pull-up to Pull-down Ratio (Zpu/Zpd.) for an NMOS Inverter Driven by Another NMOS Inverter Fig. Shows an inverter is driven from the output of another similar inverter. Let Vgs = 0 for the depletion mode transistor under all conditions, also in order to cascade inverters without degradation of levels, our target is to meet the requirement In order to equal margins around the inverter threshold, we select Vinv = 0.5VDD· Then both the transistors are in saturation, the drain to source current under the saturation is given by
- 102. Determination of Pull-up to Pull-down Ratio (Zpu/Zpd.) for an NMOS Inverter Driven by Another NMOS Inverter • In the depletion mode • in the enhancement mode Since the two currents are same (P.U and P.D devices are in series ), we have Where Wp.d, Lp.d.,Wp.u., and Lp.u. are the widths and lengths of the pull-down and pull-up transistors respectively.
- 103. Determination of Pull-up to Pull-down Ratio (Zpu/Zpd.) for an NMOS Inverter Driven by Another NMOS Inverter Denoting by We get From which The typical values for the voltages are Vtd= 0.2VDD. Vt =- 0.6VDD and Vinv = 0.5VDD (to have equal margin) Putting these values into equation we get
- 104. Pull-up To Pull-down Ratio For an NMOS Inverter Driven Through One or More Pass Transistors Sometimes the input to an inverter 2 may come from the output of inverter 1 but passes through one or more nMOS transistors that are used as pass transistors. Such an arrangement is shown in fig. 2.9 The point concern here is that connection of pass transistors in series will degrade the logic 1 level into inverter 2 so that the output may not be a proper logic 0 level. Of special concern is the condition when point A in fig. 2.9 is at 0 volts and B is thus at VDD. But the voltage into inverter 2 at point C has got reduced from VDD by the threshold voltage of the series pass transistor. With the gates all pass transistor connected to VDD as shown in Fig. 2.9. there is a reduction in voltage by Vtp, where Vtp is the threshold voltage of a pass transistor.
- 105. Pull-up To Pull-down Ratio For an NMOS Inverter Driven Through One or More Pass Transistors Although many devices are connected in series, there can be no voltage drop in the channels since no static current flows through them. Hence the input voltage to inverter 2 is Vin2= VDD-Vtp where Vtp= Threshold voltage for a pass transistor • We now aim at getting the same voltage as would be the case for inverter 1 driven with input = VDD· • When input to inverter 1 (Figure 2.1O (a)) with input = VDD, Its pull down transistor T2 conducting but with a low voltage across it, therefore, it is in its resistive region of operation represented by R1 as shown in Figure 2.10. At the same time the p.u. transistor T1 is in saturation and is represented as a current source. • The current source in the p.d. transistor, which in its linear region of operation is give by
- 106. Pull-up To Pull-down Ratio For an NMOS Inverter Driven Through One or More Pass Transistors
- 107. Therefore Then The pull up device is in depletion mode in saturation with Vgs = 0, Its current The output of inverter1 Pull-up To Pull-down Ratio For an NMOS Inverter Driven Through One or More Pass Transistors Note: That Vds1 is small and Vds1/2 may be ignored
- 108. Now Consider inverter 2 (Figure 2.10(b)) when input = VDD- Vtp. As for inverter 1 And I2= Current for depletion mode pull up devices in saturation with Vgs=0 The output of inverter2 Vout2 is given by If the output of inverter 2 should be the same as that of inverter 1 under these conditions then Vout1 = Vout2 or I1R1=I2R2 Therefore Pull-up To Pull-down Ratio For an NMOS Inverter Driven Through One or More Pass Transistors
- 109. Taking typical values Therefore Summarizing for an nMOS inverter: • An inverter driven directly from the output of another should have a Zp.u./Zp.d,. ratio of ≥ 4/1. • An inverter driven through one or more pass transistors should have a Zp.u./Zp.d. ratio of ≥ 8/1. Pull-up To Pull-down Ratio For an NMOS Inverter Driven Through One or More Pass Transistors
- 110. Alternative Forms of Full-up Up to now we have assumed that the inverter circuit has a depletion mode pull- up transistor as its load. There are, however at least four possible arrangements: Load resistance RL (Figure 2.11 ). This arrangement is not often used because of the large space requirements of resistors produced in a silicon substrate
- 111. Alternative Forms of Full-up NMOS depletion mode transistor pull-up (Figure 1.12: • Dissipation is high ,since rail to rail current flows when Vin = logical 1. • Switching of output from 1 to 0 begins when Vin exceeds Vt, of p.d. device. • When switching the output from 1 to 0, the p.u. device is non-saturated initially and this presents lower resistance through which to charge capacitive loads
- 112. Dissipation is high since current flows when Vin =logical 1 (VGG is returned to VDD) . Vout can never reach V DD (logical I) if VGG = V DD as is normally the case. VGG may be derived from a switching source, for example, one phase of a clock, so that dissipation can be greatly reduced. If VGG is higher than VDD then an extra supply rail is required. NMOS enhancement mode pull-up · (Figure 2.13). Alternative Forms of Full-up
- 113. Complementary transistor pull-up (CMOS) (Figure 2.14). No current flow either for logical 0 or for logical 1 inputs. Full logical 1 and 0 levels are presented at the output. For devices of similar dimensions the p- channel is slower than the n-channel device. Alternative Forms of Full-up Fig 2.14 Complementary transistor pull-up (CMOS).
- 114. Alternative Forms of Full-up Fig 2.14 Complementary transistor pull-up (CMOS).
- 115. The CMOS Inverter A schematic circuit representation of the CMOS inverter is shown in fig 2.14. along with its transfer characteristics. Fig 2.14 Complementary transistor pull-up (CMOS).
- 116. The current/voltage relationships for the MOS transistor is given by the expression for Ids In the resistive region and for saturation region by The factor K depends on the geometry of the technology involved since The factor WIL is also contributed by the geometry and it is common practice to write Which gives for example The CMOS Inverter
- 117. In saturation, the factor β is applicable to both nMOS and pMOS transistors as follows Where Wn and Ln, WP and LP are the n- and p-transistor dimensions respectively. and µp and µn are the hole and electron mobility respectively. From Figures 2.14(b) and 2.14(c), we find that the CMOS inverter has five distinct regions of operation. The region 1 corresponds to operation when Vin=logic 0, the p-transistor fully turned on while the n-transistor is fully turned off. Thus no current flows through the inverter and the output is directly connected to VDD through the pull-up p-transistor. The output has a good logic 1 level. The CMOS Inverter
- 118. The CMOS Inverter CMOS inverter is divided into five regions of operation C Vout 0 Vin VDD VDD A B D E Vtn VDD /2 VDD +Vtp Region nMOS pMOS Region 1 (A) Cutoff Linear Region 2 (B) Saturation Linear Region 3 (C) Saturation Saturation Region 4 (D) Linear Saturation Region 5 (E) Linear Cutoff • In region C both Transistors are in saturation • Ideal transistors are only in region C for Vin=VDD/2 • The DC curve slope in region C is Infinity(∞) • The crossover point where Vin=Vout is called input threshold
- 119. In region 5: The inverted output corresponds to region 5 when Vin= logic 1, the n- transistor turned fully on while p-transistor is fully off. In this region again, no current flows through the circuit and a good logic 0 appears at the output. These two regions viz. region1 and 5 are the static conditions. In region 2: The input voltage has increased to a level which just exceeds the threshold voltage of the n-transistor. The n-transistor conducts and has a large voltage difference between source and drain is in saturation. • The p-transistor is also conducting but with only a small voltage difference between its drain and source and hence it operates in the unsaturated resistive region. The inverter circuits draws a small current from VDD to VSS . • If we wish to analyze the behavior in this region, we equate the p-device resistive region current with the n-device saturation current and thus obtain the voltage and current relationships. The CMOS Inverter
- 120. In the Region 4: Conditions are similar to region 2 but with the roles of the p- and n-transistors reversed. That is , p-transistor has a large voltage across it while the n-transistor has a small drop across it. • The current magnitudes in regions 2 and 4 are small and most of the energy consumed in switching from one state to the other is due to the larger current which flows in region 3. In the Region 3: Most of the energy consumed in switching from one state to the other is attributed to the large current flows in the region 3. This is the region of operation in which the inverter exhibits gain and in which both transistors are in saturation. Since the two transistor are in series , the current through them is same and we can write • Where The CMOS Inverter
- 121. Writing for Vin in terms of the β ratio and the other circuit voltages and currents In region 3, both transistors are in saturation, here they act as current sources so that the equivalent circuit in this region is two current sources in series between VDD and VSS with the output voltage coming from their common point. The region 3 is inherently unstable and changeover from one logic level to the other is rapid. The CMOS Inverter
- 122. This indicates that the changeover between logic levels is symmetrically set the point Corresponding to Vin=Vout=0.5VDD because only at this point the two β factors will be equal. But for βn=βp the device geometries should satisfy the condition that Now the mobility's of electrons and holes are inherently unequal and thus it is necessary for the width to length ratio (W/L) of the p-device to be two to three times that of the n-device • However, mobility µ is affected by the transverse electric field in the channel which is a function of Vgs. Thus mobility is depend on Vin. The mobility is given by the empirical relation. The CMOS Inverter
- 123. Where µz is the mobility with zero transvers field, φ a constant approximately equal to 0.05, Vt includes any body effect, and µz is the mobility with zero transverse field. Thus a β ratio of 1 will only hold good around the point of symmetry when Vout = Vin = 0.5VDD· By keeping minimum size geometry for both p- and n devices, effect β ratio is minimized . Variation of β causes transfer characteristic of the inverter to change as indicated in fig 2.15 . However, The changes indicated in the figure would be for quite large variations in β ratio (e.g. up to 10: 1) and the ratio is thus not too critical in this respect. The CMOS Inverter
- 124. Beta Ratio If βn/βp≠1, switching point will move from VDD/2
- 125. Beta Ratio
- 126. CMOS inverter Operation Cutoff Linear Saturated Vgsn < Vgsn > Vdsn < Vgsn > Vdsn > Idsn Idsp Vout VDD Vin NMOS Operation
- 127. Cutoff Linear Saturated Vgsn < Vtn Vgsn > Vtn Vdsn < Vgsn – Vtn Vgsn > Vtn Vdsn > Vgsn – Vtn Idsn Idsp Vout VDD Vin NMOS Operation CMOS inverter Operation
- 128. Cutoff Linear Saturated Vgsn < Vtn Vgsn > Vtn Vdsn < Vgsn – Vtn Vgsn > Vtn Vdsn > Vgsn – Vtn Idsn Idsp Vout VDD Vin Vgsn = Vin Vdsn = Vout CMOS inverter Operation NMOS Operation
- 129. Cutoff Linear Saturated Vgsn < Vtn Vin < Vtn Vgsn > Vtn Vin > Vtn Vdsn < Vgsn – Vtn Vout < Vin - Vtn Vgsn > Vtn Vin > Vtn Vdsn > Vgsn – Vtn Vout > Vin - Vtn Idsn Idsp Vout VDD Vin Vgsn = Vin Vdsn = Vout CMOS inverter Operation NMOS Operation
- 130. CMOS inverter Operation Cutoff Linear Saturated Vgsp > Vgsp < Vdsp > Vgsp < Vdsp < Idsn Idsp Vout VDD Vin PMOS Operation
- 131. Cutoff Linear Saturated Vgsp > Vtp Vgsp < Vtp Vdsp > Vgsp – Vtp Vgsp < Vtp Vdsp < Vgsp – Vtp Idsn Idsp Vout VDD Vin CMOS inverter Operation PMOS Operation
- 132. Cutoff Linear Saturated Vgsp > Vtp Vgsp < Vtp Vdsp > Vgsp – Vtp Vgsp < Vtp Vdsp < Vgsp – Vtp Idsn Idsp Vout VDD Vin Vgsp = Vin - VDD Vdsp = Vout - VDD Vtp < 0 CMOS inverter Operation PMOS Operation
- 133. Cutoff Linear Saturated Vgsp > Vtp Vin > VDD + Vtp Vgsp < Vtp Vin < VDD + Vtp Vdsp > Vgsp – Vtp Vout > Vin - Vtp Vgsp < Vtp Vin < VDD + Vtp Vdsp < Vgsp – Vtp Vout < Vin - Vtp Idsn Idsp Vout VDD Vin Vgsp = Vin - VDD Vdsp = Vout - VDD Vtp < 0 CMOS inverter Operation PMOS Operation
- 134. CMOS IDS-VDS Characteristics Make pMOS is wider than nMOS such that bn = bp Vgsn5 Vgsn4 Vgsn3 Vgsn2 Vgsn1 Vgsp5 Vgsp4 Vgsp3 Vgsp2 Vgsp1 VDD -VDD Vdsn -Vdsp -Idsp Idsn 0
- 135. CMOS Current versus Vout, Vin Vin5 Vin4 Vin3 Vin2 Vin1 Vin0 Vin1 Vin2 Vin3 Vin4 Idsn, |Idsp| Vout VDD
- 136. CMOS Load Line Analysis Vin5 Vin4 Vin3 Vin2 Vin1 Vin0 Vin1 Vin2 Vin3 Vin4 Idsn, |Idsp| Vout VDD • For a given Vin: • Plot Idsn, Idsp vs. Vout • Vout must be where |currents| are equal in Idsn Idsp Vout VDD Vin
- 137. MOS Transistor Circuit Model The MOS transistor can be modeled with varying degrees of complexity. a consideration of the actual physical construction of the device (as in Figure 2.16) leads to some understanding of the various components of the model CGC = Gate to channel capacitance CGS = Gate to source capacitance CGD = Gate to drain capacitance CSS = Source-to-substrate capacitance CDS= Drain-to-substrate capacitances CS =Channel-to-substrate capacitances.
- 138. BiCMOS Inverter BICMOS logic circuits are made by combining the CMOS and bipolar IC technologies. These ICs combine the advantages of BJT and CMOS transistors in them. We know that the speed of BJT is very high compared to CMOS. However, power dissipation in CMOS is extremely low compared to BJT. By combining such advantages, we construct the BICMOS circuits. The very approach of BiCMOS is to exploit the advantageous characteristics of bipolar and CMOS technologies. Hence in BiCMOS design the logical approach is to use MOS switches to perform the logic function and bipolar transistors to drive the output loads. The simplest logic function is that of inversion, and a simple BiCMOS inverter circuit is readily set out as shown in Figure 2.17
- 139. The inverter circuit consists of two bipolar transistors T1 and T2 with one nMOS transistor T3, and one pMOS transistor T4, both the MOS devices are being enhancement mode devices. The function of the circuit as follows • With Vin at logic 0 i.e. 0 Volts (GND) T3 is off which keep T1 non-conducting. But T4 is on and supplies current to the base of T2 which conduct and act as a current source to charge the load CL toward +5 volts (VDD). The output Vout goes to +5 volts less the base to emitter voltage VBE of T2. BiCMOS Inverter
- 140. • When Vin = logic 1 , i.e. +5 Volts (VDD), T4 is off so that T2 will be non-conducting. But T3 is on and supply current to the base of T1 which conduct and act as a current sink to the load CL which discharging through it to 0 volts (GND). • The output Vout of the inverter will fall to 0 volts plus the saturation voltage VCEsat between the collector and emitter of T1. • Charging and discharging of the load CL is very fast because transistor T1 and T2 present low impedances when turned on into saturation . BiCMOS Inverter
- 141. Characteristics of BiCMOS Inverter: • The output logic levels will be good and will be close to the rail voltages since V Cesar is quite small and V8E is approximately + 0.7 volts. • The inverter has a high input impedance. • The inverter has a low output impedance. • The inverter has a high current drive capability but occupies a relatively small area. • The inverter has high noise margins. However there is a constant D.C. path between the rails from VDD to GND through T3 and T1. Which allows a significant static current flow whenever Vin= logic 1. This is not a good arrangement. Also, there is another problem, that there is no discharge path for current from the base of either npn transistor when it s being turned off. This adversely affects the speed of action of the circuit. BiCMOS Inverter
- 142. An improved version of this circuit is given in Figure 2.18 The problem of the DC path trough T1 and T3 is eliminated in an improved inverter of this circuit is shown in Figure 2.18. Drawbacks: The output voltage swing gets reduced because the output cannot go below the base to emitter voltage VBE of transistor T1. BiCMOS Inverter
- 143. A further improvement in inverter arrangement circuit can be achieved using resistors as shown in Figure 2.19. In this circuit resistors provide an improved swing of output voltage when each bipolar transistor is off, and also provide discharge paths for base current during turn-off. Drawbacks: Fabricating resistors of suitable values is not always convenient and may occupy large space consuming. BiCMOS Inverter
- 144. An improved BICMOS inverter using MOS transistors for base current discharge arrangements are as shown in Figure 2.20. In this circuit shown in fig 2.20. arrangement is made to turn on transistors T5 and T6 when T2 and T1 respectively are being turned off. T5 gets turned on and provides discharge path for base circuit of T2. Thus we observe that BiCMOS inverters are more suitable where high load current sinking and sourcing is required FIG. 2.20 An Improved BICMOS Inverter using MOS transistors for base current discharge. BiCMOS Inverter
- 145. What is Latch up? • A problem which is inherent in the p-well and n-well processes is due to the relatively large number of junctions which are formed in these structures and consequent presence of parasitic transistors and diodes. • Latch-up is a condition in which the parasitic components give rise to the establishment of low-resistance conducting paths between VDD and VSS with disastrous results. Current can destroy chip • Latch-up may be induced by glitches on the supply rails or by incident radiation. The mechanism involved may be understood by referring to Figure 2.21 • which shows the key parasitic components associated with a p-well structure in which an inverter circuit has been formed. Latch-up In CMOS Circuits
- 146. Latch up occurs due to parasitic bipolar transistors that exist in the basic inverter as shown below Latch-up In CMOS Circuits
- 147. There are, in effect, two transistors and two resistances (associated with the p-well and with regions of the substrate) which form a path between VDD and VSS. If sufficient substrate current flows to generate enough voltage across RS to turn on transistor T1, this will then draw current through Rp and, if the voltage developed is sufficient, T2 will also turn on, establishing a self-sustaining low-resistance path between the supply rails. If the current gains of the two transistors are such that β 1 x β2 > 1, latch-up may occur. Equivalent circuits are given in Figure 2.22. With no injected current, the parasitic transistors will exhibit high resistance, but sufficient substrate current flow will cause switching to the low-resistance state as already explained. The switching characteristic of the arrangement is outlined in Figure 2.23. Once latched-up, this condition will be maintained until the latch-up current drops below I1. It is thus essential for a CMOS process to ensure that V1 and I1 are not readily achieved in any normal mode of operation. Latch-up In CMOS Circuits
- 149. Latch-up: Analysis The configuration of these bipolar transistors create a positive feedback loop, and will cause the logic gate to latch-up as shown to the right If VA>VDD+0.6, T1 will be turned ON. IC1 causes a voltage drop across RP If V (RP) > 0.6V V, T2 will be turned ON, this forces IC2 to be supplied by VDD through n+ substrate contact, then the bulk to p-well. Increase in voltage across RS causes and in increase in IC1, hence sustaining SCR action. The same action will take place when: VB< -0.6V Hence to prevent latch-up, limit the output voltage - 0.6< Vout < VDD+0.6V By using heavily doped material where Rn and Rp exist, there resistance will be lowered thereby reducing the chance of latchup occurring VB T1 VDD VSS VA T2 IE1 IC1 IB1 IB2 IC2 IE2 RS RP
- 150. Use Guard rings to remove the latchup problem i. N+ Ring for PMOS and connect it to VDD ii. P+ Ring for NMOS and connect it to GND Keep spacing between NMOS and PMOS Reducing R-sub and R-well i. Minimizing spacing between source and bulk ii. An increasing the substrate and N-well doping density iii. Using more number of source , substrate and N-well contacts. Wider Guard rings provides low resistive paths to minority Reduce the values of RN- and RP-. This requires more current before latch-up can occur. Surround the transistors with guard rings. Guard rings reduce transistor betas and divert collector current from the base of SCR transistors Latchup resistant CMOS processes – reduce the gain the parasitic transistors. Layout techniques - Use substrate contact to reduce Rn & Rp. Latch-up Prevention
- 151. latch-up configuration for an n-well structure
- 152. 152 1. Kamran Eshraghian, Eshraghian Dougles and A. Pucknell, ”Essential of VLSI Circuits and systems” 3rd Edition, PHI, 2005. 2. Wayne Wolf, ”Modern VLSI Design”, Pearson Education, 3rd Edition, 1997. 3. Weste and Eshraghian,”Principles of CMOS VLSI Design” , Pearson Education, 3rd Edition, 1999. NMOS Fabrication https://www.slideshare.net/SemiDesignSystem/nmos-fabrication-process-55111294?next_slideshow= 1 CMOS Fabrication https://www.slideshare.net/SemiDesignSystem/cmos-fabrication-process-55111271 https://www.slideshare.net/KANAGARAJT4/cmos-fabrication-71314286 REFERENCES
- 153. THANK YOU
Editor's Notes
- #8: Fairchild developed ICs based on Resistor-Transistor Logic On the Fairchild IC, the irregular black specks are imperfections in the chip's surface.