CMOS_Basics_PPT.pdf

EC303 CMOS VLSI Design
Dr. P. Sreehari Rao, Associate Professor (Section-A)
Dr. Vadthiya Narendar, Assistant Professor (Section-B)
Department of Electronics & Communication Engineering
National Institute of Technology Warangal
Warangal-506004

EC303 CMOS VLSI Design-Syllabus
Course Outcomes: After the completion of the course the student
will be able to:
CO1: Explain the fabrication, operation and characteristics MOSFET
CO2: Analyze the performance of CMOS inverter
CO3: Design digital circuits using CMOS gates
CO4: Design analog circuits using CMOS gates
CO5: Outline the latest trends in CMOS technology

Detailed Syllabus:
INTRODUCTION to MOSFETs: Unit process steps of CMOS
technology, Fabrication process flow: NMOS, PMOS, Twin well
CMOS; Structure and operation of the MOS transistor, I-V and C-
V characteristics, MOSFET capacitances, layout, design rules,
Scaling and Short channel effects.
MOS INVERTERS: Inverters with resistive, MOSFET load;
CMOS inverter: Voltage transfer characteristics, Noise margins,
switching characteristics, calculation of delay times; effect of load
on switching characteristics and driving large loads, logical effort
of paths

Digital circuits using CMOS: Pseudo NMOS, Pass transistor,
transmission gates, Dynamic logic, Domino logic, Differential
cascode voltage switch logic, design of combinational circuits,
design of sequential circuits, timing requirements.
Analog circuits: Second order effects in MOSFETs. Single stage
Amplifiers: Common-source stage, Source follower, Common-gate,
Cascode stage, Differential Amplifiers, Passive and Active current
mirrors, CMOS operational amplifier, gain boosting techniques.
Trends in CMOS technology: SOI, FinFET and multi-gate FET,
2D materials based FETs, On-chip interconnects.

Reading:
1. Sung-Mo Kang, Yusuf Leblebici Chulwoo kim, Digital Integrated
Circuits: Analysis and Design, 4th Edition, McGraw Hill Education,
2016.
2. Behzad Razavi, Design of Analog CMOS Integrated Circuits,
2nd Edition, McGraw Hill Education, 2016.
3. Jan M RABAEY, Digital Integrated Circuits, 2nd Edition, Pearson
Education, 2003.
4. Neil H.E. Weste and David Harris, CMOS VLSI Design: A circuits
and systems perspective, 4th Edition, Pearson Education, 2015.
5. J.-P. Colinge FinFETs and Other Multi-Gate Transistors,
Springer, 2007.

Evolution of VLSI
V Narendar
IC Products
• Processors
– CPU, DSP, Controllers
• Memory chips
– RAM, ROM, EEPROM
• Analog
– Mobile communication,
audio/video processing
• Programmable
– PLA, FPGA
• Embedded systems
– Used in cars, factories
– Network cards
• System-on-chip (SoC)

Electronics: The Big Picture
Figure: A VLSI system (Device to System)
V Narendar

Historical Perspective
V Narendar
 In the beginning of the twenty-first century, we find ourselves surrounded by
different machines and appliances that are impossible to build without applying the
principles of electronics onto them.
 Moreover, the communication boom that we see now would not have been possible
without the advancement in the electronics industry and without using integrated
circuits (ICs).
 The journey started when the first transistor was invented in 1947 by John Bardeen,
Walter Brattain, and William Shockley at the Bell Telephone Laboratory and they
shared the Nobel prize in 1956.
Vacuum Tubes First Transistor Inventors

V Narendar
 The biggest revolution happened when Jack Kilby at Texas Instruments first made
the monolithic integrated circuit in 1958. This was a significant breakthrough in the
semiconductor technology by Kilby, for which he was awarded Nobel Prize in
2000.
 The first commercial IC was introduced by Fairchild Corporation in 1960 followed
by TTL IC in 1962.
 Another breakthrough in the IC technology is the introduction of the first
microprocessor 4004 by Intel in 1971. Since then, there has been a steady progress
in the IC industry resulting in high density chips such as Pentium and Xeon
processors.

V Narendar

V Narendar
Evolution of integration level in integrated circuits

Evolution of VLSI
V Narendar
1925: Julius Edgar Lilienfeld’s MESFET patent
1935: Oskar Heil’s MOSFET patent
194?: Unpublished Bell Labs MESFET
1947: Ge BJT (Bardeen, Brattain, Shockley, Bell Labs)
1954: Si BJT (Teal, Bell Labs)
1960: MOSFET (Atalla&Khang, Bell Labs)
1961: Integrated circuit (Kilby, TI)
1963: CMOS (Sah&Wanlass, Fairchild)
1964: Commercial CMOS IC (RCA)
1965: DRAM (Fairchild)
1968: Poly-Si gate (Faggin&Klein, Fairchild)
1968: 1-FET DRAM cell (Dennard, IBM)
1971: UV EPROM (Frohman, Intel)
1971: Full CPU in chip, Intel 8008 (Faggin, Intel)
1974: Digital watch
1974: Scaling theory (Gänsslen&Dennard, IBM)
1978: Use of ion implanter
1978: Flotox EEPROM (Perlegos, Intel)
1980: Ion-implanted CMOS IC
1980: Plasma etching
1984: Scaling theory <0.25 μm (Baccarani, U. Bologna)
1986: 0.1 μm Si MOSFET (Sai-Halasz, IBM)
1991: CMOS replaces BJT also at high-end
1993: DGFET scalable to 30 nm (theory, Frank et al.)
2007: Non-SiO2 (HfO2–based) MOSFET (Intel)
1955: Si, Ge conduction band (Herring&Vogt)
Deformation-potential, high-field (Bardeen&Shockley)
1957: BTE in semiconductors – impurities (Luttinger&Kohn),
phonons (Price, Argyles)
1964: Band structure calculations (Hermann)
Monte Carlo for semiconductors (Kurosawa)
1965: Linear-parabolic oxidation model (Deal&Grove)
1966: Observations of 2DEG (Fowler, Fang, Stiles, Stern,..)
1967: Conductance technique (Nicollian&Goetzberger)
1974: DDE device simulator (Cottrell&Buturla)
1975: Quantum Hall Effect predicted (Ando)
1979: Quantum Hall Effect observed (von Klitzing)
1981: Identification of native Nit: Pb-centers (Poindexter)
Full-band MC (Shichijo&Hess)
1982: Fractional QHE observed (Störmer&Tsui, Laughlin)
1988: Full-band MC device simulator (MVF&Laux)
1992: NEGF device simulator (Lake, Klimeck, et al.)
Technology Physics/
Technology Physics/Simulations
Simulations

Technology Advancement
V Narendar

Scaling in Processor
V Narendar

Introduction
• Nowadays, digital electronics are pervasive across the globe enriching
people’s lives and making communication and sharing easier than ever.
• At the heart of the each of these digital devices are semiconductor chips
that provide the intelligence and power to drive the device.
• Each chip is made up with billions of transistors with complementary
metal-oxide semiconductor (CMOS) technology [1-3], the building blocks
of the digital world to build better digital devices and enhance the user
experience.

Introduction (cont’…)
• CMOS chips have become the core component of computers, mobile
phones, virtual reality (VR) machines and also revolutionized the military
and medical fields.
• The CMOS technology has now accomplished two extreme levels:
Gigascale and Nanoscale.
• The metal-oxide semiconductor field effect transistor (MOSFET) has been
considered as a fundamental element of CMOS technology which has been
used in a digital IC and follows the Moore’s law since five decades [4, 5].

Figure : Integration density of different generation of Intel microprocessors [8]
Moore’s Law and Technology Integration:

• International Technology Roadmap for Semiconductor [ITRS] [6] & IRDS.
• Every year, a new report has been created by the ITRS/IRDS in which they
define the benchmark rules for every technology nodes.
• To continue the downsizing of future technology nodes new device
architectures have been proposed by the researchers and shown a favorable
performance.
• Moreover, new technologies such as silicon on insulator (SOI), Strained
Silicon (S-Si) as a channel material, high-k dielectrics as a gate oxide
materials and with multiple gate structures have been investigated at
nanoscale regime.

a) High performance (HP): In High performance (HP) technologies, the high
density ICs requires high clock frequencies with acceptable power
consumption. Example: Desktop microprocessors.
b) Low operating power (LOP): The portable electronics need low operating
power (LOP) CMOS ICs with high performance.
c) Low stand-by power (LSTP): The cellular phones come under low stand-by
power technological options, where the requirements are low cost,
increasing functionality and power reduction is as low as possible.
Future Technology Options and their Requirements

Figure : The cross sectional view of an n-channel enhancement type MOSFET
MOSFET: Current-Voltage Characteristics
Basics of MOSFET

Basics of MOSFET
Two Terminal MOS Structure
M
O
S

Two-Terminal MOS Structure
Energy band diagrams of the components that
make up the MOS system
Energy band diagram of the combined MOS
system.

Two-Terminal MOS Structure
Example
Consider the MOS structure that consists of a p-type doped silicon substrate, a silicon
dioxide layer, and a metal (aluminum) gate. The equilibrium Fermi potential of the
doped silicon substrate is given as qϕFp= 0.2 eV. Using the electron affinity for silicon
(4.15 eV) and the work function for aluminum (4.1 eV), calculate the built-in potential
difference across the MOS system. Assume that the MOS system contains no other
charges in the oxide or on the silicon-oxide interface.
First, we have to calculate the work function for the doped silicon (qΦS), which is:
qΦS = qχsi + Ec — Ef
qΦS = 4.15eV + 0.75eV = 4.9eV
Solution
Now calculate the work function difference between the silicon substrate and the
aluminum gate
qΦMS = qΦM — qΦS
qΦMS = 4.1 eV - 4.9 eV = - 0. 8 eV

MOS System under External Bias
 Assume that the substrate voltage is set at VB = 0 V, and let the gate voltage be
the controlling parameter.
 Depending on the polarity and the magnitude of VG, three different operating
regions can be observed for the MOS system:
1. Accumulation
2. Depletion
3. Inversion.

 If a negative voltage VG is applied to the gate electrode, the holes in the p-type
substrate are attracted to the semiconductor-oxide interface.
 The majority carrier concentration near the surface becomes larger than the
equilibrium hole concentration in the substrate; hence, this condition is called carrier
accumulation on the surface.
 In this case, the oxide electric field is directed towards the gate electrode.
 The negative surface potential also causes the energy bands to bend upward near
the surface.
 While the hole density near the surface increases as a result of the applied
negative gate bias, the electron (minority carrier) concentration decreases as the
negatively charged electrons are pushed deeper into the substrate.
(Accumulation)

(Accumulation)
Figure: The cross-sectional view and the energy band diagram of the MOS
structure operating in accumulation region
M
O
S

(Depletion)
 A small positive gate bias VG is applied to the gate electrode.
 Since the substrate bias is zero, the oxide electric field will be directed towards
the substrate in this case.
 The positive surface potential causes the energy bands to bend downward near
the surface.
 The majority carriers, i.e., the holes in the substrate, will be repelled back into
the substrate as a result of the positive gate bias, and these holes will leave
negatively charged fixed acceptor ions behind. Thus, a depletion region is created
near the surface.
 Note that under this bias condition, the region near the semiconductor-oxide
interface is nearly devoid of all mobile carriers.

(Depletion)
structure operating in depletion mode, under small gate bias.

Depth of Depletion Region and Depletion
Region Charge Density

(Inversion)
o If the positive voltage further increased, i.e. VG > 0 (Large).
o As a result of the increasing surface potential, the downward bending of the
energy bands will increase as well.
o Eventually, the mid-gap energy level Ei becomes smaller than the Fermi level EFP
on the surface, which means that the substrate semiconductor in this region becomes
n-type.
o Within this thin layer, the electron density is larger than the majority hole density,
since the positive gate potential attracts additional minority carriers (electrons) from
the bulk substrate to the surface.
o The n-type region created near the surface by the positive gate bias is called the
inversion layer, and this condition is called surface inversion.

 The surface is said to be inverted when the density of mobile electrons on the
surface becomes equal to the density of holes in the bulk (p-type) substrate.
 This condition requires that the surface potential has the same magnitude, but the
reverse polarity, as the bulk Fermi potential ϕF .
 Once the surface is inverted, any further increase in the gate voltage leads to an
increase of mobile electron concentration on the surface, but not to an increase of
the depletion depth.
 Thus, the depletion region depth achieved at the onset of surface inversion is also
equal to the maximum depletion depth, xdm, which remains constant for higher gate
voltages.
 Using the inversion condition ϕs = - ϕF , the maximum depletion region depth at
the onset of surface inversion can be found from (11) as follows:
(13) (13)
(Inversion)

structure in surface inversion, under larger gate bias voltage
(Inversion)

MOSFET Terminal Voltages
Vg
Vs
Vd
Vgd
Vgs
Vds
+
-
+
-
+
-
 Mode of operation depends on Vg, Vd, Vs
Vgs = Vg – Vs
Vgd = Vg – Vd
Vds = Vd – Vs = Vgs - Vgd
 Source and drain are symmetric diffusion terminals
 By convention, source is terminal at lower voltage
 Hence Vds  0
 nMOS body is grounded. First assume source is 0 too.
 Three regions of operation
– Cutoff
– Linear
– Saturation

NMOS in Cutoff region
+
-
Vgs
= 0
n+ n+
+
-
Vgd
p-typebody
b
g
s d
• No channel
• Ids = 0
Vg
Vs
Vd
Vgd
Vgs
Vds
+
-
+
-
+
-

N-Channel MOSFET Characteristics
 The model assumes that the channel length is long enough that the
lateral electric field (the field between source and drain) is relatively low,
which is no longer the case in nanometer devices.
 The long-channel model assumes that the current through an OFF
transistor is 0.
 When a transistor turns ON (Vgs > Vt), the gate attracts carriers
(electrons) to form a channel.
 The electrons drift from source to drain at a rate proportional to the
electric field between these regions. Thus, we can compute currents if we
know the amount of charge in the channel and the rate at which it moves.

 MOS structure looks like parallel plate capacitor
 We know that the charge on each plate of a capacitor is Q = CV.
 Thus, the charge in the channel Qchannel
 Qchannel = C V = Cg (Vgc – Vt )
 C = Cg = eoxWL/tox = CoxWL
 V = Vgc – Vt = (Vgs – Vds/2) – Vt
n+ n+
p-typebody
+
Vgd
gate
+ +
source
-
Vgs
-
drain
Vds
channel
-
Vg
Vs
Vd
Cg
n+ n+
p-typebody
W
L
tox
SiO2 gateoxide
(goodinsulator, eox
=3.9)
polysilicon
gate
Vg
Vs
Vd
Vgd
Vgs
Vds
+
-
+
-
+
-
Cox = eox / tox
Vgc= (Vgs+Vgd)/2 = Vgs-Vds /2

 Each carrier in the channel is accelerated to an average velocity, v,
proportional to the lateral electric field, (the field between source and drain).
 v = mE (m is called mobility)
 The electric field E is the voltage difference between drain and source
Vds divided by the channel length L.
 E = Vds/L
 The time t required for carriers to cross the channel is the channel
length L divided by the carrier velocityv.
 t = L / v
 t = L2 / (mVds )

Now we know
How much charge Qchannel is in the channel
How much time t each carrier takes to cross
Therefore, the current between source and drain is the total amount of
charge in the channel divided by the time required to cross
channel
ox 2
2
ds
ds
gs t ds
ds
gs t ds
Q
I
t
W V
C V V V
L
V
V V V



 
  
 
 
 
  
 
 
ox
=
W
C
L
 

 The term Vgs – Vt arises so often that it is convenient to abbreviate it as
VGT. Ids describes the linear region of operation, for Vgs > Vt, but Vds
relatively small. It is called linear or resistive because when Vds << VGT, Ids
increases almost linearly with Vds, just like an ideal resistor.
 If Vgd < Vt, channel pinches off near drain
 When Vds > Vdsat = Vgs – Vt
 Now drain voltage no longer increases current
 
2
2
2
dsat
ds gs t dsat
gs t
V
I V V V
V V


 
  
 
 
 

 
2
cutoff
linear
saturatio
0
2
2
n
gs t
ds
ds gs t ds ds dsat
gs t ds dsat
V V
V
I V V V V V
V V V V



 

  
   
 

 


 


■ Shockley 1st order transistor models (long-channel)

Cross-sectional view and top view (mask view)
of a typical n-channel MOSFET

MOSFET Capacitances
• MOSFET Capacitance
- We group the various capacitances into two groups
1) Oxide Capacitances - capacitance due to the Gate oxide
2) Junction Capacitances - capacitance due to the Source/Drain
diffusion regions
Oxide Capacitances
Junctions Capacitances

Lumped representation of the parasitic
MOSFET capacitances
 Since the channel region is connected to
the source, the drain, and the substrate, we
can identify three capacitances between the
gate and these regions, i.e., Cgs, Cgd and Cgb
respectively.
 Cgs = Gate to Source capacitance
Cgd = Gate to Drain capacitance
Cgb = Gate to Body capacitance
Csb = Source to Body capacitance
Cdb = Drain to Body capacitance

Oxide-Related Capacitance
 It was shown earlier that the gate electrode overlaps both the source region and
the drain region at the edges.
 The two overlap capacitances that arise as a result of this structural arrangement
are called CGD (overlap) and CGS (overlap), respectively.
 Assuming that both the source and the drain diffusion regions have the same
width W, the overlap capacitances can be found as
CGS (overlap) = Cox W LD
CGD (overlap) = Cox W LD Cox = ℇox / tox
 Note that both of these overlap capacitances do not depend on the bias
conditions, i.e., they are voltage-independent.

(cut-off mode)
 In cut-off mode, the surface is not inverted. Consequently, there is no
conducting channel that links the surface to the source and to the drain.
 Therefore, the gate-to-source and the gate-to-drain capacitances are both equal
to zero: Cgs = Cgd = 0.
 The gate-to-substrate capacitance can be approximated by Cgb = Cox W L

(linear-mode)
 In linear-mode operation, the inverted channel extends across the MOSFET,
between the source and the drain.
This conducting inversion layer on the surface effectively shields the substrate
from the gate electric field; thus, Cgb = 0.
In this case, the distributed gate-to-channel capacitance may be viewed as being
shared equally between the source and the drain, yielding Cgs = Cgd = ½ (Cox W L )

(saturation mode)
 In saturation mode, the inversion layer on the surface does not extend to the
drain, but it is pinched as shown in below Figure.
The gate-to-drain capacitance component is therefore equal to zero (Cgd = 0).
Since the source is still linked to the conducting channel, its shielding effect also
forces the gate-to-substrate capacitance to be zero, Cgb = 0.
Finally, the distributed gate-to-channel capacitance as seen between the gate and
the source can be approximated by Cgs = 2/3 (Cox W L )

Oxide-Related Capacitance (Summary)
• Summary of Oxide-Related Capacitance
Cut-off Linear Saturation
D
ox
gd L
W
C
C sat



)
(
0
)
(

sat
gb
C
D
ox
gs L
W
C
C off
cut



 )
(
D
ox
gd L
W
C
C off
cut



 )
(
L
W
C
C ox
gb off
cut



 )
(
D
ox
ox
gs L
W
C
L
W
C
C sat







3
2
)
(
D
ox
ox
gs L
W
C
L
W
C
C linear







2
1
)
(
D
ox
ox
gd L
W
C
L
W
C
C linear







2
1
)
(
0
)
(

linear
gb
C

Junction Capacitance
 Junction Capacitance
- Junction Capacitance refers to capacitance between the diffusion regions of
the Source & Drain to the doped substrate surrounding them.
- They are called "junction" because these capacitances are due to the PN
junctions that are formed between the two materials
- We are concerned with the following junction capacitances:
Csb = Source to Body capacitance
Cdb = Drain to Body capacitance
- These capacitances are highly dependant on the bias voltages since the
effective distance between plates is the depth of the built in depletion region
that forms at the PN junction

Junction Capacitance
• Junction Capacitance
1) n+ / p junction = diffusion region to substrate beneath gate : Area = W·xj
2) n+ / p+ junction = diffusion region to channel-stop implant in back (sidewall) : Area = Y·xj
3) n+ / p+ junction = diffusion region to channel-stop implant on side (sidewall) : Area = W·xj
4) n+ / p+ junction = diffusion region to channel-stop implant in front (sidewall) : Area = Y·xj
5) n+ / p junction = diffusion region to substrate underneath : Area = W·Y

N-Channel MOSFET C-V Characteristics

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