IC Technology

IC Technology
Dr. Sachin D. Pabale
Matosri College of Engineering
and Research Centre, Nasik

The IC Market
The semiconductor industry is approaching $300B/yr in sales
Transportation
8%
Consumer Electronics
16%
Communications
24%
Computers
42%
Industrial
8%
Military
2%
Courtesy of Dr. Bill Flounders, UC Berkeley Microlab

IC Technology
What advantages do ICs have over discrete components?
 Size: Sub-micron vs. millimeter/centimeter.
 Speed and Power: Smaller size of IC components yields higher speed and
lower power consumption due to smaller parasitic resistances, capacitances
and inductances.
Switching between ‘0’ and ‘1’ much faster on chip than between chips.
Lower power consumption => less heat => cheaper power supplies =>
reduced system cost.
 Integrated circuit manufacturing is versatile. Simply change the mask to
change the design.
However, designing the layout (changing the masks) is usually the most
time consuming task in IC design.

IC Technology
Early developments of the Integrated Circuit (IC) go
back to 1949.
German engineer Werner Jacobi filed a patent for an IC
like semiconductor amplifying device showing five
transistors on a common substrate in a 2-stage
amplifier arrangement.
Jacobi disclosed small cheap of hearing aids.
Invention

Inventor Year Circuit Remark
Fleming 1904
1906
Vacuum tube diode
Vacuum triode
large expensive, power-
hungry, unreliable
William Shockley
(Bell labs)
1945 Semiconductor replacing
vacuum tube
Bardeen and
Brattain and
Shockley
(Bell labs)
1947 Point Contact transfer
resistance device “BJT”
Driving factor of growth
of the VLSI technology
Werner Jacobi
(Siemens AG)
1949 1st IC containing
amplifying Device
2stage amplifier
No commercial use
reported
Shockley 1951 Junction Transistor “Practical form of
transistor”
Jack Kilby
(Texas Instruments)
July 1958 Integrated Circuits F/F
With 2-T Germanium
slice and gold wires
Father of IC design

IC Technology
Inventor Year Circuit Remark
Noyce
Fairchild
Semiconductor
Dec. 1958 Integrated
Circuits
Silicon
“The Mayor of
Silicon Valley”
Kahng
Bell Lab
1960 First MOSFET Start of new era for
semiconductor
industry
Fairchild
Semiconductor
And Texas
1061 First Commercial
IC
Frank Wanlass
(Fairchild Semiconductor)
1963 CMOS
Federico Faggin
(Fairchild Semiconductor)
1968 Silicon gate IC
technology
Later Joined Intel to
lead first CPU Intel
4004 in 1970
2300 T on 9mm2
Zarlink
Semiconductors
Recently M2A capsule for
endoscopy
take photographs of
digestive tract 2/sec.

Cell Construction Layers
Product
Process
type
Line
width
(µm)
Transis
tors
(K)
Mask
layers Proc/bus
(bits)
Clock
(MHz)
Voltage
(V)
Cache
(Kbits)
Poly Metal
Die
size
(mm
)
1971 4004 PMOS 10 2.3 --- 4 0.108 12 0 1 1 13.5
1972 8008 PMOS 10 3.5 --- 8 0.2 12 0 1 1 15.2
1974 8080 NMOS 6.0 6.0 --- 8 2 12 0 1 1 20.0
1976 8085 NMOS 3.0 6.5 --- 8 0.37 5 0 1 1 20.0
1978 8086 NMOS 3.0 29 --- 16 5-10 5 0 1 1 28.6
1979 8088 NMOS 3.0 29 --- 16/8 5-8 5 0 1 1 28.6
1982 80286 CMOS 1.5 134 --- 16 6-12 5 0 1 2 68.7
1985 80386DX CMOS 1.5 275 10 32 16-33 5 0 1 2 104.0
1989 80486DX CMOS 1.0 1,200 12 32 25-50 5 0 1 3 163.0
1992 80486DX2 CMOS 0.8 1,200 --- 32 50-66 5 0 1 3 81.0
1993 Pentium BiCMOS 0.8 3,100 18 32/64 60-66 5 0 1 3 264.0
1994 80486DX4 CMOS 0.5 1,600 32 75-100 5 0 1 3
1995
Pentium
Pro
BiCMOS 0.35 5,500 20 32/64
150-
200
--- 0 1 4 310.0
1997 Pentium II CMOS 0.35 7,500 16 32/64
233-
300
--- 0 1 4 209.0
1998 Celeron CMOS 0.25 19,000 19 32/64
300-
333
--- 128 1 5
1999
Pentium
III
CMOS 0.18 28,000 21 32/64
500-
733
--- 256 1 6 140.0
2000 Pentium 4 CMOS 0.18 42,000 21 32/64
1,400-
1,500
--- 256 1 6 224

How semiconductor industry have achieved
the complex integrated circuits?
1. Moore’s Law.
2. Continuous technology Scaling.

Gordon E. Moore - Chairman Emeritus of Intel Corporation
 1965 - observed trends in industry - of transistors on ICs vs.
release dates:
Noticed number of transistors doubling with release of
each new IC generation
release dates (separate generations) were all 18-24
months apart
 Moore’s Law:
“The number of transistors on an integrated circuit
will double every 18 months”
 The level of integration of silicon technology as measured in terms
of number of devices per IC
 Semiconductor industry has followed this prediction with surprising
accuracy.
1965 - Moore's law
"Cramming more components onto integrated
circuits".

Transistor Scaling
 Until 1980’s technology was mixed, using nMOS,
pMOS, bipolar, and some CMOS.
 Supply voltage was not scaling, so power was rising.
 To reduce power, scale VDD.
 Even then power is growing, due to increased die
size, and fast frequency scaling

Transistor Scaling
130nm
90nm 65nm
45nm 32nm 22nm

1. Increase device packing density- reduces area
2. Improve frequency response α 1/L
3. Improve drive current
4. To improve power efficiency
Why do we scale MOS transistor?

Technology Scaling
Delay, Area, Cost and
Dynamic power
Static power
and Variability
issues
13

Scaling
Full Scaling (Constant Electric Field Scaling)
 In reality constant field scaling has not been observed strictly.
Since the transistor current is proportional to the gate
overdrive.
 High performance demands have dictated the use of higher
supply voltage.
 However, higher VDD implies increased power dissipation.
 Improved performance is due to the reduced capacitance.

Full Scaling
Classical Voltage scaling ended at 130nm

Fixed- Voltage Scaling
 Keeping voltage constant while scaling device
dimensions.
 Improved ION is due higher VDD.
 Fixed voltage scaling is comes with major power
penalty.
Hot carrier effect and oxide breakdown phenomena
compels supply voltage scaling.

General Scaling
• General scaling model dimensions are scaled by a
factor S, while voltage are reduced by a factor U.
• When voltage is held constant, U=1, the scaling
model reduces to the fixed-voltage model.
• Offers similar performance scenario identical to the
full-and fixed scaling models.

Changes in Scaling
Then >130nm
 Scaling drove down cost
 Scaling drove
performance
 Performance constrained
 Active power dominates
Now <45nm
 Scaling drives down cost
 Materials drive
performance
 Power constrained
 Standby power dominates
 Variability issues
 SCEs
 Need to indentify alternative
to Si and/or SiO2

Year Technology
node
Year
(Approxima
te)
Projected
Technology
node
1971 10µm 2014 14nm
1975 3µm 2016 10nm
1982 1.5µm 2018 7nm
1985 1µm 2020 5nm
1989 800nm
1994 600nm
1995 350nm
1998 250nm
1999 180nm
2000 130nm
2002 90nm
2006 65nm
2008 45nm
2010 32nm
2012 22nm
Semiconductor
Manufacturing Processes
Scaling of CMOS has driven
the tremendous growth of
semiconductor industry for
last four decades.

The Nanometer Size Scale
Carbon nanotube
MOSFET
Transistor
Scaling
22nm
Scaling cannot go on forever because transistors cannot be smaller than atoms

Transistor density and performance
100
1000
1995 2000 2005 2010
Gate
Pitch
(nm) 0.7x every
2 years
32nm
65nm
45nm
112.5 nm
1001000
Gate Pitch (nm)
Drive
Current
(mA/um)
0.0
0.5
1.0
1.5
2.0
1.0 V, 100 nA IOFF
45nm
32nm
65nm
90nm
NMOS
PMOS
130nm

Parameters Limiting further technology scaling
1. Increased Static power dissipation
2. Increased variability issues
3. Short channel effects

• Process
• Voltage
• Temperature
Variations
• Threshold voltage
• Oxide thickness
• Geometry parameters
Device
Characteristics
• ION/ IOFF
• Subthreshold
slope
• Drive Current
• Speed
Device
Performance
Circuit
Performance
Voltage and
Temperature
Process
Variability Issues
Variability issues are even more pronounce for nano - scale.
26

Discrete vs Integrated Circuit Design
Activity/Item Discrete circuits Integrated Circuits
Component Accuracy Well Known Poor absolute Accuracies
Bread boarding Yes No
Fabrication Independent Very dependent
Physical Implementation PC Layout Layout, verification and
Extraction
Parasitic Not important Must be included in the
design
Simulation Model Parameters well known Model parameters vary
widely
Testing Generally complete testing is
possible
Must be considered before
design
CAD Schematic capture
Simulation, PC Board layout
Schematic capture
Simulation, layout
Components All possible Active devices, capacitor,
and resistor

Why ICs?
 Size
 Speed
 Power
 Complexity
 Smaller size of IC components yields higher speed
and lower power consumption
 Integration reduces manufacturing cost

Integrated Circuit Classification
Circuit Technology
(BJT, BiCMOS, NMOS, CMOS)
Design Style
(Standard cell, Gate array, full Custom, FPGA)
Circuit Size
(SSI, MSI, LSI, VLSI, ULSI, GSI)

Circuit Technology
IC Technology
Bipolar CMOS BiCMOS SOI SiGe GaAs
Category BJT CMOS
Power
Dissipation
Moderate
to High
less
Speed Faster Fast
Gm 4ms 0.4ms
Switch
implementation
poor Good
Technology
improvement
slower Faster
Why
CMOS
?
Lower
Power
Dissipation
High
packing
density
Scale down
more easily
Fully
restored
logic levels
Appr.
Equal rise
and fall
time

ECL
 It is fastest bipolar circuit architecture available
today.
 It was the technology of choice for large mainframe
computers and supercomputers for many many years.
 Suffered from relatively high levels of power
consumption compared to CMOS technology.
 CMOS now offers speed approaching that of emitter-
coupled logic and also support much higher circuit
density and lower power consumption.
 However, high trans conductance of bipolar family
leads to develop BiCMOS.

BiCMOS
BJT
CMOS
BICMOS
Higher speed
High gain
Low out put resistance
Low power consumption
High input resistance
Simple construction and
scaling
Excellent properties for high-
frequency analog amplifiers
low-power logic gate
Fabrication challenges
Challenges in optimizing
parameters of both BJT and
CMOS
Amplifiers, analog power
management ckt.

SOI Technology
 Silicon on insulator (SOI) technology refers to the
use of a layered silicon-insulator-silicon substrate in
place of conventional silicon substrates.
 Reduces parasitic device capacitance, thereby
improving performance.

GaAs
 It is a III/V semiconductor, and is used in the manufacture of
devices such as microwave frequency integrated circuits.
 Some electronic properties of gallium arsenide are superior to
those of silicon. It has a higher saturated electron velocity and
higher electron mobility, allowing gallium arsenide transistors
to function at frequencies in excess of 250 GHz.
 GaAs logic circuits have much higher power consumption,
which has made them unable to compete with silicon logic
circuits.
 GaAs is not having its native oxide like SiO2 in case of Si.
 GaAs in contrast has a very high impurity density, which
makes it difficult to build ICs with small structures, suitable up
to (500nm)

IC Technology
Ref. Fairchild semiconductor_Logic selection guide

CMOS for logic
BiCMOS for I/O and driver circuits
ECL for critical high speed parts of the system.

Design Style
Issues of VLSI Design
Performance Cost Area Time –to-market
Different Design Style
Full
Custom
Standard
Cell
Gate Array FPGA

Full Custom Design
 Custom design involves the entire design of the IC, down to
the smallest detail of the layout.
 No restriction on the placement of functional blocks and
their interconnections
 Highly optimized, but labor intensive.
 Designer must be an expert in VLSI design
 Design time can be very long (multiple months)
 Involves the creation of a completely new chip
 Fabrication costs are high

Standard Cell Design
 Designer uses a library of standard cells:
an automatic place and route tool does the layout.
 Each standard cell contains a single gate of AND, OR,
NOT etc.
 Standard cells can be placed in rows and connected
with wires Routing done on “channels” between the
rows.
 All cells are the same height but vary in width.
 All cells have inputs and outputs on top or bottom of
cell.
 Design time can be much faster than full custom
because layout is automatically generated.

Gate Array Design
 Pre-fabricated array of gates (could be NAND).
(Gates already created on a wafer; only need to add the
interconnections)
 Entire chip contains identical gates
 normally 3- or 4-input NAND or NOR gates.
 10,000 – 1,000,000 gates can be fabricated within a single IC
depending on the technology used.
 Manufacture of interconnections requires only metal
deposition
 Fabrication costs are cheaper than standard cell or full
custom.
 The density of gate arrays is lower than that of custom IC’s
 This style is often a suitable approach for low production
volumes.

FPGA Design
 Pre-fabricated array of programmable logic and
interconnections.
 Programmable interconnects between the combinational logic,
flip-flops and chip Inputs and Outputs.
 Field Programmable devices are arrays of logic components
whose connectivity can be established with memory.
 No fabrication step required, avoid fabrication cost and time.
 Very good for prototype design because many FPGAs are
re-usable.

Flexible Circuit Design
FPGA
Reconfigured
No physical
layout design
lower NRE
cost
• Power
• Delay
Complex
Interconnect
structure
• PowerMemory
Requirement
• Chip
size
Complex
Architecture
Field Programmable Gate Arrays (FPGA) are also attracted
by subthreshold circuits. 42

FPGA Architecture
FPGA consists of
 Array of CLBs
 Programmable interconnect
resources
CLBs consists of
 N input LUT
 SRAM cells
 Flip flops
 Programmable interconnect
resources consists of
 Switch box
 Metal tracks
 Connection box
 Programmable routing
multiplexer
Programmable
Routing Switch
Short Wire
Segment
Programmable
Connection
Switch
Logic
Block
Long Wire
Segment
Switch
Block
Connection
Block
43

Design type
Analog, digital, or mixed signal
Digital Analog
Regular, hierarchical and
modular
Irregular
Designed at system level Designed at circuit level
Available synthesis EDA tool Hard to find synthesis tool
Shorter design time Longer design time
Less power consumption
Difficult to test

 Small scale integration(SSI) --1960
The technology was developed by integrating the number of transistors
of 1-100 on a single chip. Ex: Gates, flip-flops, op-amps.
 Medium scale integration(MSI) --1967
of 100-1000 on a single chip. Ex: Counters, MUX, adders, 4-bit
microprocessors.
 Large scale integration(LSI) --1972
of 1000-10000 on a single chip. Ex:8-bit microprocessors,ROM,RAM.
 Very large scale integration(VLSI) -1978
of 10000-1Million on a single chip. Ex:16-32 bit microprocessors,
peripherals, complimentary high MOS.
Integrated Circuits Based on transistor count

 Ultra large scale integration(ULSI)
The technology was developed by integrating the
number of transistors of 1Million-10 Millions on a
single chip. Ex: special purpose processors.
 Giant scale integration(GSI)
The technology was developed by integrating the
number of transistors of above 10 Millions on a
single chip. Ex:Embedded system, system on chip.

What is next?- SoC
 Fabrication technology has advanced to the point that
we can put a complete system on a single chip.
 Single chip computer can include a CPU, bus, I/O
devices and memory.
 This reduces the manufacturing cost than the
equivalent board level system with higher
performance and lower power.

System-on- Chip
A system on a chip or system on chip (SoC or SOC) is an
integrated circuits (IC) that integrates all components of a
computers or other electronics systems into a single chip.
It may contain digital, analog, mixed - signal, and often radio-
frequency functions—all on a single chip substrate
More compact system
Higher speed
Better reliability
Less expensive

SoCmicrocontroller,
microprocessor
ROM,RAM,
EEPROM and
flash memory
Timing sources
oscillator and
PLL
counters -
timers, and
power on reset
generators.
External interface
USB, Firewire,
Ethernet, USART,
SPI.
ADCs and
DACs.
Voltage
regulator and
power
management

Power Consumption
Dr. Sachin D. Pabale
Matoshri College of Engineering
and Technology

Motivation to estimate power dissipation
Sources of power dissipation
Metrics
Power optimization Techniques
Conclusion
Outlines

Moore’s Law
• Blessing of technology Scaling:
Transistor count get double every 2 years
• Direct consequence of technology scaling:
Power density of IC increases exponentially at each
technology generation.

Power Dissipation
CMOS technology is scaling to meet the
1. Performance
2. To reduce the cost
3. Power requirement
However, static power dissipation increases
considerably which is primarily due to the
flow of leakage currents.

Figure 2.1: Normalized dynamic and static power dissipation for (W/Lg=3)
devi e. Data is ased o the ITRS [ 6] a d or alized to the year ’s figure
[2].

Power
Dissipation
Performance
Cost
PortabilityPackaging
Reliability
Power dissipation affects:
Need to estimate power dissipation

1999 2002 2005 2008 2011 2014
0
50
100
150
200
Year
Power(Watts)
High performance microprocesssor chip
Hand held products
Figure 2.2: Power requirements of high performance
microprocessor chip and handheld products as per ITRS
[16].

KHz , nW
• RFIDs
• Biomedical Sensors
MHz, µW
• Embedded, ASICs
• Mobile electronics
GHz, W
• Servers
• Workstation
• Notebooks
Exploring Applications Space

Where does power goes in CMOS?
Dynamic power consumption
Short circuit power dissipation
Static/ leakage power
consumption

Power Consumption in CMOS
Leakage
reduces
Delay
Delay
DDscpeakleakDDleak
2
DD VftItfVIVf  loadtotal CP 
Pdynamic
PStatic Pshort-circuit

1. Dynamic power dissipation
VDD
Vin
VOUT
CL

Dynamic capacitive power and energy stored
in PMOS device
Case I: When input is at logic 0:
Power dissipation in PMOS is,
The current and voltages are related by,
CL
VDD
Vin
VO
VSD
)( ODDLSDLP VViViP 
dtdvCi oLL /
Similarly, energy dissipation in the PMOS,

Case II: when the input is high and
output is low.
During switching all the energy stored in the load
capacitor is dissipated in the NMOS device is
conducting and PMOS is in cutoff mode. The
energy dissipation in the NMOS inverter can be
written as,
VO
CL
VDD
Vin
2
222
2
2
1
2
1
2
1
DDLT
T
T
DDLDDLDDL
DDL
VfCfEP
t
E
PPtE
VCVCVCENEPET
VCEN




• Power dissipation in terms of frequency,
• Above equation shows that the power dissipation in
the CMOS inverter is directly proportional to
switching frequency and VDD.
2
2
DDLT
T
T VfCfEP
t
E
PPtE 
 
dynamic
0
0
sw
2
sw
1
( )
( )
T
DD DD
T
DD
DD
DD
DD
DD
P i t V dt
T
V
i t dt
T
V
Tf CV
T
CV f







Dynamic capacitive power
• Dynamic power:
Observations:
 Does not depends on device size
 Does not depends on switching delay
 Applies to general CMOS gate in which,
• Switch cap. are lumped into CL
• Output swing from GND to VDD
• Gate switches with frequency f
2
DDLdynamic VfCP 

Lowering Dynamic Power
2
DDLdynamic VfCP 
Function of fan-out,
wire length, transistor
sizes
Supply Voltage:
Has been reduced with
successive generation
Clock frequency
Increasing…..

10
0
10
2
10
4
10
-11
10
-10
10
-9
10
-8
10
-7
10
-6
10
-5
Frequency (KHz)
Powerdisspation(W)
VDD=0.35V
VDD=0.4V
VDD=0.9V
VDD=1.2V
superthreshold
regime
Subthreshold
regime
Figure 2.13: Power dissipation as a function of
operating frequency.
Power as function of Frequency

 Finite slope of input signal causes a
direct current path between VDD and
GND for short period of time.
 i.e. Short circuit current flows from
VDD to GND when both transistors
are on.
Short Circuit Power Consumption
VDD
Vin VOUT
CL

Vin
Vth
VDD - Vth
t
I short
I max
0 50 100 150 200 250 300 350 400
0
100
200
300
400
0 50 100 150 200 250 300 350 400
0
1000
2000
3000
4000
Input voltage (mV)
Outputvoltage(mV)
Current(pA)
Vout short circuit leakage
Transition
32nm NMOS
VDD=0.4V
Figure 2.4: Short circuit leakage
current of inverter at 32 nm technology
node and VDD=0.4V.

• Approximate short circuit current as triangular
wave.
• Energy per cycle,
2
222
max
max
maxmax
fr
DDSC
fr
DD
r
DD
r
DDSC
tt
fIVP
tt
IV
tI
V
tI
VE





Short Circuit Current Determines
10 fIVtP peakDDscSC
• Duration and slope of the input signal, tsc
Ipeak determined by,
 The saturation current of the P and N transistors
which depends on their sizes, process technology,
temperature, etc.
 Strong function of the ratio between input and output
slopes
• a function of CL

Impact of CL on PSC

VDD
Vin
VOUT
CL
Large Capacitive Load
ISC≈ 0
VDD
Vin VOUT
CL
Small Capacitive Load
ISC≈ Imax
Short circuit dissipation is minimized by matching the
rise/ fall times of the input and output signals.

As capacitive load increases short circuit power
decreases

Static Power Dissipation
• The static power is defined as the power consumption due to
constant current from VDD to ground in the absence of switching
activity.
• Shrinking transistor geometries causes different sources of
leakage current [16].
punchthrough
Gate
B D
Sub-threshold
p-n junction
p-n junction
p-well
p+
Gate leakage
S
GIDL leakage
n+ n+
Substrate
punchthrough
Gate
B D
Sub-threshold
p-n junction
p-n junction
p-well
p+
Gate leakage
S
GIDL leakage
n+ n+
Substrate

• Sources of static power dissipation
Reverse bias pn- junction current
Subthreshold leakage current
Gate leakage current
Gate-Induced Drain Leakage current
 Punchthrough Leakage current
Static Power Dissipation

1. Reverse bias pn- junction current is flowing
due to,
minority carrier diffusion/drift near the edge of
the depletion region;
electron-hole pair generation in the depletion
region of the reverse-biased junction [12].
The magnitude of the diode’s leakage current
depends on the area of the drain diffusion and
the leakage current density.

• In the presence of a high electric field (4106
V/cm) electrons will tunnel across a reverse-
biased p–n junction.
• Process technologies are generally well
designed to keep this pn-junction leakage
small relative to the subthreshold current.

2. Subthreshold leakage Current
• Subthreshold or weak inversion conduction
current between source and drain in an MOS
transistor occurs when gate voltage is below
[15].
)(
DSV)DSVthVGSV(
TUTnU
0DsubD e1eIII















 





 




TT
2
T
s
cheffsi
eff
eff
subD
U
1
nU
U
2
Nq
L
W
II DSthGS V
exp
VV
exp

0 100 200 300 400 500 600 700 800 900
10
-3
10
-2
10
-1
10
0
10
1
10
2
VGS (mV)
DrainCurrent(uA)
IOFF
Vth=0.49V
Subthreshold region Superthreshold region
Isub
VGS <Vth
L
n+ n+
p-Substrate
S
VDS<Vth
TOX
D
Isub
NMOS transistor with bias voltages.I-V characteristics of NMOS transistor.
Subthreshold leakage Current

3. Gate leakage current
• As technology scales down, the oxide thickness gets
thinner which causes high electric field across the
oxide.
• As TOX scales below 3 nm, gate to channel leakage
current starts to appear even at low gate voltage. That
results in direct tunneling of electrons from substrate to
gate and gate to substrate through the gate oxide.

Gate leakage current









OX/OXV
)2/3)OX/OXV1(1(B
exp2)
oxT
oxV
(AeffLeffWgateI
oxh16
3q
A


hq3
2/3
oxm24
B


The gate leakage expressed in [32] is given by equation as follows,
where ‘VOX’ is the potential drop across the thin oxide layer, ‘
is the barrier height for the tunneling particles, ‘TOX’ is the oxide
thickness, ‘A’ and ‘B’ are physical parameters.
‘
ox
Gate tunneling current has very strong dependence on the voltage
across the gate.

4. Gate induced drain leakage
• In the overlapping zone between gate and
drain, a high electric field exists, leading to the
generation of current from the edge of drain
and terminating at the body of the transistor.
• Thinner oxide thickness and higher potential
between gate and drain enhance the electric
field and therefore increase GIDL.

5. Puchthrough leakage current
• In short-channel devices, the depletion regions at the
drain-substrate and source-substrate junctions extend
into the channel.
• As the channel length is reduced, if the doping is kept
constant, the separation between the depletion region
boundaries decreases.
• When the combination of channel length and reverse
bias leads to the merging of the depletion regions,
punchthrough is said to have occurred.

Inverter Power consumption
• Total Power consumption
leakDD
fr
DDDDLtot
statscdyntot
IVf
tt
IVfVCP
PPPP




)
2
(max
2

Power Reduction
1. Dynamic Power
 Lower the voltage
 Reduce capacitance
 Reduce frequency
2. Reducing short-circuit current
 Fats rise/ fall time on input signal
 Reduce input capacitance
Insert small buffers to clean up slow i/p
3. Reducing leakage current
Small transistors (leakage proportional to width)
 Lower voltage

Power Optimization Methodology
 Multiple VDD
 Multiple VDD -Multiple Vth
 Gate sizing
 Transistor sizing
 Power gating
 Transistor stacking and sleepy stacking
 Multi-threshold architectures
 Adaptive body biasing

Dual Power Supply
Dual Power Supply
lowering the VDD along non-critical
delay paths or light workloads and
higher VDD for heavy workloads .
The main problem of designing dual
VDD in CMOS circuits is the increased
leakage current in the high voltage
gates, when a low voltage gate is
driving them.
VDDL
Vin
Static current
VOut
Static current
VDDHVDDL
Vin
Static current
VOut
Static current
VDDH

Gate and Transistor sizing
• For non critical path reduce device size to
minimize the power consumption.
• In Gate sizing techniques all transistors in gate
is having size.
• In transistor sizing, within a gate transistors
may have different size to maximize the power
saving.

Leakage Power Reduction Techniques
Power Gating and Multi-
Threshold Voltage
 In the ACTIVE mode, the sleep
transistor is ON.
 In the STANDBY mode, the sleep
transistor is turned OFF.
____
Sleep
Sleep
Virtual VDD
Virtual Ground
In Out
P
N
____
Sleep
Sleep
Virtual VDD
Virtual Ground
In Out
P
N
“Higher Vth devices are preferred for sleepy
transistors to reduce leakage current.” -
Multi-threshold architecture

VDD
VDDV
Standby
Bypass
capacitance
High-Vth sleep
transistor
Low-Vth logic
Transistor
GND
Power Gating and Multi-Threshold Voltage
MTCMOS Logic

1. Adaptive Body Bias
 Increase the threshold voltage of
transistors in the STANDBY state –
RBB technique.
 Can be applied at chip level or block
level. Block level is most commonly
preferred.
 FBB technique can be used to reduce
VTh and hence delay in active mode.
Leakage Power Reduction Techniques
)|2||2|( FSBF VVthoVth  
Gnd Active
Standby< Gnd
> Gnd
VDD
Active
Standby> VDD
< VDD
Control
Loop
Gnd Active
Standby< Gnd
> Gnd
VDD
Active
Standby> VDD
< VDD
Control
Loop
Control
Loop

Dynamic supply voltage scaling schemes
• Uses variable supply voltage and speed tech.
• The highest supply voltage delivers the highest
performance at the fastest designed frequency of
operation.
• When performance demand is low, supply voltage
and clock frequency is lowered, just delivering the
required performance with substantial power
reduction [41].

DVS system
• Processor speed is controlled
by software program
automatically
• Supply voltage is controlled
by hard-wire frequency–
voltage feedback loop, using
a ring oscillator as a critical
path replica.
• All chips operate at the same
clock frequency and same
supply voltage, which are
generated from the ring
oscillator and the regulator.

Higher oxide thickness.
• To obtain high Vth devices
• To reduce subthreshold leakage current
• To reduce gate tunneling leakage current
• However, in case of severe SCE an increase in the oxide
thickness will increase the subthreshold leakage.
• In order to suppress SCE, the high tox device needs to
have a longer channel length as compared to the low tox
device [47]
• Advanced process technology is required for fabricating
multiple tox CMOS.

Clock gating
• Clock gating is an effective way of reducing the dynamic
power dissipation in digital circuits.
• In a typical synchronous circuit such as the general purpose
microprocessor, only a portion of the circuit is active at any
given time. Hence, by shutting down the idle portion of the
circuit, the unnecessary power consumption can be
prevented.
• This prevents unnecessary switching of the inputs to the
idle circuit block, reducing the dynamic power.

Subthreshold Operating region
Low voltage of Operation

Power Consumption
Power consumption has become a significant
hurdle for recent ICs
Higher power consumption leads to
• Shorter battery life
• Higher on-chip temperatures – reduced
operating life of the chip
• Such applications are ideal candidates for sub-
threshold circuit design.
• OK, so what is sub-threshold design??
There is a large and growing class of applications where
power reduction is paramount – not speed.

Ultra Low Power Circuit Design
Need:
 Power aware design increases considerably due to
remarkable growth of portable applications.
 Remarkable power requirement gap between high
performance microprocessor chip and portable device.
 Increased leakage power density can not be ignored in
case of portable devices.
 To enhance the battery life time
KHz , nW
RFIDs tags
Biomedical Sensors
etc
• Designing
Subthreshold
Circuits
How to
satisfy
ULP
demand?

Minimum Operating Voltage
• Swanson and Meindl (1972) examined the VTC of an
inverter:
 Minimum Voltage = 8kT/q or 200 mV at 300K
(A ring oscillator worked at 100 mV soon thereafter.)
• Ideal limit of the lowest possible supply voltage (2001) :
VDD = 2kT/q ≈ 57 mV at 300K
• R. M. Swanson and J. D. Meindl, “Ion-Implanted Complementary MOS
Transistors in Low-Voltage Circuits,” IEEE JSSC, vol. 7, no. 2, April 1972.
• A. Bryant, J. Brown, P. Cottrell, M. Ketchen, J. Ellis-Monaghan, E. Nowak, I.
Div, and E. Junction, “Low-power CMOS at Vdd= 4kT/q,” in Device Research
Conference, 2001, pp. 22–23.

Subthreshold Regime (VDD<Vth)
VGS
<Vth
L
n+ n+
p-
Substrate
S
VDS<Vth
TOX
D
Isub
0 100 200 300 400 500 600 700 800 900
10
-3
10
-2
10
-1
10
0
10
1
10
2
VGS (mV)
DrainCurrent(uA)
IOFF
Vth=0.49V
Subthreshold region Superthreshold region
Isub
Fig. 2.7 I-V characteristics of NMOS
transistor
Fig. 2.6 NMOS transistor with bias
voltages













 





 




TT
2
T
s
cheffsi
eff
eff
subD
U
1
nU
U
2
Nq
L
W
II DSthGS V
exp
VV
exp

Sub-Threshold Regime
Supply
Voltage Leakage Energy
Dissipation
Circuit Delay
Switching
Energy
Exponentially
2
total load DDE C V
total leak DD leakE I V t
/( )
0
DD t
DD DD
leak V nU
on
CV CV
t
I I e
 













 





 




TT
2
T
s
cheffsi
eff
eff
subD
U
1
nU
U
2
Nq
L
W
II DSthGS V
exp
VV
exp
Subthreshold
regime
VDD< VTh
Exponentially
Quadretically

Sub-Threshold Regime
Benefits
 High transconductance gain
 Near-ideal Voltage Transfer
Characteristics (VTCs)
 Ultra low power
consumptions
Challenges
 Re-claiming the speed penalty
 Increased sensitivity to PVT
variations due to exponential
I–V characteristics
 Energy minimization in sub-
threshold circuits
 To develop subthreshold
device library files
These challenges leads us to design “Robust Subthreshold
Circuits with Moderate Speed”

Integrated Circuits
Basic Components
Active devices Interconnects
Local (short)
interconnect
Global (Long)
interconnect

VLSI Interconnects
 Used to connect components on a VLSI chip
 Used to connect chips on a multichip module
 Used to connect multichip modules on a system
board

Wires on chip
• Most of the chip is covered by
wires, many layers of wires
• Transistors: little things under wires
• Wires as important as transistors
Affect:
 Speed
 Power
 Noise
• Alternating layers usually run
orthogonally
Most of chip is wires
(interconnect)

• In past history of integrated circuits, on-chip interconnect
wires were considered to be second class citizens.
• only to be considered in special cases or when performing
high-precision analysis.
• With the progress semiconductor technologies, this picture is
undergoing rapid changes.

85% 15%
50% 50%
20% 80%
Mid 1980’s
Gate delay dominates,
Mid 90
Gate delay and wire
delay
Today
Mostly wire delay

Figure 4.4: Breakdown of (a) delay and (b) energy
in simulation of FPGA at 0.4V subthreshold voltage
[7].

Why Al
• Low cost, easily purified
• Low resistivity
• Good adherence to Si and SiO2
• Good patternability
• Ease of deposition

The wiring forms a complex geometry that introduces
parasitics: resistive, capacitive and inductive.
All three have multiple effects on the circuit behavior.
 An increase in propagation delay, or, equivalently, a
drop in performance.
 An impact on the energy dissipation and the power
distribution.
 An introduction of extra noise sources, which affects
the reliability of the circuit.

Problem with Al
• Device Dimension Decreased
Current Density Increases
Decreased reliability
(Electronics, shorting between level of Al
Solution
• Alternative Metal/ Metal Composite – Cu is preffered
in modern process- CNT will prefer in future

Metallic Interconnections Issues
Parasitic Capacitances and Inductances
 Reduction of Propagation Delays
 Reduction of Crosstalk Effects
 Reduction of Electromigration-Induced Failure

CMOS inverter driving interconnect
The delay for RC Cu
interconnect driven by a
CMOS driver is given by
[129],
l)C.RC.R(
lC.R4.0)CC(R
loadWWdriv
2
WWloaddrivdrivd



Interconnect scaling trends
Ideal scaling Constant dimension
Line width/spacing S 1
Wire thickness S 1
Interlevel dielectric S 1
Wire length 1/sqrt(S) 1/sqrt(S)
Resistance/unit length 1/S2 1
Capacitance/unit length 1 1
RC delay 1/S3 1/S
Current density 1/S S

• Pitch= w + s
• Aspect Ratio,
AR=t/w
Modern process have
AR=2 for short
AR=3 for long
interconnect
Ground
Ground
W
S
H
t
Wire geometry
l
w s
t
h

Wire_Resistance
• The resistance of a wire is proportional to its length L
and inversely proportional to its cross-section A.
HW
L
A
L
R


H
R
W
L
RR






Wire capacitance
1. Area component ( Also referred to as parallel plate
capacitance components)
2. Fringing field component
3. Wire- to-wire capacitance components
To improve delay
 Increase dielectric thickness
 Reduce wire width
 Reduce spacing

1. Parallel plate capacitance
For w >> tdi (thickness of insulating material) it is
assumed that the electrical field lines are orthogonal
to the capacitance plates.
WL
t
C
di
di
int

Fringing capacitance
• In modern process W/H ratio drops down
significantly.
• It causes capacitance between side walls of
wire and substrate, called fringing capacitance.
• It can no longer be ignored.
2/,
)/log(
2.
HWwwhere
Htt
w
CCC
di
di
di
di
fringppWire




Capacitance as function of W and tdi
@From Schaper83
W/tdi indirectly W/H

Inter wire capacitance
• Interlayer capacitance is
more dominant in multilayer
structure. This effect is more
pronounce for wires in the
higher interconnect layers.

Propagation Delays
Definitions
Delay Time
• Time required by the output signal (current or
voltage) to reach 50% of its steady state value
Rise Time
• Time required by the output signal to rise from 10%
to 90% of its steady state value
Propagation Time
• Time required by the output signal to reach 90% of its
steady state value

24
The Lumped Model
Vout
Driver
cwire
Vin
Clumped
Rdriver
V
out
Paracitics of wires are distributed along its length.
But, when signle paracitic components is dominant
it is oftenly useful to consider lumped model.
For small resistive components, low to medium
frequency range only capacitance component can be
considered.
Distributed capacitance can be lumped into single
capacitor.

The Lumped RC-Model
The Elmore Delay
To model propagation delay
time along a path from the
source s to destination i
considering the loading effect
of the other nodes on the path
from s to k
The shared path resistance Rik
s
The Elmore delay

• Wires are a distributed system
– Approximate with lumped element models
 3-segment p-model is accurate to 3% in simulation
 L-model needs 100 segments for same accuracy!
C
R
C/N
R/N
C/N
R/N
C/N
R/N
C/N
R/N
R
C
L-model
R
C/2 C/2
R/2 R/2
C
N segments
-model T-model

29
Driving an RC-line
V
in
Rs Vout
(rw,cw,L)

30
Design Rules of Thumb
 rc delays should only be considered when tpRC >>
tpgate of the driving gate
Lcrit >>  tpgate/0.38rc
 rc delays should only be considered when the rise
(fall) time at the line input is smaller than RC, the
rise (fall) time of the line
trise < RC
otherwise, the change in the input signal is slower than
the propagation delay of the wire

• Capacitance as function of AR
1 1.5 2 2.5 3
400
500
600
700
800
900
1000
Aspect Ratio
Capacitance(fF)
Opt.mixed CNT bundle
Mixed CNT bundle [94]
Cu
L=5000um 50
100
150
200
250
300
48 72 96 120 144
Spacing (nm)
Driverandtotaldelay(ns) 8
16
24
32
40
Interconnectdelay(ns)
Total delay Driver delay Inter.delay
Delay as function of spacing

PDP as function of interconnect length
2
4
6
8
10
0
10
20
30
40
0
10
20
30
40
50
60
Interconnect length
(mm)1 x min. driver width
PDP(fJ)
Superthreshold regime
Subthreshold regime

Delay as function of interconnect width
40
60
80
100
120
0
5
10
15
20
10
0
10
1
10
2
10
3
Interconnect width (nm)
Min. X driver size
Delay(ns)
Conv. device and interconnect
Opt. device and interconnect
40
60
80
100
120
0
5
10
15
20
10
-1
10
0
10
1
10
2
Interconnect width (nm)Minimum X driver size
PDP(J)
Conv. interconnect and device
Opt. interconnect and device

Interconnect Techniques
Cin Cpar. Cload
InterconnectDriver Receiver
Cpar.
InterconnectTapered Driver Tapered Receiver
CloadCin
(a)
(b)
©
Driver Receiver
Interconnect Interconnect Interconnect
Repeater RepeaterCin Clo
ad
Driver Sizing
Tapered Driver
Repeater Insertion
34

Repeaters
 R and C are proportional to l
 RC delay is proportional to l2
Unacceptably great for long wires
 Break long wires into N shorter segments
Drive each one with an inverter or buffer
Wire Length: l
Driver Receiver
l/N
Driver
Segment
Repeater
l/N
Repeater
l/N
ReceiverRepeater
NSegments

Interconnect Slide 36
Repeater Design
• How many repeaters should we use?
• How large should each one be?
• Equivalent Circuit
– Wire length l
• Wire Capacitance Cw*l, Resistance Rw*l
– Inverter width W (nMOS = W, pMOS = 2W)
• Gate Capacitance C’*W, Resistance R/W
R/W
C'WCw
l/2N Cw
l/2N
Rw
lN

Crosstalk
• The crosstalk coupling represents the parasitic
transient voltage induced by a switching interconnect
on a neighboring interconnect.
• Crosstalk is the interference in a victim line signal
transmission caused by switching activity on
aggressor lines
• As integration density of on chip interconnect
increases at every technology node, the crosstalk
effect becomes more pronounced [132].
• Strongly depends on the value of the coupling
capacitance (Cc), transition-time skew and the
adjacent interconnect length

• In order to keep crosstalk minimum, the capacitance
between two wires should not be too large [27].
• This is feasible by breaking a long interconnect by
inserting intermediate buffers.
• Another approach of reducing the crosstalk is to use
shielding wires.
Crosstalk

Aggressor 1
CloadCw
Rw Lw
Cc
Rw Lw
Cw Cload
Rw Lw
Cw Cload
Aggressor 2
Victim Cc
Figure 5.19: Schematic of equivalent circuit
to model crosstalk between adjacent wires.
layer n+1
layer n
layer n-1
Cadj
Ctop
Cbot
ws
t
h1
h2

Crosstalk noise
• Crosstalk causes noise on nonswitching wires
• If victim is floating:
– model as capacitive voltage divider
adj
victim aggressor
gnd v adj
C
V V
C C
  

Cadj
Cgnd-v
Aggressor
Victim
Vaggressor
Vvictim

Driven Victims
• Usually victim is driven by a gate that fights noise
– Noise depends on relative resistances
– Victim driver is in linear region, agg. in saturation
– If sizes are same, Raggressor = 2-4 x Rvictim
1
1
adj
victim aggressor
gnd v adj
C
V V
C C k
  
 
 
 
aggressor gnd a adjaggressor
victim victim gnd v adj
R C C
k
R C C





 

Cadj
Cgnd-v
Aggressor
Victim
Vaggressor
Vvictim
Raggressor
Rvictim
Cgnd-a

Figure: Snapshot of signal transition due to
aggressor transitions for Cu interconnect.

Snapshots of voltages across victim wire
due to aggressors transitions.

5. Effect of Crosstalk on Interconnect Performance
Aggressor
Transition
Victim
Transition
Rise
Time
(ns)
Fall Time
(ns)
Delay
(ns)
PDP (fJ)
RLC Power
(nW)
Without
Aggressors
Low to high 256.7 285.2 270.9 60.64 17.35
High to low 242.2 286.14 264.2 59.16 15.9
Low to high Low to high 256.7 285.2 270.98 60.64 17.35
High to low High to low 242.2 286.14 264.2 59.16 15.9
Low to high High to low 394.9 380 387.9 110.2 25.58
High to low Low to high 257 479 368.4 104.88 22.66
Low to high Held at low Results in rise glitch on victim
High to low Held at low Results in undershoot on victim
Table : Effect of crosstalk on interconnect performance (L=10 mm).
45

Classification of CNTs
MWCNT
Dmax
Dmin
SWCNT
d
Mixed CNT
Bundle
(a) (b) (c)
Figure (a) Single-wall carbon nanotubes, (b) Multi-wall carbon nanotubes
and (c) Mixed CNT bundle
47
Carbon Nanotubes (CNTs)

Single-Wall Carbon Nanotubes (SWCNT)
 SWCNT: Single sheet of cylindrically rolled graphene
: diameter in nanometer range
 Depending upon rolling (chiralities) it produces either
metallic CNT or semiconducting CNT.
y
d
SWCNT
Ground Plane
4CQ
CE
(Rc+RQ)/2R/2(Rc+RQ)/2 R/2 L/2L/2
48
Fig. Equivalent RLC circuit of
SWCNT

SWCNT_ Resistance
• The resistance of a SWCNT (RCNT) consists of
 Quantum resistance (RQ) / an intrinsic resistance
 Contact resistance (RC). (20 to 120 kΩ [94])
 k5.6e4/hR 2
Q
For longer length, SWCNT resistance depends on its length
and applied voltage.
 k5.6e4/hR 2
CNT CNTl
)/(/  CNT
2
CNT le4hR CNTl
49
)/( 0CNTQCCNT ll1RRR Distributed resistance model of SWCNT:

SWCNT_Capacitance
• Capacitance of an isolated SWCNT is contributed by
 Electrostatic capacitance (CE)
With diameter ‘d’ placed at a distance ‘y’ away from a ground plane
 Quantum capacitance (CQ)
CQ of individual SWCNT has a typical value of 100 aF/μm.
The effective SWCNT capacitance is given by series
combination of CE and CQ
(y/d)nl
2
CE


f
2
Q hVe2C /
50

Mixed CNT Bundle
 Higher resistance associated with individual SWCNT
motivated researchers to use a bundle of CNTs.
 Theoretically, CNT bundles may contain only SWCNTs
or only MWCNTs.
 A mixed bundle consists of SWCNTs with a diameter
‘d’ and MWCNTs with various diameters (Din < di < Dout).
 Mixed CNT bundle is more realistic than SWCNT and
MWCNT bundle.
51

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