Low power vlsi design ppt
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Low power VLSI design has become an important discipline due to increasing device densities, operating frequencies, and proliferation of portable electronics. Power dissipation, which was previously neglected, is now a primary design constraint. There are several sources of power dissipation in CMOS circuits, including switching power due to charging and discharging capacitances, short-circuit power during signal transitions, and leakage power from subthreshold and gate leakage currents. Designers have some control over power consumption by optimizing factors such as activity levels, clock frequency, supply voltage, transistor sizing and architecture.
![Power/performance tradeoffs
S. Reda EN160 SP’07
Threshold voltage (Vt)
Powersupplyvoltage(Vdd)
increasing
performance
higher
active power
higher
leakage
[Taur, 01]](https://image.slidesharecdn.com/lowpowervlsidesignbook-140426055029-phpapp02/85/Low-power-vlsi-design-ppt-96-320.jpg)
![State Machine Encoding
• The very first step of a state machine synthesis process is to
allocate the state register and assign binary codes to represent the
symbolic states. This process is called the encoding of a state
machine
• The encoding of a state machine is one of the most important
factors that determine the quality (area, power, speed etc) of the
gate level circuit
• Transition Analysis of State Encoding
– The key parameter to the power efficiency of state encoding is the expected
number of bit transitions E[M] in the state register
– Another parameter is the expected number of transitions of output signals
• In general machines with lower E[M] are more power
efficient because
– Fewer transitions of the state register lead to low power dissipation and
– Fewer transitions are propagated into the combinational logic of the machine](https://image.slidesharecdn.com/lowpowervlsidesignbook-140426055029-phpapp02/85/Low-power-vlsi-design-ppt-211-320.jpg)
![State Machine Encoding
• Consider two functionality identical state machines M1 and M2
with different encoding as shown below
• The binary codes in the state bubbles indicate the state encoding
• The labels at the state transition edges represent the probabilities
that transition will occur at any given clock cycle
• The sum of all edge probabilities equals to unity
• The expected number of state bit transitions E[M] is given by the
sum of products of edge probabilities and their associated number
of bit flips as dictated by the encoding](https://image.slidesharecdn.com/lowpowervlsidesignbook-140426055029-phpapp02/85/Low-power-vlsi-design-ppt-212-320.jpg)
![State Machine Encoding
• However, a state encoding with the lowest E[M] may not be the
one that results in the lowest overall power dissipation
• The reason is that the particular encoding may require more gates
in the combinational logic, resulting in more signal transitions and
power
• The synthesized area and power dissipation of some randomly
encoded state machines is shown below](https://image.slidesharecdn.com/lowpowervlsidesignbook-140426055029-phpapp02/85/Low-power-vlsi-design-ppt-213-320.jpg)
![Clock Gating: Example
286
DSP/
HIF
DEU
MIF
VDE
896Kb SRAM
90% of FlipFlops clock-gated
70% power reduction by clock-gating
MPEG4 decoder
10
8.5mW
0 155
30.6mW
20 25
Without clock gating
With clock gating
Power [mW]](https://image.slidesharecdn.com/lowpowervlsidesignbook-140426055029-phpapp02/85/Low-power-vlsi-design-ppt-282-320.jpg)
![Source-code Transformations
• Minimize power-consuming activity:
– Computation
– Communication
– Storage
307
A*B+A*C A*(B+C)
for (c = 1..N)
receive (A)
B=c*A
receive (A)
for (c = 1..N)
B=c*A
for (c = 1..N)
B[c] = A[c]*D[c]
for (c = 1..N)
F[c] = B[c]-1
for (c = 1..N)
F[c] = A[c]*D[c]-1](https://image.slidesharecdn.com/lowpowervlsidesignbook-140426055029-phpapp02/85/Low-power-vlsi-design-ppt-303-320.jpg)
![Battery aware design: Example 2
Discharge profile A Discharge profile B
Minimum average current ≠ Maximum battery life time
321
Profile Aver. Current [mA] Battery lifetime [ms] Specif. energy [Wh/Kg]
A 123.8 357053 15.12
B 124.2 536484 18.58
Current[mA]
Current[mA]](https://image.slidesharecdn.com/lowpowervlsidesignbook-140426055029-phpapp02/85/Low-power-vlsi-design-ppt-317-320.jpg)
![Trend: Interconnects
324
Interconnects
Example (very optimistic):
6–10 clock cycles in 50nm
technology
[Benini, 2002]
Propagation delays of
global wires will be a
multiple of the clock cycle.](https://image.slidesharecdn.com/lowpowervlsidesignbook-140426055029-phpapp02/85/Low-power-vlsi-design-ppt-320-320.jpg)
Low power vlsi design ppt
- 1. UNIT I Low Power VLSI Design By Dr. R. Nakkeeran Associate Professor School of Engineering & Technology Department of Electronics Engineering Pondicherry University Pondicherry-14
- 2. Low Power Design – An Emerging Discipline • Historical figure of merit for VLSI design – performance (circuit speed) and chip area (circuit density/cost) • Power dissipation is now an important metric in VLSI design – No single major source for power savings across all design levels – Required a new way of THINKING!!! – Companies lack the basic power-conscious culture and designers need to be educated in this respect • Overall Goal – To reduce power dissipations but maintaining adequate throughput rate
- 3. Need for Low Power VLSI Chips • Power dissipation was neglected due to – Low device density – Low operating frequency • Now it is important issue due to – High device density – High operating frequency – Proliferation of portable consumer electronics – Concerns on Environments and energy sources
- 4. Competitive Reasons – Low Power • Battery Powered Systems – Extended Battery Life and reduce weight and size. • High-Performance Systems – Cost • Package (chip carrier, heat sink, card slots, plenum, …) • Power Systems (supplies, distribution, regulators, …) • Fans (noise, power, reliability, area, …) • Operating cost to customer – Energy Star issue. – Reliability • Failure rate increase by 4X for Tj @ 110C vs 70C • Mission critical operation at 100C – Size and Weight – Product footprint (office and deskspace)pp. 4
- 5. Moore’s Law In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months. He made a prediction that semiconductor technology will double its effectiveness every 18 months IBM Cell 234M transistors in die size of 221 mm2 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 LOG2OFTHENUMBEROF COMPONENTSPERINTEGRATEDFUNCTION Electronics, April 19, 1965
- 7. Transistor Counts 1,000,000 100,000 10,000 1,000 10 100 1 1975 1980 1985 1990 1995 2000 2005 2010 8086 80286 i386 i486 Pentium® Pentium® Pro K 1 Billion Transistors Source: Intel Projected Pentium® II Pentium® III Courtesy, Intel
- 8. Moore’s law in Microprocessors 4004 8008 8080 8085 8086 286 386 486 Pentium® proc P6 0.001 0.01 0.1 1 10 100 1000 1970 1980 1990 2000 2010 Year Transistors(MT) 2X growth in 1.96 years! Transistors on Lead Microprocessors double every 2 years Courtesy, Intel
- 9. Die Size Growth 4004 8008 8080 8085 8086 286 386 486 Pentium ® proc P6 1 10 100 1970 1980 1990 2000 2010 Year Diesize(mm) ~7% growth per year ~2X growth in 10 years Die size grows by 14% to satisfy Moore’s Law Courtesy, Intel
- 10. Frequency P6 Pentium ® proc 486 386 28680868085 8080 8008 4004 0.1 1 10 100 1000 10000 1970 1980 1990 2000 2010 Year Frequency(Mhz) Lead Microprocessors frequency doubles every 2 years Doubles every 2 years Courtesy, Intel
- 11. Power Dissipation P6 Pentium ® proc 486 386 2868086 8085 8080 8008 4004 0.1 1 10 100 1971 1974 1978 1985 1992 2000 Year Power(Watts) Lead Microprocessors power continues to increase Courtesy, Intel
- 12. Power will be a major problem 5KW 18KW 1.5KW 500W 4004 8008 8080 8085 8086 286 386 486 Pentium® proc 0.1 1 10 100 1000 10000 100000 1971 1974 1978 1985 1992 2000 2004 2008 Year Power(Watts) Power delivery and dissipation will be prohibitive Courtesy, Intel
- 13. Power density 4004 8008 8080 8085 8086 286 386 486 Pentium® proc P6 1 10 100 1000 10000 1970 1980 1990 2000 2010 Year PowerDensity(W/cm2) Hot Plate Nuclear Reactor Rocket Nozzle Power density too high to keep junctions at low temp Courtesy, Intel Sun Surface
- 14. Not Only Microprocessors Digital Cellular Market (Phones Shipped) 1996 1997 1998 1999 2000 Units 48M 86M 162M 260M 435M Analog Baseband Digital Baseband (DSP + MCU) Power Management Small Signal RF Power RF (data from Texas Instruments) Cell Phone
- 15. Important (Wireless) Technology Trends “Spectral Efficiency”: More bits/m3 Rapidly declining system cost Rapidly increasing transistor density
- 16. Important (Wireless) Technology Trends Speed-Distance-Cost Tradeoffs Rapid Growth: Machine-to- Machine Devices (mostly sensors)
- 17. In the Physical World: Sensor Devices
- 18. Low Power Design • Source of power disspation • P = P switching + P short-circuit + P leakage + P static – Definitions: • Switching power P = CV2fα • Short circuit power P = IscV • Leakage power P = IleakageV • Static power P = IstaticV • α : switching activity factor – Low power design would look at the trade-offs of the above issues
- 19. Why Worry About Power? • Portable devices: – Handhelds, laptops, phones, MP3 players, cameras, … all need to run for extended periods on small batteries without recharging – Devices that need regular recharging or large heavy batteries will lose out to those that don’t. • Power consumption important even in “tethered” devices – System cost tracks power consumption: • Power supplies, distribution, heat removal – Power conservation, environmental concerns • In 10 years, have gone from minimal consideration of power consumption to (designing with power consumption as a primary design constraint!
- 20. Battery Portable consumer electronics powered by battery Battery is heavy and big Energy density barely doubles in several years Safety concern: the energy density is approaching that of explosive chemicals The battery technology alone will not solve the low power problem
- 21. Basics • Power supply provides energy for charging and discharging wires and transistor gates. The energy supplied is stored & then dissipated as heat. • If a differential amount of charge dq is given a differential increase in energy dw, the potential of the charge is increased by: • By definition of current: dqdwV /dtdqI / /P dw dt Power: Rate of work being done w.r.t time Rate of energy being used IVP dt dq dq dw dtdw / t Pdtw Total energy Unit:tEP Watts = Joules/seconds A very practical formulation!
- 22. Basics • Warning! In everyday language, the term “power” is used incorrectly in place of “energy” • Power is not energy • Power is not something you can run out of • Power can not be lost or used up • It is not a thing, it is merely a rate • It can not be put into a battery any more than velocity can be put in the gas tank of a car
- 23. + 1V - 1 Ohm Resistor 1A 0.24 Calories per Second Heats 1 gram of water 0.24 degree C This is how electric tea pots work ... 1 Joule of Heat Energy per Second 20 W rating: Maximum power the package is able to transfer to the air. Exceed rating and resistor burns.
- 24. Cooling an iPod nano ... Like a resistor, iPod relies on passive transfer of heat from case to the air Why? Users don’t want fans in their pocket ... To stay “cool to the touch” via passive cooling, power budget of 5 W If iPod nano used 5W all the time, its battery would last 15 minutes ...
- 25. Powering an iPod nano (2005 edition) Battery has 1.2 W-hour rating: Can supply 1.2 W of power for 1 hour 1.2 W / 5 W = 15 minutes Real specs for iPod nano : 14 hours for music, 4 hours for slide shows 85 mW for music 300 mW for slides More W-hours require bigger battery and thus bigger “form factor” -- it wouldn’t be “nano” anymore!
- 26. How Do We Measure and Compare Power Consumption? • One popular metric for microprocessors is: MIPS/watt – MIPS, millions of instructions per second • Typical modern value? – Watt, standard unit of power consumption • Typical value for modern processor? – MIPS/watt reflects tradeoff between performance and power – Increasing performance requires increasing power – Problem with “MIPS/watt” • MIPS/watt values are typically not independent of MIPS – Techniques exist to achieve very high MIPS/watt values, but at very low absolute MIPS (used in watches) • Metric only relevant for comparing processors with a similar performance – One solution, MIPS2/watt. Puts more weight on performance
- 27. Metrics • How does MIPS/watt relate to energy? • Average power consumption = energy / time – MIPS/watt = instructions/sec / joules/sec = instructions/joule – Equivalent metric (reciprocal) is energy per operation (E/op) • E/op is more general - applies to more that processors – also, usually more relevant, as batteries life is limited by total energy draw – This metric gives us a measure to use to compare two alternative implementations of a particular function
- 28. Power in CMOS C pullup network pulldown network Vdd GND 10 i(t) v(t) t0 t1 v(t) VddSwitching Energy: energy used to switch a node Energy supplied Energy dissipatedEnergy stored Calculate energy dissipated in pullup: 222 2121 )()()()()( 1 0 1 0 1 0 1 0 1 0 dd t t t t dddddd t t dd t t dd t t sw cVcVcVdvvcdvcV dtdtdvcvVdttivVdttPE An equal amount of energy is dissipated on pulldown
- 29. Switching Power • Gate power consumption: – Assume a gate output is switching its output at a rate of: 1/f Pavg clock f f swavg ErateswitchingtEP 2 21 ddavg cVfP 2 21 ddavgavgavg VcfnP Chip/circuit power consumption: activity factor clock rate Therefore: number of nodes (or gates) (probability of switching on any particular clock period)
- 30. Other Sources of Energy Consumption • “Short Circuit” Current: Vout Vin Vin I I VoutVin I V Diode Characteristic10-20% of total chip power ~1nWatt/gate few mWatts/chip Transistor drain regions “leak” charge to substrate. Junction Diode Leakage :
- 31. Other Sources of Energy Consumption • Consumption caused by “DC leakage current” (Ids leakage): • This source of power consumption is becoming increasing significant as process technology scales down • For 90nm chips around 10-20% of total power consumption • Estimates put it at up to 50% for 65nm Ioff Vout=VddVin=0 Ids Vgs VthTransistor s/d conductance never turns off all the way Low voltage processes much worse
- 32. Controlling Energy Consumption: What Control Do You Have as a Designer? • Largest contributing component to CMOS power consumption is switching power: • Factors influencing power consumption: – n: total number of nodes in circuit – : activity factor (probability of each node switching) – f: clock frequency (does this effect energy consumption?) – Vdd: power supply voltage • What control do you have over each factor? • How does each effect the total Energy? 2 1 2avg avg avg ddP n f c V
- 33. Scaling Switching Energy per Gate Moore’s Law at work … Due to reduced V and C (length and width of Cs decrease, but plate distance gets smaller) Recent slope reduced because V is scaled less aggressively
- 34. Device Engineers Trade Speed and Power We can reduce leakage (Pstandby) by raising Vt We can increase speed by raising Vdd and lowering Vt We can reduce CV2 (Pactive) by lowering Vdd
- 35. Customize processes for product types
- 37. 3 Strategies for Low Power
- 38. Reliability and Cooling Costs • High power dissipation high temperature malfunction • High performance microprocessors: ~50 Watts (a hand-held soldering iron) • Packaging cost and cooling cost: fans • Power supply rails: high transient current (e.g. 3A)
- 39. Physics of Power Dissipation in CMOS FET Devices MIS structure
- 40. Physics of Power Dissipation in CMOS FET Devices • For an ideal MIS diode, the energy difference ψms between the metal work function ψm and the semiconductor work function ψs is zero • ψms ≡ψm - (χ+ Eg/2q +ΨB) = 0 where χ is the semiconductor electron affinity (from conduction band to vacuum level), Eg the band gap (from valence band to conduction band), ψB the potential barrier between the metal and the insulator, and ΨB the potential difference between the Fermi level EF and the intrinsic Fermi level Ei 44
- 41. Fermi-Dirac Function • fFD(E) = 1/ (1 + exp ((E – EF) / kT)) • The Fermi-Dirac distribution function gives the probability that a certain energy state will be occupied by an electron • As in a gas, the electrons in a solid are in constant motion and consequently changing their energy and momentum 45
- 42. P-type 46 Energy bands in as unbiased MIS diode
- 43. CMOS Gate Power equations • P = CLVDD 2f 01 + tsc VDD Ipeak f 0 1 + VDD Ileakage • Dynamic term CLVDD 2f 01 • Short-circuit term tsc VDD Ipeakf 0 1 • Leakage term VDD Ileakage • The Maxwell-Boltzmann statistics relates the equilibrium hole concentration to the intrinsic Fermi level: p0 = ni exp((Ei – EF)/kT) 47
- 44. P substrate 48 Energy bands when a negative bias is applied • The Fermi level EF in the semiconductor is now –qV below the Fermi level in the metal gate
- 45. P Substrate 49 Energy bands when a small positive bias is applied
- 46. • If the applied voltage is increased sufficiently, the bands bend far enough that level Ei at the surface crosses over to the other side of level EF • This is brought about by the tendency of carriers to occupy states with the lowest total energy • In the present condition of inversion the level Ei bends to be closer to level Ec and electrons outnumber holes at the surface 50
- 47. • Ei at the surface now is below EF by an amount of energy equal to 2 ΨB , where ΨB is the potential difference between the Fermi level EF and the intrinsic Fermi level Ei in the bulk. 51 Energy bands in strong inversion • The value of V necessary to reach the onset of strong inversion is called the threshold voltage
- 48. Surface Space Charge Region and the Threshold Voltage • Poisson equation • ▽ ‧D = ρ(x, y, z) Where D is the electric displacement vector, is equal to εs E under low-frequency or static conditions εs is the permittivity of Si E the electric field vector and ρ(x, y, z) the total electric charge density 52
- 49. 53 Energy bands at the insulator semiconductor surface
- 50. Threshold voltage • VT = (2d/εi ) * ( q εs NA ψB (1 – e-2βψ B) )0.5 + 2ψB The total voltage needed to offset the effect of nonzero work function difference and the presence of the charges is referred to as the flat-band voltage VFB VFB = ψms – QT*d/εi • VT = (2d/εi ) * ( q εs NA ψB (1 – e-2βψ B) )0.5 + 2ψB + VFB • VT decreases when L (length) is decreased, varies with Z (width), and decreases when the drain-source voltage VDS is increased. 54
- 51. 55 Variation of minority concentration in the channel of a MOSFET biased in weak inversion
- 52. Threshold voltage • Drain-induced barrier lowering (DIBL) is the basis for a number of more complex models of the threshold voltage shift • It refers to the decrease in threshold voltage due to the depletion region charges in the potential barrier between the source and the channel at the semiconductor surface • A recent model adopt a quasi two-dimensional approach to solving the two-dimensional Poisson equation • dEx/dx at each point (x, y) can be replaced with the average of its value at (0, y) and at (W, y) 56 Short channel effect • The minimum value of the surface potential increases with decreasing channel length and increasing VDS
- 53. Subsurface Drain-Induced Barrier Lowering (Punchthrough) • The punchthrough voltage VPT defined as the value of VDS at which I D, st reaches some specific magnitude with VGS = 0 • The parameter VPT can be roughly approximated as the value of VDS for which the sum of the widths of the source and the drain depletion regions becomes equal to L 57
- 54. Power Dissipation in CMOS • The first ICs ever fabricated used a PMOS process. This is due to the simplicity of fabrication of a p-channel enhancement mode MOS field-effect transistor (PMOST) with threshold voltage VTp < 0 • The charge mobility factor caused the move to the NMOS process • Then change to CMOS because of the power dissipation problem • This advantage of CMOS over NMOS has proven to be important enough that the shortcomings of CMOS are overlooked • The CMOS process is more complex than the NMOS, the CMOS requires use of guard-rings to get around the latch-up problem, and CMOS circuits require more transistors than the equivalent NMOS circuits 58
- 55. 59 CMOS inverter
- 56. Short-Circuit Dissipation • The short-circuit dissipation of the gate varies with the output load and the input signal slope • The short-circuit dissipation decreases linearly (roughly) in both absolute terms and a fraction of the total dissipation as the output load is increased to a critical value and then it will increase again rapidly 60
- 58. • For simplicity a symmetrical inverter (i.e., βN = βp and VTn = -Vtp;) and a symmetrical input signal (rise time = fall time) are considered. • I = β/2(Vin – V T)2 for 0≦ I≦ Imax • Imean = 1/T ∫0 T I(t) dt = 2* 2/T ∫t1 t2 β/2 (Vin (t) – VT)2 dt • Assuming the rising and falling portions of the input voltage waveform to be linear ramps, • Vin(t) = t* VDD/τ • Imean = 2*2/T∫(Vt/Vdd) τ τ/2 β/2(t*VT/τ – VT)2 dt • Let θ= (VT/τ)t - VT 62
- 59. • Imean = - 2β/T∫(Vt/Vdd) τ τ/2 θ dθ • Imean = 1/12*β/VDD(VDD – VT)3 τ/T • The short-circuit power dissipation of an unloaded inverter is • PSC = β/12(VDD – VT)3 τ/T 63 • If the inverter is lightly loaded, causing output rise and fall times that are relatively shorter than the input rise and fall times, the short-circuit dissipation increases to become comparable to dynamic dissipation • To minimize dissipation, an inverter should be designed in such a way so that the input rise and fall times are about equal to the output rise and fall times
- 60. Dynamic Dissipation • Assuming that the input Vin is a square wave having a period T and that the rise and fall times of the input are much less than the repetition period, the dynamic dissipation is given by • PD = CL VDD 2/T 64
- 61. 65 Energy per transition • When V = VDD, E 0->1 = CLVDD 2. • When energy stored in a capacitor with capacitance CL and voltage VDD across its plates is CL VDD 2/2, the rest of the energy, another CL VDD 2/2, is converted into heat
- 62. Principles of Low-Power Design • Using the lowest possible supply voltage • Using the smallest geometry, highest frequency devices but operating them at the lowest possible frequency • Using parallelism and pipelining to lower required frequency of operation • Power management by disconnecting the power source when the system is idle • Designing systems to have lowest requirements on subsystem performance for the given user level functionality 66
- 63. Fundamental Limits • The limit from thermodynamic principles results from the need to have, at any node with an equivalent resistor R to the ground, the signal power Ps exceed the available noise power Pavail • The quantum theoretic limit on low power comes from the Heisenberg uncertainty principle. In order to be able to measure the effect of a switching transition of duration Δt, it must involve an energy greater than h/ Δt: • P ≧ h/ (Δt)2 where h is the Planck’s constant 67
- 64. • Finally the fundamental limit based on electromagnetic theory results in the velocity of propagation of a high-speed pulse on an interconnect to be always less than the speed of light in free space, c0: • L/τ≦ c0 where L is the length of the interconnect and τ is the interconnect transit time 68
- 65. Material Limits • The attributes of a semiconductor material that determine the properties of a device built with the material are • Carrier mobility μ • Carrier saturation velocity σs • Self-ionizing electric field strength Ec • Thermal conductivity K 69
- 66. • Consider an SOI structure by surrounding the above generic device in a hemispherical shell of SiO2 of radius ri, indicating a two-order-of- magnitude reduction in thermal conductivity • The response time of the global interconnect circuit is τ= (2.3 Rtr + Rint) Cint where Rtr is the output resistance of the driving transistor and Rint and Cint are the total resistance and capacitance, respectively, of the global interconnect. 70
- 67. System Limits • The architecture of the chip • The power-delay product of the CMOS technology used to implement the chip • The heat removal capacity of the chip package • The clock frequency • Its physical size 71
- 68. Energy characterization • Transition-sensitive energy models – Single energy tables • Bit independent modules e.g., flipflops – Multiple energy tables • Large bit dependent modules e.g., 32-b adders • Large multi-element modules e.g., register files – Transition sensitive energy equations – System level interconnect capacitance values • Analytical energy modes – Cache and main memory 72
- 69. Transition-sensitive energy model • Must first design and layout a functional unit and then simulate it to capture switch capacitances – Bit independent – bus lines, pipeline registers • One bit switching does not affect other bit slices’ operations • Bit dependent – ALU, decoders • Once constructed, the models can be reused in simulations of other architectures built with the same technology 73
- 70. Architectural Level Analysis Considerations • Very computationally efficient – Requires predefined analytical and transition- sensitive energy characterization models – Requires design only to RTL (with some idea as to the kind of functional units planned) – Coarse grain – use of gated clocks implicit • Reasonably accurate (within 5% - 15% of SPICE) 74
- 71. Dynamic Power Consumption • Not a function of transistor sizes! • Need to reduce CL, Vdd, and f ti reduce power • Reduce the probability, P0 -> 1 pp. 75 Energy/transition = CL * Vdd2 Power = Energy/transition * f = CL * Vdd 2 * f
- 72. Dynamic Power Consumption - Extended • Power = Energy/transition * transition rate = CL * Vdd 2 * f0->1 = CL * Vdd 2 * P0->1 * f = CEFF * Vdd 2 * f • Power Dissipation is Data Dependent Function of Switching Activity – CEFF = Effective Capacitance = CL * P0->1 pp. 76
- 73. Ultra Low Power System Design • Power minimization approaches: • Run at minimum allowable voltage • Minimize effective switching capacitance pp. 77
- 74. Choice of Logic Style pp. 78
- 75. Choice of Logic Style • Power-delay product improves as voltage decreases • The “best” logic style minimizes power-delay for a given delay constraint pp. 79
- 76. Power Consumption is Data Dependent • Example : Static 2 Input NOR Gate pp. 80 Assume : P(A=1) = ½ P(B=1) = ½ Then : P(Out=1) = ¼ P(0→1) = P(Out=0).P(Out=1) =3/4 * 1/4 = 3/16 CEFF = 3/16 * CL
- 77. Operating at the Lowest Possible Voltage! • Desire to operate at lowest possible speeds (using low supply voltages) • Use Architecture optimization to compensate for slower operation Approach : Trade-off AREA for lower POWER pp. 81
- 78. Operating at the Lowest Possible Voltage! • Desire to operate at lowest possible speeds (using low supply voltages) • Use Architecture optimization to compensate for slower operation Approach : Trade-off AREA for lower POWER pp. 82
- 80. Lowering Vdd Increases Delay pp. 84 • Concept of Dynamic Voltage Scaling (DVS)
- 81. Architecture Trade-offs : Reference Data Path pp. 85
- 82. Parallel Data Path pp. 86
- 83. Pipelined Data Path pp. 87
- 84. A Simple Data Path : Summary pp. 88
- 85. Computational Complexity of DCT Algorithms pp. 89
- 86. Power Down Techniques pp. 90 • Concept of Dynamic Frequency Scaling (DFS)
- 87. Energy-efficient Software Coding • Potential for power reduction via software modification is relatively unexploited. • Code size and algorithmic efficiency can significantly affect energy dissipation • Pipelining at software level- VLIW coding style • Examples - pp. 91
- 88. Power Hunger – Clock Network (Always Ticking) • H-Tree – design deficiencies based on Elmore delay model • PLL – every designer (digital or analog) should have the knowledge of PLL • Multiple frequencies in chips/systems – by PLL • Low main frequency, But • Jitter and Noise, Gain and Bandwidth, Pull-in and Lock Time, Stability … • Local time zone • Self-Timed • Asynchronous => Use Gated Clocks, Sleep Mode pp. 92
- 89. Power Analysis in the Design Flow pp. 93
- 90. Scaling of MOS transistors S. Reda EN160 SP’07 minimum feature size (gate length) 1.2nm Current oxide thickness ~ 1.0 – 2.0nm thickness 3 – 4 atomic layers of oxide Power supply voltage scaling
- 91. Scaling S. Reda EN160 SP’07 Avg transistor price is 0.1 μcent! Fewer and fewer companies can afford to have their own foundries Scaling of lithographic wavelength Number of transistors shipped
- 92. Device scaling S. Reda EN160 SP’07 (very idealistic NMOS transistor) doping increased by a factor of S scale Increasing the channel doping density decreases the depletion width improves isolation between source and drain during OFF status permits distance between the source and drain regions to be scaled (scaled down by L)
- 93. Implications of ideal device scaling Influence of scaling on MOS device characteristics
- 94. Total power was increasing (mostly because of 2 frequency + die) until we hit a “wall” S. Reda EN160 SP’07 Intel VP Patrick Gelsinger (ISSCC 2001) “If scaling continues at present pace, by 2005, high speed processors would have power density of nuclear reactor, by 2010, a rocket nozzle, and by 2015, surface of sun.”
- 95. Scaling of standby (leakage) power )(1 mkT qV ox off t e t P S. Reda EN160 SP’07 Even if Vt is kept constant after scaling, Poff scales up by S if tox is scaled down by S Vt must be scaled down if VDD is scaled down (otherwise ISAT is weaker and transistor is slow) Standby power would further increase by 10 for every 0.1V reduction of Vt Standby power bottleneck
- 96. Power/performance tradeoffs S. Reda EN160 SP’07 Threshold voltage (Vt) Powersupplyvoltage(Vdd) increasing performance higher active power higher leakage [Taur, 01]
- 97. Interconnect scaling w S. Reda EN160 SP’07 h s t l w: width of interconnect (layer dependant) s: spacing between interconnects with same layer h: dielectric thickness (spacing between interconnects in two vertically adjacent layers) l: length of interconnect t: thickness of interconnect
- 98. Constant thickness scaling versus reduced thickness scaling S. Reda EN160 SP’07 S w t S l w t S l S tS w w t l l reduced thickness scaling constant thickness scaling
- 99. Implications of ideal interconnect scaling Influence of scaling on interconnect characteristics
- 100. Interconnect delay is dominating gate delay S. Reda EN160 SP’07 bottleneck Repeaters can help but…
- 101. With scaling the reachable radius of a buffer decreases we need more and more buffers S. Reda EN160 SP’07 A corner-to-corner (BL-UR) wire in Itanium (180nm) requires 6 repeaters to span die Repeaters consume chip area; consume power; add vias repeaters required to buffer Itanium global interconnects bottleneck
- 103. Conclusions • High-speed design is a requirement for many applications • Low-power design is also a requirement for IC designers. • A new way of THINKING to simultaneously achieve both!!! • Low power impacts in the cost, size, weight, performance, and reliability. • Variable Vdd and Vt is a trend (DVS and DFS) • CAD tools high-level power estimation and management • Pay attention to nano electro mechanical Systems (NEMS) – lots of problems and potential is great. pp. 107
- 105. Simulation Power analysis • Computer simulation has been applied to VLSI design for several decades • Simulation programs operate on mathematical models which mimic the physical laws and properties of the object under simulation • Simulation is used for – Functional verification – Performance – Cost – Reliability – Power analysis • Digital logic simulation examples – VHDL (very high Speed IC Hardware Description Language) – Verilog
- 106. Computing resources and analysis accuracy at various abstraction levels • The main difference between simulation at different levels of design abstraction is the tradeoff between computing resource (memory and CPU time) and accuracy of the results
- 107. Points to remember • Simulation based power estimation and analysis techniques have been developed and applied to VLSI design process • Simulation at lower level design abstraction offers better accuracy at the expense of increased computer resource • Circuit simulators such as SPICE attain excellent accuracy but cannot be applied to full chip analysis • Logic simulation generally can handle full chip analysis but the accuracy is not as good and sometimes the execution speed is too low • Behavioral level or functional level simulation offers rapid analysis but the accuracy is sacrificed
- 108. SPICE circuit simulation • SPICE (Simulation program with IC emphasis) is the power analysis tool at the circuit level • SPICE operates by solving a large matrix of nodal current using the Kirchoffs current law (KCL) • The basic components of SPICE are the primitive elements of circuit theory such as resistors, capacitors, inductors, current sources and voltage sources • Complex device models such as diodes and transistors are constructed from the basic components Circuit level and switch level representation of a transistor
- 109. SPICE • Device models are subsequently used to construct a circuit for simulation • Circuit parameters such as voltage, current, charge etc are reported by SPICE with high degree of precision • Circuit power dissipation can be directly derived from SPICE simulation • Transient mode analysis for digital IC power estimation is widely used in SPICE – Involves DC solution of the circuit at time zero and makes small time increments – Used for dynamic behavior of the circuit over time
- 110. Gate level logic simulation • Simulation based gate level timing analysis has been a very mature technique in today's VLSI design • The component abstraction at this level is logic gates and nets • The circuit consists of components having defined logic behavior at its input and output such as NAND gates, latches and flip flops • Gate level logic simulation software is one of the earliest CAD tools being developed • In present world, Gate level logic simulator can perform full chip simulation up to several million gates
- 111. Basics of Gate level analysis • Event driven logic simulation – Events are zero-one logic switching of nets in a circuit at a particular simulation time point • Cycle based simulators • Gate level simulators – Hardware acceleration – Hardware emulation • VHDL and verilog are two popular languages used to describe gate-level design
- 112. Capacitive power estimation • The major advantage of gate level power analysis is that the P = C V2 f can be computed precisely • In non logic abstraction such as SPICE, the notion of the frequency of a node is not well defined because it has an analog waveform that is potentially non-periodic and non- digital • In logic simulation, the switching activities of each node can be monitored to determine its frequency • The capacitive power dissipation of the circuit is 2 (1) / 2 cap i i net i i i P C V f where f t T T – Simulation time elapsed C- Capacitance ti – Counter variable
- 113. Internal switching energy • The Equation (1) computes the power dissipated due to charging and discharging of node capacitance • Switching activities are not accounted • Short circuit power is also not captured • The dynamic power dissipated inside the logic cell is called internal power which consists of short circuit power and charging and discharging of internal nodes • Idea is to simulate the “dynamic energy dissipation events” of the gate with SPICE or other lower level power simulation tools • Switching from 1 to 0 or vice versa consumes some amount of dynamic energy internally
- 114. Internal switching energy • Computation of dynamic internal power uses the concept of logic events • Each gate has a pre-defined set of logic events in which a quantum of energy is consumed for each event • The energy value of each event can be computed with SPICE circuit simulation • The total dynamic internal power dissipation is given by Where E(g,e) is the energy of the event e of gate g obtained from logic gate characterization f(g,e) is the occurrence frequency of the event on the gate observed from logic simulation E(g,e) depends on process conditions, operating voltage, temperature, output loading capacitance, input signal slopes etc int , , gateg evente P E g e f g e
- 115. Internal switching energy • For example a simple 4 transistor NAND gate has four dynamic energy dissipation events as shown in below Fig. Dynamic events and static states of a 2-input CMOS NAND gate
- 116. Internal switching energy Two different implementation of NAND gate result in different dynamic energy dissipation events • The first implementation has only four energy dissipation events • Second implementation has two additional events due to switching of is internal nodes
- 117. Static state power • A similar event characterization idea can also be used to compute the static power dissipation of a logic gate • Here, the power dissipation depends on the state of the logic gate • The total static power is – P(g,s) is the static power dissipation of gate g at state s obtained from characterization – State duration T(g,s) is obtained from logic simulation • It is the total time gate g stays at state s , ,stat gate g state s T g s P P g s T
- 118. Gate level capacitance estimation • As discussed earlier, capacitance is the most important attribute that affects the power dissipation of CMOS circuits • Capacitance also has a impact on delays and signal slopes of logic gates • Change in gate delay may affect the switching characteristics of the circuit and influence power dissipation • Short circuit current is affected by the input signal slopes and output capacitance loading • Thus, capacitance has a direct and indirect impact on power analysis • The accurate estimation of capacitance is important for power analysis and optimization
- 119. Gate level capacitance estimation • Two types of parasitic capacitance exist in CMOS circuits: – Device parasitic capacitance – Wiring capacitance • Parasitic capacitance of MOS devices is associated with terminals • The gate capacitance depends on the oxide thickness of the gate that is process dependent • Design dependent factors are – Width, length and shape of the gate • In general a larger transistor has more capacitance in all its terminals • The second source of parasitic capacitance is wiring capacitance – Depends on the layer, area and shape of the wire
- 120. Gate level power analysis • The event driven gate level power simulation is summarized as follows: – Run logic simulation with a set of input vectors – Monitor the toggle count for each net – Obtain capacitive power dissipation Pcap – Monitor the dynamic energy dissipation events of each gate – Obtain internal switching power dissipation Pint – Monitor the static power dissipation states of each gate – Obtain static power dissipation Pstat – Sum up all power dissipation components P = Pcap + Pint + Pstat
- 121. Signal glitches - Gate level power analysis • The major disadvantage of gate level analysis is that signal glitches cannot be modeled precisely • Signal glitches are inherently analog phenomena and the simplified zero-one logic model in gate-level analysis fails to capture their effects • The presence of glitches is very sensitive to the signal and gate delays of the circuit • As signal glitches are significant source of power dissipation in some VLSI circuits, it cannot be ignored • However, it is difficult for any analysis model above the logic level to account for the signal glitches precisely
- 122. Architecture level analysis • Over the years, the design abstraction has moved from the mask, the transistors, to gates and now to the architecture level • Architecture level abstraction is called as block level or macro level design • Building blocks – Registers – Adders – Multipliers – Buses – Multiplexers – Memories – State machines etc • Today, architecture level power analysis is becoming more important because more digital circuits are now synthesized from architecture description
- 123. Power model based on activities • One way to characterize the architectural components is to express the power dissipation as a function of the number of bits of the components and their operating frequencies • Eg: the power dissipation of an adder can be expressed as: P = (n K1 + K2) f Where n – number of bits f – frequency of the addition operation K1 and K2 – empirical coefficients derived from gate level simulation • The above model depends only on the operating frequency and size of the adder • The model does not account the data dependency of the power dissipation
- 124. Power model based on activities • A more accurate model that can capture data dependency is to characterize the power dissipation as • For multipliers, the model is given by • Since it is tedious to characterize Ki for each input i, the P can be simplified as follows i i input i P K f i i j j input i input j P K f K f 1 2 1 2 i j input i input j in out P K f K f P K f K f
- 125. Power dissipation based on Component operations • In this model the power dissipation is expressed in terms of the frequency of some primitive operations of an architecture component • The power dissipation is given by • The parameters fread and fwrite are the frequencies of READ and WRITE operations, respectively • Coefficients K1 and K2 are obtained from characterization and properties of the component 1 2read writeP K f K f
- 126. Abstract statistical power models • The previous power models have to make certain assumptions on the statistical behavior of components in order to model the power dissipation efficiently • There are several fundamental issues in composing a power model – Which parameters have major influences on the power dissipation ? Size, signal frequency, operation frequency etc – What is the relationship of the power dissipation with the chosen parameters? Equation or lookup table • The solution depends on the type, implementation and accuracy level tolerated by the analysis
- 127. Data correlation analysis in DSP systems • Sample correlation – Refers to the property that successive data samples are very close in their numerical values and consequently their binary representations have many bits in common • Negative correlation (anti-correlation) – Successive samples jump from a large positive value to a large negative value • Positive or negative correlation has a significant effect on the power dissipation of a DSP system because of the switching activities on the system data path • Hence, here we discuss how to estimate power of the architecture level component based on the frequency and correlation measures of the data stream
- 128. Data correlation analysis in DSP systems • Dual bit type signal model – The effect of data correlation on power dissipation depends on the numerical representation of the digital system • Two’s complement • Signed magnitude – Uniform white noise region • Bits toggle in a random fasion Correlation resulting from sampling analog signals
- 129. Data correlation analysis in DSP systems • The data stream can be characterized with only a few parameters – Sample frequency – Data correlation factor from -1.0 to +1.0 – The sign bit and uniform white noise regions with two integers • Such characterization of data signals is called the dual bit type model proposed by Landman and Rabaey Effects of data correlation on bit switch frequency
- 130. Monte Carlo Simulation • Statistical estimation of mean Where p refers to the power samples 0 1 .............. Np p p P N Normal distribution curve of sample average P Table of Z distribution
- 131. Monte Carlo power Simulation • As we simulate the circuit, we collect samples pi at a fixed interval to compute the sample mean P and sample variance S2 • Given the confidence level (1-alpha) and error tolerance, we check whether the following equation is satisfied • If so, we claim that the stopping criteria have been achieved and stop the simulation. This process is called Monte Carlo power simulation 22 1 1 N i i S p P N 2 1, /2N t S N P
- 132. Graph plot of instantaneous power samples
- 133. Graph plot of computed sample mean during simulation
- 134. 138 Power Analysis: Probabilistic Methods
- 135. 139 Basic Idea • View signals as a random processes Prob{s(t) = 1} = p1 p0 = 1 – p1 C 0→1 transition probability = (1 – p1) p1 Power, P = (1 – p1) p1 CV2fck
- 136. 140 Source of Inaccuracy 1/fck p1 = 0.5 P = 0.5CV2fck p1 = 0.5 P = 0.33CV2fck p1 = 0.5 P = 0.167CV2fck Observe that the formula, Power, P = (1 – p1) p1 CV2fck, is not Correct.
- 137. 141 Switching Frequency Number of transitions per unit time: N(t) T = ─── t For a continuous signal: N(t) T = lim ─── t→∞ t T is defined as the transition density.
- 138. 142 Static Signal Probabilities • Observe signal for interval t0 + t1 – Signal is 1 for duration t1 – Signal is 0 for duration t0 – Signal probabilities: • p1 = t1/(t0 + t1) • p0 = t0/(t0 + t1) = 1 – p1
- 139. 143 Static Transition Probabilities • Transition probabilities: • T01 = p0 Prob{signal is 1 | signal was 0} = p0 p1 • T10 = p1 Prob{signal is 0 | signal was 1} = p1 p0 • T = T01 + T10 = 2 p0 p1 = 2 p1 (1 – p1) • Transition density: T = 2 p1 (1 – p1) • Transition frequency: f = T/ 2 • Power = CV2T/ 2 (correct formula)
- 140. 144 Static Transition Frequency 0 0.25 0.5 0.75 1.0 0.25 0.2 0.1 0.0 p1 f=p1(1–p1)
- 141. 145 Inaccuracy in Transition Density 1/fck p1 = 0.5 T = 1.0 p1 = 0.5 T = 4/6 p1 = 0.5 T = 1/6 Observe that the formula, T = 2 p1 (1 – p1), is not correct.
- 142. 146 Cause for Error and Correction • Probability of transition is not independent of the present state of the signal • Consider probability p01of a 0→1 transition, • Then p01 ≠ p0 p1 • We can write p1 = (1 – p1)p01 + p1 p11 p01 p1 = ───────── 1 – p11 + p01
- 143. 147 Correction (Cont.) • Since p11 + p10 = 1, i.e., given that the signal was previously 1, its present value can be either 1 or 0 • Therefore, p01 p1 = ────── p10 + p01 This uniquely gives signal probability as a function of transition probabilities
- 144. 148 Transition and Signal Probabilities 1/fck p01 = p10 = 0.5 p1 = 0.5 p01 = p10 = 1/3 p1 = 0.5 p1 = 0.5 p01 = p10 = 1/6
- 145. 149 Probabilities: p0, p1, p00, p01, p10, p11 • p01 + p00 =1 • p11 + p10 = 1 • p0 = 1 – p1 • p01 p1 = ────── p10 + p01
- 146. 150 Transition Density • T = 2 p1(1 – p1) = p0 p01 + p1 p10 = 2 p10 p01/(p10 + p01) = 2 p1 p10 = 2 p0 p01
- 147. 151 Power Calculation • Power can be estimated if transition density is known for all signals. • Calculation of transition density requires – Signal probabilities – Transition densities for primary inputs; computed from vector statistics
- 148. 152 Signal Probabilities x1 x2 x1 x2 x1 x2 x1 + x2 – x1x2 x1 1 - x1
- 149. 153 Signal Probabilities x1 x2 x3 x1 x2 y = 1 - (1 - x1x2) x3 = 1 - x3 + x1x2x3 = 0.625 X1 X2 X3 Y 0 0 0 1 0 0 1 0 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1 0 1 1 0 1 1 1 1 1 0.5 0.5 0.5 0.25 0.625 Ref: K. P. Parker and E. J. McCluskey, “Probabilistic Treatment of General Combinational Networks,” IEEE Trans. on Computers, vol. C-24, no. 6, pp. 668-670, June 1975.
- 150. 154 Correlated Signal Probabilities x1 x2 x1 x2 y = 1 - (1 - x1x2) x2 = 1 – x2 + x1x2x2 = 1 – x2 + x1x2 = 0.75 X1 X2 Y 0 0 1 0 1 0 1 0 1 1 1 1 0.5 0.5 0.25 0.625?
- 151. 155 Correlated Signal Probabilities x1 x2 x1 + x2 – x1x2 y = (x1 + x2 – x1x2) x2 = x1x2 + x2x2 – x1x2x2 = x1x2 + x2 – x1x2 = x2 = 0.5 X1 X2 Y 0 0 0 0 1 1 1 0 0 1 1 1 0.5 0.5 0.75 0.375?
- 152. 156 Observation • Numerical computation of signal probabilities is accurate for fanout-free circuits.
- 153. 157 Remedies • Use Shannon’s expansion theorem to compute signal probabilities. • Use Boolean difference formula to compute transition densities.
- 154. 158 Shannon’s Expansion Theorem • C. E. Shannon, “A Symbolic Analysis of Relay and Switching Circuits,” Trans. AIEE, vol. 57, pp. 713- 723, 1938. • Consider: • Boolean variables, X1, X2, . . . , Xn • Boolean function, F(X1, X2, . . . , Xn) • Then F = Xi F(Xi=1) + Xi’ F(Xi=0) • Where • Xi’ is complement of X1 • Cofactors, F(Xi=j) = F(X1, X2, . . , Xi=j, . . , Xn), j = 0 or 1
- 155. 159 Expansion About Two Inputs • F = XiXj F(Xi=1, Xj=1) + XiXj’ F(Xi=1, Xj=0) + Xi’Xj F(Xi=0, Xj=1) + Xi’Xj’ F(Xi=0, Xj=0) • In general, a Boolean function can be expanded about any number of input variables. • Expansion about k variables will have 2k terms.
- 156. 160 Correlated Signal Probabilities X1 X2 X1 X2 X1 X2 Y 0 0 1 0 1 0 1 0 1 1 1 1 Y = X1 X2 + X2’ Shannon expansion about the reconverging input: Y = X2 Y(X2=1) + X2’Y(X2=0) = X2 (X1) + X2’ (1)
- 157. 161 Correlated Signals • When the output function is expanded about all reconverging input variables, • All cofactors correspond to fanout-free circuits. • Signal probabilities for cofactor outputs can be calculated without error. • A weighted sum of cofactor probabilities gives the correct probability of the output. • For two reconverging inputs: f = xixj f(Xi=1, Xj=1) + xi(1-xj) f(Xi=1, Xj=0) + (1-xi)xj f(Xi=0, Xj=1) + (1-xi)(1-xj) f(Xi=0, Xj=0)
- 158. 162 Correlated Signal Probabilities X1 X2 X1 X2 X1 X2 Y 0 0 1 0 1 0 1 0 1 1 1 1 Y = X1 X2 + X2’ Shannon expansion about the reconverging input: Y = X2 Y(X2=1) + X2’Y(X2=0) = X2 (X1) + X2’ (1) y = x2 (0.5) + (1-x2) (1) = 0.5 (0.5) + (1-0.5) (1) = 0.75
- 159. 163 Example Point of reconv. Supergate 0.5 0.5 0.5 0.5 0.25 1 0 0.5 0.0 0.0 1.0 0.5 1.0 Signal probability for supergate output = 0.5 Prob{rec. signal = 1} + 1.0 Prob{rec. signal = 0} = 0.5 × 0.5 + 1.0 × 0.5 = 0.75 0.375 Reconv. signal S. C. Seth and V. D. Agrawal, “A New Model for Computation of Probabilistic Testability in Combinational Circuits,” Integration, the VLSI Journal, vol. 7, no. 1, pp. 49-75, April 1989.
- 160. Signal entropy • The entropy of a set of logic signals is a measure of its randomness • Entropy correlates to the average switching frequency of the signals • Skewed occurrence probability gives a low probability measure • If signal switching is active, it maximizes the entropy of the signals • These observations prompts the idea of using signal entropy for power estimation 164
- 161. Power estimation of combinational logic using entropy analysis 165
- 162. 166 Entropy Entropy based approach – Entropy: Measure of uncertainty in a random variable – Entropy H of a random variable x is given by avgavgavg CGEDP .. Davg: Average node switching activity GE: Gate equivalents Cavg: Average gate capacitance Recall that p p p pxH 1 1 log)1( 1 log)( • p: probability of x being 1
- 163. 167 Entropy • Answer: Yes! avgavg CGEHP .. Entropy H is given by 2 / 3 ( ( ) ( ))H H X H Y n m H(X) and H(Y) are respectively the input and output entropies Hypothesis Can Davg be estimated only from knowledge of inputs and output behavior?
- 164. Entropy analysis of a sequential circuit 168
- 165. 169 Entropy • Entropy Based Power Estimation Methodology: – Run a structural RTL simulation to measure input/output entropies – Using input/output entropies, estimate Pavg for the combinational block – Use other techniques to estimate latch and clock power
- 166. UNIT-III Low Power Design Circuit level
- 167. Power consumption in circuits • The power reduction techniques at the circuit level are quite limited if compared with the other techniques at higher abstraction levels • At the circuit level , percentage power reduction in the teens is considered good • However, circuit techniques can have major impact because some circuits, especially in cell- based design, are repeated thousands of times on a chip • Therefore, circuit techniques with a small percentage improvement should not be overlooked • Circuits designed manually can often be analyzed in great details • This allows us to optimize the circuit speed, power and area to suit our specification • One important circuit technique is the reduction of operating voltage – The general rule is to select the lowest voltage that is acceptable
- 168. Transistor and Gate Sizing • At the circuit level, transistors are the basic building blocks and a digital circuit can be viewed as a network of transistors with some additional parasitic elements such as capacitors and resistors • Transistor sizes are the most important factor affecting the quality ie area, and power dissipation of a circuit • Some studies assume that the sizing problem is a convex function and linear programming can be used to solve the sizing problem optimally • Another problem encountered in cell based design is gate sizing • The goal is to choose a set of gate sizes that best fits the design constraints
- 169. Sizing an Inverter Chain • The simplest transistor sizing problem is that of an inverter chain • The general design problem is to drive a large capacitive load without excessive delay, area and power requirements • A large inverter is required to drive the large capacitive load at the final stage Sizing an inverter chain
- 170. Sizing an Inverter Chain • If the chain is too long, the signal delay will be too large due to intrinsic delay of each inverter • If the chain is too short, the output signal slope will be very weak with long rise and fall times, which again causes long delay • The challenge is to decide the length of the chain ie. How many inverters, and the size of each inverter Graph plot of inverter chain delay and power dissipation
- 171. Transistor and Gate Sizing for Dynamic Power Dissipation • As seen in the previous graph, a large gate is required to drive a large load with acceptable delay but requires more power • This is similar to the classical delay area tradeoff problem • If we are not allowed to restructure the transistor network, the sizing for dynamic power reduction generally has the same goal as the area reduction problem • The basic rule is to use the smallest transistors or gates that satisfy the delay constraints • To reduce dynamic power, the gates that toggle with higher frequency should be made smaller • Although the basic rule sounds simple, the actual sizing problem is very complicated
- 172. Transistor and Gate Sizing for Dynamic Power Dissipation • Consider a part of the circuit as shown above • Suppose that the gates are not on the critical delay path and should be sized down • W can size down the first gate, the second gate or both, subject to the available sizes in the cell library as long as the path delay is not violated • If the path contains many gates, the optimization problem becomes very complicated • Stack time – Used to express the timing constraints of the circuit – It is the difference between the signal required time and signal arivela time at the output of a gate Gate sizing problem
- 173. Transistor and Gate Sizing for Dynamic Power Dissipation • A positive stack time mean that the signal arrived earlier than its required time and the gate can be sized down • The goal of gate sizing is to adjust the gate sizes such that the stack time of each gate is as low as possible without any gate having a negative stack i.e. timing violation • The area minimum sizing problem has been a subject of research in logic synthesis for dozen of years • Today in top down cell based design environment gate sizing has been much automated by the logic synthesis system
- 174. Transistor Sizing for Leakage Power Reduction • An interesting problem occurs when the sizing goal is to reduce the leakage power of a circuit • The leakage current of a transistor increases with decreasing threshold voltage and channel length • In general, a lower threshold or shorter channel transistor can provide more saturation current and thus offers a faster transistor • The presents a tradeoff between leakage power and delay • The leakage power of a digital circuit depends on the logic state of a circuit • Consider a simple two transistor inverter • If the output of the inverter is at logic high, the leakage current of the inverter is determined by the N- transistor that is turned off
- 175. Transistor Sizing for Leakage Power Reduction • Conversely if the output is low, the leakage current depends on the P- transistor • In order to suppress the leakage current, we can increase the threshold voltage or the channel length of the N- transistor • However, by doing so we also increase the delay of the inverter because the N- transistor now offers less saturation current when it is turned ON • If we are fortunate that the falling transition of the inverter is not the critical delay, we can use skewed transistor sizing method to reduce the leakage power without incurring any delay penalty
- 176. Transistor Sizing for Leakage Power Reduction • The transistor sizing concept is illustrated below Transistor sizing for leakage power reduction or speed increase
- 177. Equivalent Pin Ordering • Most combinational digital logic gates have input pins that logically equivalent • Eg: AND, OR, XOR • Such gates are use frequently because they are natural to the human thinking process • As for circuit implementation, the gates are robust and easy to design • Logically equivalent pins may not have identical circuit characteristics, which means that the pins have different delay and power consumption • Such property can be exploited for low power design
- 178. Equivalent Pin Ordering • Consider a CMOS NAND gate as shown below • We examine the condition when the input A is at high logic and the input B switches from logic low to high • The difference in power dissipation varies depending on various factors such as capacitances and transistor sizes • To conserve power the inputs should be connected such that transistors from input A to OUT occur more frequently than transitions from input B to OUT. This low power technique is known as pin ordering
- 179. Network Restructuring and Reorganization • The pin reordering technique is a special case of more general method called transistor restructuring • In this method, we restructure the transistors of a combinational cell, based on signal probabilities, to achieve better power efficiency within the allowable timing constraints • Transistor Network Restructuring – In CMOS logic design, there is a well known technique in which a Boolean function composed of AND and OR operators is directly mapped to a complex transistor network that implements the function – The mapping steps are as follows: 1. Each variable in the Boolean function corresponds to a pair of P and N transistors 2. For the N transistor network, an AND operator corresponds to a serial connection and an OR operator corresponds to a parallel connection
- 180. Network Restructuring and Reorganization 3. For the P transistor network, the composition rule is inverted 4. An inverter is optionally added to the output of the complex gate to maintain the proper polarity or to ensure signal strength Network composition of CMOS complex logic gate Y = A ( B + C )
- 181. Network Restructuring and Reorganization Alternative circuit implementation of Y = A ( B + C ) Four different circuit implementation of Y = A ( B + C ) Power reduction up to 20% was reported using the transistor network restructuring technique
- 182. Transistor Network Partitioning and Reorganization • In this section, we look beyond a CMOS gate and consider a transistor network • We study the problem of partitioning and reorganizing the network to explore the different power-area-delay trade off • Network reorganization by definition is the task of composing different transistor networks that can implement the same functionality • The figure below show two ways to implement a 4 input AND operation with a serial chain limit of three
- 183. Flip Flops & Latches design • Flip flops and latches are some of the most frequently used elements in digital VLSI • In synchronous systems, they are the starting and ending points of signal delay paths, which decide the maximum speed of the system • Typically, they consume more power because they are clocked at the system operating frequency • Careful design of the flip flop and latch circuits is important to a low power VLSI design • The energy dissipation of a flip flop can be divided into two components: 1. Clock energy 2. Data energy
- 184. Flip Flops & Latches design • The first component is the energy dissipated when the flip flop is clocked while the data of the flip flop is unchanged • The second component is the additional energy required to write a different data value into flip flop • In a typical flip flop the two energy components are comparable • However, in most systems, the data rate of a flip flop is typically much lower than its clock rate • This means that identical data values is being loaded with very high probability • Thus, the power saving techniques for flip flops mostly concentrate on the clock energy reduction
- 185. Flip Flop & Latch Circuits • The figure below shows various implementation of CMOS latches
- 186. Flip Flop & Latch Circuits • The above circuits provides a different tradeoff among setup time, hold time, data to output and clock to output delay • The use of NMOS pass transistors instead of transmission gates reduces the loading capacitance of the clock pin at the cost of reduced speed • This eliminates the need for a two phase non overlapping clock on the system or a phase splitter inverter that consumes power inside the cell • The circuit suffers from threshold voltage loss when logic 1 is propagated through the NMOS pass transistor • The single phase latch circuit avoids the threshold voltage problem but relies on charge storage effect to retain its data value • This cause some loss in the noise margin but the circuit has been successfully used in high performance processor design
- 187. Flip Flop & Latch Circuits • The figure below shows some circuit configuration of flip flops
- 188. Flip Flop & Latch Circuits • A flip flop is typically constructed from two latches connected together • The single phase dynamic flip flop at the top left is a cascaded version of two single phase latches • It is suitable for some low power applications because it does not require internal phase splitting inverter for the clock pin • The circuit at the bottom was reported to achieve lower power at the same speed with more transistors, compared to a standard flip flop design on the top right
- 189. Flip Flop & Latch Circuits • One circuit that an exotic differential signaling method to increase speed at the expense of area and power is shown below Differential input latch for high speed low voltage application
- 190. Self-gating Flip-flop • Part of the clock energy of a flip flop is consumed by the internal clock buffer to control the transmission gates • If the input of the flip flop is identical to its output, the switching of its clock signal can be suppressed to conserve power • This is similar to clock gating techniques • The difference is that the gating function is derived within the flip flop without any external control signal • Power is saved by holding the internal clock signals of the flip flop when allowed • The external clock signal of the flip flop still switches
- 191. Self-gating Flip-flop • An example of self gating flip flop is shown below Flip flop with self clock gating Power dissipation of self gating flip flop and regular flip flop
- 192. Combinational flip flop • One way to reduce circuit size is to associate logic gates with a flip flop to produce a combinational flip flop • Combinational flip flops are efficient because they are able to eliminate or share redundant gates • In terms of area, power and delay, combinational flip flops are desirable but they increase the design complexity
- 193. Double Edge Triggered flip flop • Most flip flops in use today are called single edge triggered flip flop (SETFF) because the data are loaded at only one clock edge, either rising or falling • A flip flop can also be designed so that it loads data at both rising and falling clock edges
- 194. Double Edge Triggered flip flop • Compared to SETFF, the double edge triggered flip flop (DETFF) requires slightly more transistors to implement • The flip flop retains its data when the clock signal is not toggling
- 195. Low Power Digital Cell Library • Over the years, the major VLSI design focus has shifted from masks, to transistors, to gates and to register transfer level • Undoubtedly, the quality of gate level circuit synthesized depends on the quality of the cell library • Cell Sizes and Spacing – In the top-down cell based design methodology, the tradeoff among power, area and delay is performed by selecting the appropriate sizes of the cells – Therefore, the important attribute that constitute a good low power cell library is the availability of wide ranges of cell sizes for commonly used gates – Further, the library cell count can be reduced without too much compromise in quality is to have more size selections for gates that are commonly used than those are less likely used
- 196. Low Power Digital Cell Library • Varieties of Boolean Functions – The lack of varieties of Boolean functions in a cell library can result in inferior circuits to be generated – For example if the Boolean function were to be implemented and the inverted input cells are not available, the logic synthesis system has to use an INVERTER and an AND gate to implement the function – The two cell implementation is less power efficient compared to the single cell implementation because of the external routing capacitance at the output of the inverter Y AB Inverted input cells for low power cell library
- 197. UNIT-III Low Power Design-Logic level
- 198. Logic Design • Logic design was once the primary abstraction level where automatic design synthesis begins • The most prevalent theme in logic level power optimization techniques is the reduction of switching activities • Switching activities directly contribute to the charging and discharging capacitance and the short circuit power • Some switching activities are the result of unspecified or undefined behavior of a logic system that are not related to its power operation • Such stray switching activities should be eliminated or reduced if possible • However, suppressing unnecessary activities usually requires additional hardware logic that increases the area and consumes power • The challenge is to justify the low power techniques via intelligent analysis
- 199. Gate Reorganization • The reorganization idea is not limited to transistor networks only since the same problem exists in gate level networks • Network reorganization is applied to the gate level network to produce logically equivalent networks with different qualities for power, area and delay • Technology mapping – Original network is expressed in a generic form such as two input NAND gates only • The reorganized network hopefully has better power efficiency than the original network • The complexity of the gate reorganization problem limits manual solution to small circuits only • Most gate reorganization tasks are performed by automated software in the logic synthesis system
- 200. Local Restructuring • Gate reorganization is an operation to transform one logic circuit to another that is functionally equivalent • Logic restructuring techniques use local restructuring rules to transform one network to another • Some basic transformation operators are: 1. Combine several gates into a single gate 2. Decompose a single gate into several gates 3. Duplicate a gate and redistribute its output connections 4. Delete a wire 5. Add a wire 6. Eliminate unconnected gates
- 201. Local transformation operators for gate reorganization
- 202. Local Restructuring • COMBINE operator can be used to hide high frequency nodes inside a cell so that the node capacitance is not being switched • DECOMPOSE and DUPLICATE operators help to separate the critical path from the non critical ones so that the latter can be sized down • DELETE WIRE operator reduces the circuit size • ADD WIRE operator helps to provide an intermediate circuit that may eventually lead to a better one
- 203. Signal Gating • Signal gating refers to a class of general techniques to mask unwanted switching activities from propagating forward, causing unnecessary power dissipation • The probabilistic techniques are often used for switching activity analysis • The simplest method to implement signal gating is to put an AND/OR gate at the signal path to stop the propagation of the signal when it needs to be masked • Another method is to use a latch or flip flop to block the propagation of the signal • Sometimes a transmission gate or tristate buffer can be used in place of a latch if charge leakage is not a concern
- 204. Signal Gating • The various logic implementation of signal gating is shown below • The signals at the bottom of the circuits are control signals used to suppress the source signal on the left from propagating to the gated signal on the right
- 205. Logic Encoding • The logic designer of a digital circuit often has the freedom of choosing a different encoding scheme as long as the functional specification of the circuit is met • For Eg. An 8 bit counter can be implemented using the binary counting sequence or the gray code sequence • Different encoding implementation often lead to different power, area and delay tradeoff • The encoding techniques require the knowledge of signal statistics in order to make design decisions • The next slide discusses some techniques for using different logic encoding to achieve low power consumption
- 206. Binary versus Gray Code Counting • Consider two n-bit counters implemented with Binary and Gray code counting sequences • The counting sequences of the two counters are shown below
- 207. Binary versus Gray Code Counting • Toggle activities of binary versus gray code counter • When n is large, the Binary counter has twice as many transitions as the Gray counter • Since the power dissipation is related to toggle activities, a Gray counter is generally more power efficient than a Binary counter
- 208. Bus Invert Encoding • Bus invert encoding is a low power encoding technique that is suitable for a set of parallel synchronous signals e.g.: off-chip busses • The architecture of bus invert encoding is illustrated below
- 209. Bus Invert Encoding • At each clock cycle, the data sender examines the current and next values of the bus and decides whether sending the true or the compliment signal leads to fewer toggles • Since the data signals on the bus may be complemented, an additional polarity signals is sent to the bus receiver to decode the bus data properly • The assertion of the polarity signal tells the receiver to invert the received bus signals Efficiency of bus invert encoding under uniform random signal
- 210. State Machine Encoding • A state machine is an abstract computation model that can be readily implemented using Boolean logic and flip flops as shown below • In today's logic synthesis environment, a state transition graph is specified by the designer and the synthesis system will produce a gate level circuit based on the machines specification • The state transition graph is a functional description of a machine specifying the inputs and outputs of the machine under a particular state and its transition to the next state
- 211. State Machine Encoding • The very first step of a state machine synthesis process is to allocate the state register and assign binary codes to represent the symbolic states. This process is called the encoding of a state machine • The encoding of a state machine is one of the most important factors that determine the quality (area, power, speed etc) of the gate level circuit • Transition Analysis of State Encoding – The key parameter to the power efficiency of state encoding is the expected number of bit transitions E[M] in the state register – Another parameter is the expected number of transitions of output signals • In general machines with lower E[M] are more power efficient because – Fewer transitions of the state register lead to low power dissipation and – Fewer transitions are propagated into the combinational logic of the machine
- 212. State Machine Encoding • Consider two functionality identical state machines M1 and M2 with different encoding as shown below • The binary codes in the state bubbles indicate the state encoding • The labels at the state transition edges represent the probabilities that transition will occur at any given clock cycle • The sum of all edge probabilities equals to unity • The expected number of state bit transitions E[M] is given by the sum of products of edge probabilities and their associated number of bit flips as dictated by the encoding
- 213. State Machine Encoding • However, a state encoding with the lowest E[M] may not be the one that results in the lowest overall power dissipation • The reason is that the particular encoding may require more gates in the combinational logic, resulting in more signal transitions and power • The synthesized area and power dissipation of some randomly encoded state machines is shown below
- 214. Precomputation Logic • Precomputation logic optimization is a method to trade area for power in a synchronous digital circuit • The principle of precomputation logic is to identify logical conditions at some inputs to a combinational logic that is invariant to the output • Since those input values do not affect the output, the input transitions can be disabled to reduce switching activities • One variant of precomputation logic is shown below
- 215. Precomputation Logic • Let R1 and R2 are registers with a common clock feeding a combinational logic circuit with a known Boolean function f(x) • Due to the nature of the function f(x), there may be some conditions under which the output of f(x) is independent of the logic value of R2 • Under such conditions, we can disable the register loading of R2 to avoid causing unnecessary switching activities, thus conserving power • The Boolean function f(x) is correctly computed because it receives all required values from R1 • To generate the load disable signal to R2, a precomputation Boolean function g(x) is required to detect the condition at which f(x) is independent of R2 • g(x) depends on the input signals of R1 only because the load disable condition is independent t of R2, otherwise f(x) will depend on the inputs of R2 when the load disable signal is active
- 216. Binary comparator function using Precomputation Logic • Assuming uncorrelated input bits with uniform random probabilities where every bit has an equal probability of 0 or 1 • There is 50% probability that and the register R2 is disabled in 50% of the clock cycles • Therefore, with only one additional 2 input XOR gate, we have reduced the signal switching activities of the 2n-2 least significant bits at R2 to half of its original expected switching frequency 1n nA B
- 217. Binary comparator function using Precomputation Logic • Also, when the load disable signal is asserted, the combinational logic of the comparator has fewer switching activities because the outputs of R2 are not switched • The extra power required to compute is negligible compared to the power saving even for moderate size of n • The precomputation scheme based on Shannon's decomposition is states that a Boolean function f(x1,…,xn) can be decomposed with respect to the variable xi as follows • The equation allows us to use xi as the load disable signal • When xi= 0 (xi= 1)the inputs to the logic block fxi can be disabled n nA B Alternate Precomputation Architectures 1,......, i i in i x x f x x x f x f
- 218. Alternate Precomputation Architectures • The multiplexer selects the output of the combinational logic block that is active • This means that only one combinational logic block is activated at any clock cycle • Power saving is saving is achieved if each of the two decomposed logic blocks consumes less power than a direct implementation • However, the precomputation architecture consumes more area and delay in general A precomputation architecture based on Shannon’s decomposition
- 219. Latch based Precomputation Architecture • The latch based precomputation architecture is shown below • This architecture is also called guarded evaluation because some inputs to the logic block C2 are isolated when the signals are not required, to avoid unnecessary transition • Transmission gates may be used in place of the latches if the charge storage and noise immunity conditions permit Latch based precomputation architecture
- 220. Design Issues in Precomputation Logic Technique • The basic design steps with precomputation logic are as follows: 1. Select precomputation architecture 2. Determine the precomputed inputs R1 and gated inputs R2 given the function f(x) 3. With R1 and R2 selected, find a precomputation logic function g(x). 4. Note that g(x) is not unique and the choice greatly affects the power efficiency. The function g(x) may also fail to exist for poor choices of R1 and R2 5. Evaluate the probability of precomputation condition and the potential power savings. Make sure that the final circuit is not overwhelmed by the additional logic circuitry and power consumption required to compute g(x) 6. After R1, R2 and g(x) are determined, the precomputation logic can be synthesized using a logic synthesis tool
- 221. UNIT-III Low power Architecture & Systems
- 222. Architecture & Systems • The most common abstraction level for manual design is at the so called register level transfer • At this level, all synchronous registers, latches and the combinational logic between the sequential elements are described in a hardware description language such as Verilog or VHDL • The description is then transferred to logic gate implementation • Hence, the designer can implement more complex design • More than register level transfer, the analysis and synthesis of digital circuits are still being pushed toward even higher level of abstraction for manual implementation E.g. macro block level specification • The register level transfer and macro block level will be discussed in architecture and systems • Low power architecture techniques are important because the design analysis, verification and automated synthesis begin at this level • The choice of clocking strategy, parallelism, pipelining, component organization, etc are the issues to be considered at this level
- 223. Power & performance management • Power management – It refers to a general class of low power techniques that carefully manage the performance and throughput of a system based on its computation needs to achieve low power goals • Microprocessor sleep modes – The most important and successful use of power management is to deactivate some functional units when no computation is required – The tradeoff is to justify the additional hardware and design complexity in managing the various functional units – At architecture design, this is attractive technique because little hardware and design complexity is needed to achieve substantial power saving
- 224. Power & performance management • An example of power management schemes can been seen with Motorola’s PowerPC 603 processor design – The CPU has three primary power save modes called DOZE, Nap and SLEEP controlled by software – DOZE mode – The most functional units of the processor are stopped except the on chip cache memory to maintain cache coherency – NAP mode – The cache is also turned off to conserve power and the processor wakes up after a fixed amount of time or upon external interrupt – SLEEP mode – The entire processor clock may be halted and only an external reset or interrupt can resume its operation
- 225. Power & performance management • The aim is to put more functional units in idle when the processor goes into a deeper sleep mode • However, it requires more latency to resume computation from a deeper sleep mode • This allows the software to choose the proper power saver mode based on the computation requirements of the processor • As the computational requirements becomes less, the processor can be put into deeper sleep modes without any perceivable loss in performance • The dynamic power management mode refers to the application of clock gating at the macro module level in which unused functional units are not clocked
- 226. Portable computer Application • When an application program is running and the processor is waiting for a key stroke, it can be put into DOZE mode • If the processor is waiting for disk access, it may go into the NAP mode • If the processor has been idle for a long time and the power saver is activated, the processor can be put into the SLEEP mode Power saver modes of Motorola’s Power PC 603
- 227. Performance management • Performance matching is another important issue in architecture level management • The performance requirement of a system is typically prescribed from a high level perspective • Since its is a waste of power to design and operate a circuit beyond its performance requirements, it is important to balance the throughput of each subsystem • One from of performance management is to scale down the operating voltage on parts of the system that are not performance critical • The operating voltage of a subsystem can be chosen to match its speed requirement • This allows the performance and power tradeoff to be applied to the subsystem level and increases the potential for power efficiency
- 228. Adaptive performance management by voltage control • The throughput of the data processing unit is dependent on the operating voltage, which is typical of an asynchronous processing system • The load sensor checks the FIFO buffer length to determine the workload of the system • If the queue is long, the voltage of the system is increased so that the throughput is accelerated • The voltage is scaled down during light loading to conserve power
- 229. Adaptive filtering • The system level design technique for low power can be made through the design of digital filters • The basic principle is to adjust the filters order length depending on the noise characteristics of the input signal • Two basic classes of digital filter are FIR and IIR filter as shown below
- 230. Adaptive filtering • The length of the delay chain of the filter is called the order of the filter • Higher order filter achieves a higher quality of filtering – Attenuation between the passband and the stopband is larger and the slope is steeper • The filter responses of the three lowpass filters with increasing higher order is shown below • The quality or order length requirement of a digital filter depends on – The desired SNR of the output – The noise energy level of the input signal
- 231. Adaptive filtering • For a fixed order filter, if the input signal is higher than normal (ie input is not noisy), the output SNR may be much higher than the required by the specification • This means that lower order filtering should be sufficient to achieve the specified output SNR • Also, the low order filter requires less power to operate because the amount of computation is less • This motivates a low power technique to adaptively adjust the filter order based on the input SNR • When the input signal is less noisy, the filter order is reduced to conserve power • When the input noise increases, the filter order is lengthened accordingly • The output SNR of the filter will be maintained above the minimum threshold specified by the design thus achieving the desired output signal quality
- 232. Adaptive filtering • A general framework for updating filter order length • The filter order update algorithm is as follows – Order(n) is the filter order, ESB is the stopband energy of the filter and alpha is the const – Variable N is a const in which the filter order is adjusted at each sample – Q(n) represents the noise energy measured at a particular output sample n
- 233. Switching Activity Reduction • Switching activities are the biggest cause of power dissipation in most CMOS digital systems • In order to do computation, switching activities cannot be avoided • However, some switching activities do not contribute to the actual contribution and should be eliminated • The suppression of switching activities always involves some tradeoff decisions • In general hardware logic is required to suppress unwanted switching activities and the additional logic itself consumes power • Guarded Evaluation – It is a technique to reduce switching activities by adding latches or blocking gates at the inputs of a combinational module if the inputs are not used
- 234. Guarded Evaluation • As shown in figure below the result of multiplication may or may not be used depending on the condition selection of the multiplexer • To reduce switching activities, latches are added at the input of the multiplexer • The latches are transparent when the result of multiplication is to be used • Instead of using latches, which increase the area substantially, we can also use AND gates to mask one or both inputs of the multiplier to zero
- 235. Bus Multiplexing • One common way to reduce hardware resources in a digital system is to share long data buses with time multiplexing, as shown in left Fig • At even clock cycles, S1 uses the shared bus to send data to destination D1 while at odd cycles, source S2 send data to D2 • The switching activity characteristics of the shared and dedicated buses, as shown in right Fig
- 236. Glitch Reduction by Pipelining • Glitches are unwanted switching activities that occur before a signal settles to its intended value • They are caused by transitions at multiple inputs of a gate within a clock cycle • Glitches are undefined and unpredictable behavior of a circuit that cannot be analyzed deterministically • Glitches of a signal node are dependent on the logic depth of the node • A logically deep node is typically affected by more primary input switching and therefore more susceptible to glitches • One way to reduce glitches is to shorten the depth of combinational logic by adding pipeline registers
- 237. Parallel Architecture with Voltage Reduction • Parallelism has been traditionally used to improve the computational throughput of high performance digital systems • Parallelism essentially trades area off for a lower operating frequency or higher throughput • The same tradeoff idea can also be applied to achieve power reduction • In a uniprocessing system, the power dissipation is given by – Where C is the average capacitance switched and V is the operating voltage of the uniprocessing system • The power of parallel system is given by • 60% power reduction is achieved by parallelism
- 238. Parallel Architecture with Voltage Reduction Power dissipation of uniprocessing and parallel processing systems
- 239. Power Efficiency by Pipelining • The above parallel technique increases the chip area by at least twice • If the area penalty of a parallel system is prohibitive, pipelining can offer similar tradeoff results with less area overhead but more complexity in controller design
- 240. Flow Graph Transformation • Here, we focus on a system level technique for the design of special purpose architecture DSP systems • Such systems are characterized by computation intensive data path operations with simple control structures • The system architecture can be represented by a control data flow graph • The graph consists of control nodes and data nodes connected by directed edges • Control nodes change the flow of data that pass through it • Data nodes provide computation operators for the input data streams such as addition, multiplication, shift etc • The graph edges represent the data streams of the system
- 241. Flow Graph Transformation • A control data graph expresses the conceptual computation algorithm of the system • It provides basic information such as the number of control and data operators, their ordering dependencies and the inherent parallelism that may exist • The path from system input to output is a good estimate of the delay of the system • The number of operator nodes is an estimate of the computation needs and the complexity of the system • A control data flow graph is often the starting point to derive the actual hardware architecture of a system by mapping the operators and edges to actual hardware modules and busses respectively • A controller schedules the operators to perform the desired computation in the proper order
- 242. Flow Graph Transformation • The below example illustrates a simple mapping from the control data flow graph to the system hardware architecture
- 243. Operator Reduction • The transformations preserve the functionality of the graph so that the resulting graph is computationally equivalent to the original work • The transformed graph represents an alternate hardware implementation with a different tradeoff • If the system operating voltage is variable, the transformed graph may offer a lower voltage implementation by reducing the worst case delay path • An example of operator transformation is illustrated below Constant multiplication versus shift and addition
- 244. Operator Reduction • The multiplication by an integer constant can be replaced by binary shift (multiplication by powers of 2) and add / subtract operations, which may be power efficient • Rearranging the order of computation can also lead to fewer operations and lower power as shown below Associative Transformation
- 245. Operator Reduction • Also the direct and transformed flow graphs of coordinate rotation operation is shown below
- 246. Loop Unrolling • The control data flow graphs of DSP systems often contain loops, as a result of recursive computations • An important technique for flow graph transformation is to unroll the loop • Loop unrolling is a method to apply parallelism to the computation • Consider a simple recursive computation of an IIR filter • We can unroll the loop once and obtain • After loop unrolling, two output values are produced using two input values in a single computation cycle • The unrolled computation structure increases the computation by more than twice
- 247. Loop Unrolling • The data flow graphs of the original and unrolled computation are illustrated below
- 248. Loop Unrolling • If the unrolled computation structure is implemented directly, the power efficiency should be worse than the original implementation because of the increased computation • However, the unrolled structure allows us to apply pipelining by adding pipeline registers on the graph edges crossing the vertical dashed line • With pipelining , the longest delay path of the unrolled graph is identical to the original path (i.e. a multiplication followed by a addition) • Since the unrolled graph produces two outputs simultaneously, it can be implemented with half the operating frequency of the original path • Thus, its critical delay is identical but the operating frequency is halved • This allows us to lower the operating voltage to improve the overall system power efficiency
- 249. UNIT-III Power Reduction in Clock Networks
- 250. Introduction • In a synchronous digital chip, the clock signal is generally one with the highest frequency • The clock signal typically drives a large load because it has to reach many sequential elements distributed throughout the chip • Therefore, clock signals have been a notorious source of power dissipation because of high frequency and load • It has been observed that clock distribution can take up to 40% of the total power dissipation of a high performance microprocessor • Many techniques have been devoted to the power efficiency of clock generation and distribution
- 251. Clock Gating • Clock gating is the most popular method for power reduction of clock signals • When the clock signal of a fundamental module (ALUs, memories etc) is not required for some extended period, we use a gating function (NAND or NOR gate) to turn off the clock feeding the module • The gating signal should be enabled or disabled at a much slower rate compared to the clock frequency • Clock gating saves power by reducing unnecessary clock activities inside the gated module
- 252. Reduced Swing Clock • Referring P = C V2 f equation, the most attractive parameter for power reduction is the voltage swing V due to the quadratic effect • Also, it is difficult to reduce the load capacitance or frequency of clock signals due to performance reasons • Consider a 5 V digital CMOS chip with a N – transistor threshold voltage of 0.8 V • N – transistor will turn on if the clock signal is above 0.8 V • Hence, if we limit the swing of the N – transistor clock signal from 0 to 2.5 V (half swing) • Further, the on – off characteristics of all N – transistor remains digitally identical • Similar observation can be made for the clock signal feeding a P – transistor
- 253. Reduced Swing Clock • The figure below illustrates the clock waveform of the half swing clocking scheme
- 254. Reduced Swing Clock • Generating the half swing clock signal is also relatively simple using the charge sharing principle with stacked inverters • The circuit to generate the clock waveform is shown below
- 255. Reduced Swing Clock • The capacitance C1, C2, C3 and C4 are the parasitic capacitances of the circuit • CA and CB are add on capacitance much larger than the parasitic capacitance • From the principle of charge sharing, when CLK is low the voltage at VH is given by • When CLK is high, the voltage is • The circuit generates two-phase, half-swing waveforms
- 256. Reduced Swing Clock • Creating large on chip capacitance CA and CB is difficult and may require an external pin for the node VH • A simpler charge sharing circuit is shown below • The circuit relies on the parasitic loading of the clock lines CP and CN to achieve the charge sharing effect • The capacitance CP and CN should be equalized to obtain the proper half swing waveform
- 257. Oscillator Circuit for Clock Generation • The simplest oscillator circuit is shown below • The inverter I0 serves as a gain amplifier for the feedback oscillator and the inverter I1 reshapes the waveform to obtain a proper digital clock signal • For good stability of oscillation, we like to set a large gain on the inverter I0 • However, a large gain results in large voltage swing and short circuit current that increase the power dissipation • Hence, it is important to tune the transistor sizes of the inverters to achieve a trade off between quality of oscillation and power dissipation of the circuit
- 258. Frequency Division and Multiplication • A power reduction scheme using frequency division and multiplexing is shown below • This is common for off chip clock signals because they drive very large capacitance
- 259. Frequency Division and Multiplication • Off chip clock signal runs at a slower speed and on chip PLL circuit is used to multiply the frequency to the desired rate • The slower signal also eases the off chip signal distribution in terms of electromagnetic interference and reliability • The frequency multiplier N is a trade off between power dissipation and the PLL circuit complexity • Larger values of N lead to better power dissipation but increases the design complexity and performance of the PLL circuit
- 260. Algorithm & Architectural Level Methodologies
- 261. Agenda • Recap • Power reduction on – Gate level – Architecture level – Algorithm level – System level 265
- 262. Recap: Problems of Power Dissipation 266 Continuously increasing performance demands Increasing power dissipation of technical devices Today: power dissipation is a main problem High Power dissipation leads to: High efforts for cooling Increasing operational costs Reduced reliability Reduced time of operation Higher weight (batteries) Reduced mobility
- 263. Recap: Consumption in CMOS Voltage (Volt, V) Water pressure (bar) Current (Ampere, A) Water quantity per second (liter/s) Energy Amount of Water 267 CL Energy consumption is proportional to capacitive load! 0 1
- 264. Recap: Energy and Power 268 Watts time Power is height of curve Watts time Energy is area under curve Approach 1 Approach 2 Approach 2 Approach 1 Energy = Power * time for calculation = Power * Delay
- 265. Recap: Power Equations in CMOS P = α f CL VDD 2 + VDD Ipeak (P01 + P10 ) + VDD Ileak 269 Dynamic power (≈ 40 - 70% today and decreasing relatively) Short-circuit power (≈ 10 % today and decreasing absolutely) Leakage power (≈ 20 – 50 % today and increasing)
- 266. Recap: Levels of Optimization 270 System Algorithm Architecture Gate Transistor T T + ST1 ALU MEM MEMMP3 Savings Speed Error > 70 % 40-70 % 25-40 % 15-25 % 10-15 % Seconds Minute Minutes Hour Hours > 50 % 25-50 % 15-30 % 10-20 % 5-10 % nach Massoud Pedram
- 267. Recap: Logic Restructuring Chain implementation has a lower overall switching activity than tree implementation for random inputs BUT: Ignores glitching effects 271 Logic restructuring: changing the topology of a logic network to reduce transitions A B C D F A B C D Z F W X Y0.5 0.5 (1-0.25)*0.25 = 3/16 0.5 0.5 0.5 0.5 0.5 0.5 7/64 = 0.109 15/256 3/16 3/16 = 0.188 15/256 AND: P01 = P0 * P1 = (1 - PAPB) * PAPB
- 268. Recap: Input Ordering Beneficial: postponing introduction of signals with a high transition rate (signals with signal probability close to 0.5) 272 A B C X F 0.5 0.2 0.1 B C A X F 0.2 0.1 0.5 (1-0.5x0.2)*(0.5x0.2)=0.09 (1-0.2x0.1)*(0.2x0.1)=0.0196 AND: P01 = (1 - PAPB) * PAPB
- 269. Recap: Glitching 273 ABC X Z 101 000 Unit Delay A B X ZC
- 270. Design Layer: Gate Level • Basic elements: – Logic gates – Sequential elements (flipflops, latches) • Behavior of elements is described in libraries 274
- 271. Dynamic Power and Device Size • Device Sizing (= changing gate width) Affects input capacitance Cin Affects load capacitance Cload Affects dynamic power consumption Pdyn • Optimal fanout factor f for Pdyn is smaller than for performance (especially for large loads) – e.g., for Cload=20, Cin=1 fcircuit = 20 fopt_energy = 3.53 fopt_performance = 4.47 • For Low Power: avoid oversizing (f too big) beyond the optimal 275 1 2 3 4 5 6 7 0 0.5 1 1.5 fanout fnormalizedenergy fcircuit=1 fcircuit=2 fcircuit=5 fcircuit=10 fcircuit=20
- 272. VDD versus Delay and Power • Delay (td) and dynamic power consumption (Pdyn) are functions of VDD 276 0 1 2 3 4 5 6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 Supply voltage (VDD) RelativeDelaytd 0 2 4 6 8 10 RelativePdyn td Pdyn
- 273. Multiple VDD • Main ideas: – Use of different supply voltages within the same design – High VDD for critical parts (high performance needed) – Low VDD for non-critical parts (only low performance demands) • At design phase: – Determine critical path(s) (see upper next slide) – High VDD for gates on those paths – Lower VDD on the other gates (in non-critical paths) – For low VDD: prefer gates that drive large capacitances (yields the largest energy benefits) • Usually two different VDD (but more are possible) 277
- 274. Multiple VDD cont’d • Level converters: – Necessary, when module at lower supply drives gate at higher supply (step-up) – If gate supplied with VDDL drives a gate supplied with VDDH then PMOS never turns off – Possible implementation: • Cross-coupled PMOS transistors • NMOS transistor operate on reduced supply – No need of level converters for step-down change in voltage – Reducing of overhead: • Conversions at register boundaries • Embedding of inside flipflop 278 VDDH Vin Vout VDDL
- 275. Data Paths • Data propagate through different data paths between registers (flipflops - FF) • Paths mostly differ in propagation delay times • Frequency of clock signal (CLK) depends on path with longest delay critical path 279 FF FF FF FF FF FF FF FF FF CLK CLK CLK Paths Path
- 276. Data Paths: Slack 280 B A Y C time all Inputs of G1 arrived G1 ready with evaluation delay of G1 all inputs of G2 arrived Slack for G1 B A Y C G1 G2
- 277. Multiple VDD in Data Paths • Minimum energy consumption when all logic paths are critical (same delay) • Possible Algorithm: clustered voltage-scaling – Each path starts with VDDH and switches to VDDL (blue gates) when slack is available – Level conversion in flipflops at end of paths 281 Connected with VDDL Connected with VDDH
- 278. Design Layer: Architecture Level • Also known as Register transfer level (RTL) • Base elements: – Register structures – Arithmetic logic units (ALU) – Memory elements • Only behavior is described (no inner structure) 282
- 279. Clock Gating • Most popular method for power reduction of clock signals and functional units • Gate off clock to idle functional units • Logic for generation of disable signal necessary Higher complexity of control logic Higher power consumption Critical timing critical for avoiding of clock glitches at OR gate output Additional gate delay on clock signal 283 R e g clock disable Functional unit
- 280. Clock Gating cont’d • Clock-Gating in Low-Power Flip-Flop 284 D QD CLK
- 281. Clock Gating cont’d • Clock gating over consideration of state in Finite-State- Machines (FSM) 285 Combinational logic Latch Clock activation logic Flip-flops PI CLK PO
- 282. Clock Gating: Example 286 DSP/ HIF DEU MIF VDE 896Kb SRAM 90% of FlipFlops clock-gated 70% power reduction by clock-gating MPEG4 decoder 10 8.5mW 0 155 30.6mW 20 25 Without clock gating With clock gating Power [mW]
- 283. Recap: VDD versus Delay and Power Dynamic Power can be traded by delay 287 0 1 2 3 4 5 6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 Supply voltage (VDD) RelativeDelaytd 0 2 4 6 8 10 RelativePdyn td Pdyn
- 284. A Reference Datapath 288 Combinational logic OutputInput Register Register CLK Supply voltage = Vref Total capacitance switched per cycle = Cref Clock frequency = fClk Power consumption: Pref = CrefVref 2fclk Cref
- 285. Parallel Architecture 289 Comb. Logic Copy 1 Comb. Logic Copy 2 Comb. Logic Copy N Register Register RegisterRegister Nto1multiplexer Multiphase Clock gen. and mux control Input Output CK fclk fclk/N Each copy processes every Nth input, operates at reduced voltage Supply voltage: VN ≤ Vref N = Deg. of parallelism fclk/N fclk/N
- 286. Pipelined Architecture • Reduces the propagation time of a block by factor N Voltage can be reduced at constant clock frequency • Constant throughput • Functionality: 290 DataData CLK Area A CLK CLK A/N A/NA/N
- 287. Parallel Architecture: Example • Reference Data path (for example) • Critical path delay Tadder + Tcomparator (= 25 ns) fref = 40 MHz • Total capacitance being switched = Cref • VDD = Vref = 5V • Power for reference datapath = Pref = Cref Vref 2 fref 291 A B
- 288. Parallel Architecture: Example cont’d • The clock rate can be reduced by half with the same throughput fpar = fref / 2 • Vpar = Vref / 1.7, Cpar = 2.15 Cref • Ppar = (2.15 Cref) (Vref / 1.7)2 (fref / 2) = 0.36 Pref 292 Area = 1476 x 1219 µ2
- 289. Pipelined Architecture: Example 293 fpipe = fref, , Cpipe = 1.1 Cref , Vpipe = Vref / 1.7 Voltage can be dropped while maintaining the original throughput Ppipe = CpipeVpipe 2 fpipe = (1.1 Cref) (Vref/1.7)2 fref = 0.37 Pref
- 290. Approximate Trend N-parallel proc. N-stage pipeline proc. Capacitance N*Cref Cref Voltage Vref/N Vref/N Frequency fref/N fref Dynamic Power CrefVref 2fref/N2 CrefVref 2fref/N2 Chip area N times 10-20% increase 294
- 291. Guarded Evaluation • Reduction of switching activity by adding latches at inputs • Latch preserves previous value of inputs to suppress activity • Could also use AND gates to mask inputs to zero = forced zero 295 A Multiplier B C condition Multiplier B C A Latch condition
- 292. Precomputation • Identify logical conditions at inputs that are invariant to the output – Since those inputs don’t affect output, disable input transitions – Trade area for energy 296 Outputs Precomputation logic Precomputed inputs Gated inputs g(X) Combination logic f(X) g(X) R2 R1 Load disable
- 293. Precomputation: Design Issues • Design steps 1. Selection of precomputation architecture 2. Determination of precomputed and gated inputs (Register R1 should be much smaller than R2) 3. Search good implementation for g(X) 4. Evaluation of potential energy savings based on input statistics (if savings not sufficient go to step 2 or 3 and try again) • Also works for multiple output functions where g(X) is the product of gj(X) over all j 297
- 294. Precomputation: Example • Binary Comparator 298 A > B n-bit binary value comparator A > BR2 R1 Load disable An = Bn An Bn An-1 A1 Bn-1 B1 Can achieve up to 75% power reduction with 3% area overhead and 1 to 5 additional gate delays in worst case path
- 295. Adder Design • Various algorithms exist to implement an integer adder – Ripple, select, skip (x2), Look-ahead, conditional-sum. – Each with its own characteristics of timing and power consumption. 299 FAFAFAFAFA Ripple Carry FAFAFAFA Variable/Fixed Width Carry Skip FAFAFAFA Carry Look-ahead FAFAFAFA FAFA 0 1 Carry Select
- 296. Adder Design • Adders differ in Energy and delay Different adders for different applications Also true for other units (multiplier, counter, …) 300 Energy (pJ ) Delay (nSec ) Ripple Carry 117 54.27 Constant Width Carry Skip 109 28.38 Variable Width Carry Skip 126 21.84 Carry Lookahead 171 17.13 Carry Select 216 19.56 Conditional Sum 304 20.05
- 297. Bus Power • Buses are significant source of power dissipation – 50% of dynamic power for interconnect switching (Magen, SLIP 04) – MIT Raw processor’s on-chip network consumes 36% of total chip power (Wang et al. 2003) • Caused by: – High switching activities – Large capacitive loading 301 Ain Bin Cin Din Wout Xout Yout Zout Bus drivers Bus receivers Bus
- 298. Bus Power Reduction For an n-bit bus: Pbus = n* αfClkCloadVDD 2 Alternative bus structures Segmented buses (lower Cload) Charge recovery buses Bus multiplexing (lower fClk possible) Minimizing bus traffic (n) Code compression Instruction loop buffers Minimization of bit switching activity (fclk) by data encoding Minimize voltage swing (VDD 2) using differential signaling 302
- 299. Reducing Shared Resources • Shared resources incur switching overhead • Local bus structures reduce overhead 303 Global bus architecture Local bus architecture
- 300. Reducing Shared Resources cont’d • Bus segmentation – Another way to reduce shared buses – Control of bus segment by controller blocks (B) 304 Shared Bus B B Segmented Bus
- 301. Design Layer: Algorithm Level • Base elements: – Functions – Procedures – Processes – Control structures • Description of design behavior 305
- 302. Coding styles • Use processor-specific instruction style: – Variable types – Function calls style – Conditionalized instructions (for ARM) • Follow general guidelines for software coding – Use table look-up instead of conditionals – Make local copies of global variables so that they can be assigned to registers – Avoid multiple memory look-ups with pointer chains 306
- 303. Source-code Transformations • Minimize power-consuming activity: – Computation – Communication – Storage 307 A*B+A*C A*(B+C) for (c = 1..N) receive (A) B=c*A receive (A) for (c = 1..N) B=c*A for (c = 1..N) B[c] = A[c]*D[c] for (c = 1..N) F[c] = B[c]-1 for (c = 1..N) F[c] = A[c]*D[c]-1
- 304. Datapath Energy Consumption Algorithms can differ in power dissipation 308 0 2000 4000 6000 8000 10000 12000 14000 bubble.c heap.c quick.c SwitchedCapacitance(nF) Others Functional Unit Pipeline Registers Register File
- 305. Adaptive Dynamic Voltage Scaling (DVS) • Slow down processor to fill idle time • More Delay lower operational voltage • Runtime Scheduler determines processor speed and selects appropriate voltage • Transitions delay for frequencies ~150s • Potential to realize 10x energy savings 309 Active Idle Active Idle 3.3 V Active 2.4 V
- 306. Adaptive DVS: Example • Task with 100 ms deadline, requires 50 ms CPU time at full speed – Normal system gives 50 ms computation, 50 ms idle/stopped time – Half speed/voltage system gives 100 ms computation, 0 ms idle – Same number of CPU cycles but: E = C (VDD/2)2 = Eref / 4 – Dynamic Voltage Scaling adapts voltage to workload 310 Speed Time T1 T2 T1 T2 Idle Same work, lower energy Task Task Time
- 307. Design Layer: System Level • Basic Elements: – Complex modules – Processors – Calculation and control units – Sensors 311 ALU MEM MEM MP3
- 308. Dynamic Power Management • Systems are: – Designed to deliver peak performance, but … – Not needing peak performance most of the time • Components are idle sometimes • Dynamic power management (DPM): – Puts idle components in low-power non-operational states when idle • Power manager: – Observes and controls the system – Power consumption of power manager is negligible 312
- 309. Processor Sleep Modes • Software power control - power management DOZE Most units stopped except on-chip cache memory (cache coherency) NAP Cache also turned off, PLL still on, time out or external interrupt to resume SLEEP PLL off, external interrupt to resume 313 Deeper sleep mode consumes less power Deeper sleep mode requires more latency to resume
- 310. Processor Sleep Modes: Example • PowerPC sleep modes 314 Mode 66Mhz 80Mhz No power mgmt 2.18W 2.54W Dynamic power mgmt 1.89W 2.20W DOZE 307mW 366mW NAP 113mW 135mW SLEEP 89mW 105mW SLEEP without PLL 18mW 19mW SLEEP without clock 2mW 2mW 10 cycles to wake up from SLEEP 100us to wake up from SLEEP+
- 311. Transmeta LongRun • Applies adaptive DVS • LongRun policies: – Detection of different workload scenarios – Based on runtime performance information • After detection accordingly adaptation of: – Processor supply voltage – Processor frequency – Clock frequency always within limits required by supply voltage to avoid clock skew problems • Use of core frequency/voltage hard coded operating points Best trade-off between performance and power possible 315
- 312. Transmeta LongRun cont’d 316 0 10 20 30 40 50 60 70 80 90 100 300 400 500 600 700 800 900 1000 Frequency (MHz) %ofmaxpowerlconsumption 300 Mhz 0.80 V 433 Mhz 0.87 V 533 Mhz 0.95 V 667 Mhz 1.05 V 800 Mhz 1.15 V 900 Mhz 1.25 V 1000 Mhz 1.30 V Typical operating region Peak performance region
- 314. Battery aware design • Non-linear effects influence life time of batteries • “Rate Capacity” – If discharging currents higher than allowed real capacity goes under nominal capacity • “Battery Recovery” – Pulsed discharge increases nominal capacity – Based on recovery times – (as long there is no rate capacity effect) 318 1000 mAh (Standard Capacity) Discharge current (mA) Capacity(mAh) ( Rated Current) 125mA 1000 800 600 400 200 Available Charge (mA) time idle Discharge Current (mA) time
- 315. Diffusion Model from - Rakhmatov, Vrudula et al. 319 Electro-active species Fully charged battery Fully discharged After a recent discharge After Recovery Battery aware design cont’d Analytically very sound but computationally intensive Cannot be used for online scheduling decisions.
- 316. Battery aware design: Example 1 • Performance of a bipolar lead-acid battery subjected to six current impulses. Pulse length=3 ms, rest period=22 ms. 320 Current Battery Voltage Source: LaFollette, “Design and performance of high specific power, pulsed discharge, bipolar lead acid batteries”, 10th Annual Battery Conference on Applications and Advances, Long Beach, pp. 43– 47, January 1995.
- 317. Battery aware design: Example 2 Discharge profile A Discharge profile B Minimum average current ≠ Maximum battery life time 321 Profile Aver. Current [mA] Battery lifetime [ms] Specif. energy [Wh/Kg] A 123.8 357053 15.12 B 124.2 536484 18.58 Current[mA] Current[mA]
- 318. Backup 322
- 319. FSM: Clock-Gating • Moore machine: Outputs depend only on the state variables. – If a state has a self-loop in the state transition graph (STG), then clock can be stopped whenever a self-loop is to be executed. 323 Sj Si Sk Xi/Zk Xk/Zk Xj/Zk Clock can be stopped when (Xk, Sk) combination occurs.
- 320. Trend: Interconnects 324 Interconnects Example (very optimistic): 6–10 clock cycles in 50nm technology [Benini, 2002] Propagation delays of global wires will be a multiple of the clock cycle.
- 321. Bus Multiplexing 325 or • Number of bus transitions per cycle = 2 (1 + 1/2 + 1/4 + ...) = 4
- 322. Resource Sharing and Activity II 326
- 323. Bus Multiplexing • Sharing of long data buses with time multiplexing • Example: – S1 uses even cycles – S2 odd 327 S2 S1 D1 D2 S1 S2 D2 D1
- 324. Correlated Data Streams 0 0.5 1 14 12 10 8 6 4 2 0 Muxed Dedicated 328 Bit position MSB LSB Bitswitchingprobabilities For a shared (multiplexed) bus advantages of data correlation are lost (bus carries samples from two uncorrelated data streams) Bus sharing should not be used for positively correlated data streams Bus sharing may prove advantageous in a negatively correlated data stream (where successive samples switch sign bits) - more random switching
- 325. Disadvantages of Bus Multiplexing • If data bus is shared, advantages of data correlation are lost (bus carries samples from two uncorrelated data streams) • Bus sharing should not be used for positively correlated data streams • Bus sharing may prove advantageous in a negatively correlated data stream (where successive samples switch sign bits) - more random switching 329
- 326. Adaptive DVS cont’d • Implementation 330 Variable Power-Speed System FIFO Input Buffer Workload Filter Power-Speed Control Knob