Low Power Design Approach in VLSI
Download as PPTX, PDF9 likes7,140 views
The document discusses low power design approaches in VLSI, emphasizing the need for devices with lower power consumption and manageable delay. It outlines several techniques such as reverse body biasing, dual and multi-threshold CMOS, sleep transistors, and the sleepy stack method to achieve power reduction and improve performance. The key focus is on optimizing sub-threshold current and threshold voltage to reduce power dissipation in integrated circuits.
Low Power Design Approach in VLSI
- 1. Low Power Design Approach in VLSI
- 2. Introduction • In this electronic era of miniaturization of circuitry, there is a need of devices with less power consumption and short delay. • But in actual these both these parameters are contradictory to each other. If we improve the one, other one gets deteriorated because power delay product remains constant. • This suggests that there must be a different approach to achieve desired level of power with delay in limits which can be tolerated in circuit.
- 3. Why to reduce Power Consumption ? • To optimise battery Back-Up in mobile Devices. • To ensure stable and Optimum working of circuit. • Implementation of integrated circuitry in a chip results in very high power consumption and dissipation. • For longer device life.
- 4. Basic Concept Behind Power Reduction.....! • The power reduction approach can be implemented by reducing the sub-threshold current which in-turn is responsible for lower static power consumption in circuit. • Power consumption is proportional to the sub threshold current, if we decrease the current we can decrease the power consumption and this current is decreased if we increase the threshold voltage. • So, basically to ensure less power dissipation, threshold voltage level can be increased.
- 5. Low Power Strategies • Reverse Body Biasing • Dual Threshold CMOS • Multi Threshold CMOS • Sleep transistor • Sleepy Stack
- 6. Reverse Body Biasing technique: In this technique we provide voltage to the Body (Substrate) terminal of MOSFET so that there is an increase in the threshold voltage which further decreases the sub threshold current that ultimately helps in reduction of the power dissipation because power is proportional to the current.
- 7. Dual Threshold CMOS: This approach is implemented by using different CMOS with different threshold voltage to decrease the power consumption. It mainly decreases the sub threshold leakage current. But at the same time there is certain increase in the number of MOSFETs which altogether increases the delay in circuit.
- 8. Multi Threshold CMOS: Multiple threshold CMOS technique makes use of both high and low threshold MOS in the same circuit. The main concern is to selectively change the threshold voltages in order to improve the power consumption with improved the circuit speed. Simple method of making MOS with multiple threshold voltages is to apply different bias voltages (VB) to the body or substrate terminal of the transistors. Other methods include changing the thickness of gate oxide or dopant concentration in the MOS channel. This approach overcomes the speed limitation which is present in DT CMOS
- 9. Sleep Transistor: • In this technique, the sleep transistors having high threshold value is inserted between the Vdd and the pull up network and another transistor is inserted between the pull down network and ground. • These transistors switch ON when circuit is ON and switch off when circuit is idle. By cutting off the power supply, this can reduce the leakage power. • But when it is in cut off state, it does not hold states, it destruct the states.
- 10. Sleepy Stack approach: • This technique divides the single transistor into two half-size transistors. In this approach every half-transistor is added in series so that there is small leakage current. • It also adds sleepy transistors to disconnect the power supply and ground from the network so that there is no power consumption in off mode.
- 11. • If you still have any query about low power design approach in VLSI then no need to worry just contact us and get the answers for your all question. • And if you are a M.tech or PhD students and seeking guidance for your VLSI projects then contact us to get instant help.
- 12. About Us • Company : SiliconMentor • Website: http://www.siliconmentor.com/
- 13. Thank You