low pw and leakage current techniques for cmos circuits
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This document discusses various techniques to reduce leakage power in CMOS circuits, including the sleep mode approach, stack mode approach, leakage feedback approach, sleepy stack approach, and sleepy keeper approach. It then proposes a new LECTOR technique which introduces two leakage control transistors between the pull-up and pull-down circuits to ensure that one transistor is always near cutoff, reducing leakage power dissipation. The document concludes that leakage reduction is important for VLSI circuit design as scaling continues, and that the LECTOR method is effective at reducing leakage power in both active and standby modes.
low pw and leakage current techniques for cmos circuits
- 1. LEAKAGE POWER REDUCTION TECHNIQUES FOR CMOS CIRCUIT DESIGN Submitted by: Submitted to: Anamika Pancholi Ms. Vandana Niranjan 02702072014 Asst. Professor, ECE Dept. M.Tech(VLSI Design) IGDTUW, Delhi 2014‐2016
- 2. CONTENTS Introduction Previous Work Sleep Mode Approach Stack Mode Approach Leakage Feedback Approach Sleepy Stack Approach Sleepy Keeper Approach Proposed Lector Technique Conclusion
- 3. Introduction In order to achieve high density and high performance, CMOS technology feature size and threshold voltage have been scaling down for decades. As the feature size becomes smaller, shorter channel lengths result in increased subthreshold leakage current through a transistor when it is off. Low threshold voltage also results in increased subthreshold leakage current because transistors cannot be turned off completely.
- 4. Leakage power consumption is an important issue in DSM CMOS VLSI circuit. The main Contribution of Power dissipation in CMOS circuit increases with the reduction of channel length, Threshold voltage and gate oxide thickness. The power dissipation of a logic gate is given by Pavg /gate = Pswitching + Pshort circuit +Pleakage Subthreshold leakage current (Isub) in MOS transistors, which occurs when the gate voltage is below the threshold voltage and mainly, consists of diffusion current.
- 5. •Diode reverse bias current–I1 •Sub threshold current – I2 •Gate induced drain leakage – I3 •Gate oxide tunneling – I4 Fig.1. Leakage Mechanism in Short-Channel NMOS Transistor
- 6. Leakage Power Reduction Techniques Sleep Mode Approach • An additional "sleep" PMOS transistor is placed between VDD and the pull-up network of a circuit and • An additional "sleep" NMOS transistor is placed between the pull-down network and GND. These sleep transistors turn off the circuit by cutting off the power rails. • By cutting off the power source, this technique can reduce leakage power effectively Fig.2. Sleep Approach NAND gate
- 7. Stack Approach In the stack approach, which forces a stack affect by breaking down an existing transistor into two half size transistors. Subthreshold leakage is exponentially related to the threshold voltage of the device, and the threshold voltage changes due to body effect. From these two facts, one can reduce the subthreshold leakage in the device by stacking two or more transistors serially . Fig.3. Stack Approach based 2 input NAND gate
- 8. Leakage Feedback Approach In this approach we use two parallel PMOS transistor above pull up network and Vdd . To provide the inverting output of the circuit we connect inverter at the output, an inverter provides the proper logic feedback to both pull down NMOS(S') and pull up PMOS(S) sleep transistor as shown in Fig.4. This two transistor enhance the circuit performance and maintain the proper logic of the circuit during standby mode. Fig.4. Leakage Feedback Approach
- 9. SLEEPY STACK APPROACH Fig. 5. Sleepy Stack Approach based 2 input NAND gate
- 10. The main idea behind the sleepy stack technique is to combine the sleep transistor approach during active mode with the stack approach during sleep mode. The stacked transistors in the sleepy stack approach suppress leakage current. Although the sleep transistors are turned off, the sleepy stack structure maintains exact logic state. The leakage reduction of the sleepy stack structure occurs in two ways. First, leakage power is suppressed by high- transistors, which are applied to the sleep transistors and the transistors parallel to the sleep transistors.
- 11. Second, stacked and turned off transistors induce the stack effect which also suppresses leakage power consumption. By combining these two effects, the sleepy stack structure achieves ultra-low leakage power consumption during sleep mode while retaining exact logic state The price for this, however, is increased area
- 12. Sleepy Keeper Approach In this approach combination of PMOS and NMOS transistor which is connected paralleled inserted between pull up network and Vdd and pull down and GND, NMOS transistor of pull up sleep transistor connected PMOS pull down sleep transistor. This approach reduces the leakage power efficiently and maintains the proper logic of the circuit with lesser area. Fig.6. Sleepy keeper Approach based 2 input NAND gate
- 13. PROPOSED LECTOR TECHNIQUE Fig. 6. Proposed technique Sleepy Lector with high Vth transistors
- 14. In LECTOR technique two leakage control transistors (one p-type and one n-type) are introduced between pull-up and pull-down circuit within the logic gate for which the gate terminal of each leakage control transistor (LCT) is controlled by the source of the other. This arrangement ensures that one of the LCTs always operates in its near cut off region. The basic idea behind LECTOR approach is that “a state with more than one transistor OFF in a path from supply voltage to ground is far less leaky than a state with only one transistor OFF in any supply to ground path. In case of near cut off operation of transistors the resistance of transistor is as high as an OFF transistor’s resistance but the available resistance is sufficient to increase the supply voltage to ground path resistance and so to reduce the leakage power dissipation.
- 15. CONCLUSION Leakage reduction technique plays a key role in VLSI circuit design. Scaling down the appropriate parameter can reduce the leakage power. it can be concluded that there is a strong correlation between three performance parameters: leakage power, delay, power delay product. LECTOR method found more effective in both standby and active mode of operation. If propagation delay is taken as the performance metrics, then sleep transistor method is proved effective method in the standby mode. In active mode, sleepy stack based approach is suitable for faster circuit operation.