chapter 1 digital integrated circuits_Introduction

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© Digital Integrated Circuits2nd Introduction
Digital Integrated
Digital Integrated
Circuits
Circuits
A Design Perspective
A Design Perspective
Introduction
Introduction
Jan M. Rabaey
Anantha Chandrakasan
Borivoje Nikolic
July 30, 2002

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What is this book all about?
What is this book all about?
 Introduction to digital integrated circuits.
 CMOS devices and manufacturing technology.
CMOS inverters and gates. Propagation delay,
noise margins, and power dissipation. Sequential
circuits. Arithmetic, interconnect, and memories.
Programmable logic arrays. Design
methodologies.
 What will you learn?
 Understanding, designing, and optimizing digital
circuits with respect to different quality metrics:
cost, speed, power dissipation, and reliability

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Digital Integrated Circuits
Digital Integrated Circuits
 Introduction: Issues in digital design
 The CMOS inverter
 Combinational logic structures
 Sequential logic gates
 Design methodologies
 Interconnect: R, L and C
 Timing
 Arithmetic building blocks
 Memories and array structures

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Introduction
Introduction
 Why is designing
digital ICs different
today than it was
before?
 Will it change in
future?

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The First Computer
The First Computer
The Babbage
Difference Engine
(1832)
25,000 parts
cost: £17,470

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ENIAC - The first electronic computer (1946)
ENIAC - The first electronic computer (1946)

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The Transistor Revolution
The Transistor Revolution
First transistor
Bell Labs, 1948

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The First Integrated Circuits
The First Integrated Circuits
Bipolar logic
1960’s
ECL 3-input Gate
Motorola 1966

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Intel 4004 Micro-Processor
Intel 4004 Micro-Processor
1971
1000 transistors
1 MHz operation

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Intel Pentium (IV) microprocessor
Intel Pentium (IV) microprocessor

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Moore’s Law
Moore’s Law
In 1965, Gordon Moore noted that the
number of transistors on a chip doubled
every 18 to 24 months.
He made a prediction that
semiconductor technology will double its
effectiveness every 18 months

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Moore’s Law
Moore’s Law
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
LO
G
2
O
F
T
H
E
N
U
M
B
E
R
O
F
C
O
M
P
O
N
E
N
T
S
P
E
R
IN
T
E
G
R
AT
E
D
F
U
N
C
TIO
N
Electronics, April 19, 1965.

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Evolution in Complexity
Evolution in Complexity

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Transistor Counts
Transistor Counts
1,000,000
100,000
10,000
1,000
10
100
1
1975 1980 1985 1990 1995 2000 2005 2010
8086
80286
i386
i486
Pentium®
Pentium®
Pro
K
1 Billion
1 Billion
Transistors
Transistors
Source: Intel
Source: Intel
Projected
Projected
Pentium®
II
Pentium®
III
Courtesy, Intel

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Moore’s law in Microprocessors
Moore’s law in Microprocessors
4004
8008
8080
8085 8086
286
386
486
Pentium® proc
P6
0.001
0.01
0.1
1
10
100
1000
1970 1980 1990 2000 2010
Year
Transistors
(MT)
2X growth in 1.96 years!
Transistors on Lead Microprocessors double every 2 years
Courtesy, Intel

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Die Size Growth
Die Size Growth
4004
8008
8080
8085
8086
286
386
486Pentium ® proc
P6
1
10
100
1970 1980 1990 2000 2010
Year
Die
size
(mm)
~7% growth per year
~2X growth in 10 years
Die size grows by 14% to satisfy Moore’s Law
Courtesy, Intel

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Frequency
Frequency
P6
Pentium ® proc
486
386
286
8086
8085
8080
8008
4004
0.1
1
10
100
1000
10000
1970 1980 1990 2000 2010
Year
Frequency
(Mhz)
Lead Microprocessors frequency doubles every 2 years
Doubles every
2 years
Courtesy, Intel

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Power Dissipation
Power Dissipation
P6
Pentium ® proc
486
386
286
8086
8085
8080
8008
4004
0.1
1
10
100
1971 1974 1978 1985 1992 2000
Year
Power
(Watts)
Lead Microprocessors power continues to increase
Courtesy, Intel

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Power will be a major problem
Power will be a major problem
5KW
18KW
1.5KW
500W
4004
8008
8080
8085
8086
286
386
486
Pentium® proc
0.1
1
10
100
1000
10000
100000
1971 1974 1978 1985 1992 2000 2004 2008
Year
Power
(Watts)
Power delivery and dissipation will be prohibitive
Courtesy, Intel

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Power density
Power density
4004
8008
8080
8085
8086
286
386
486
Pentium® proc
P6
1
10
100
1000
10000
1970 1980 1990 2000 2010
Year
Power
Density
(W/cm2)
Hot Plate
Nuclear
Reactor
Rocket
Nozzle
Power density too high to keep junctions at low temp
Courtesy, Intel

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Not Only Microprocessors
Not Only Microprocessors
Digital Cellular Market
(Phones Shipped)
1996 1997 1998 1999 2000
Units 48M 86M 162M 260M 435M
Analog
Baseband
Digital Baseband
(DSP + MCU)
Power
Management
Small
Signal RF
Power
RF
(data from Texas Instruments)
(data from Texas Instruments)
Cell
Phone

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Challenges in Digital Design
Challenges in Digital Design
“Microscopic Problems”
• Ultra-high speed design
• Interconnect
• Noise, Crosstalk
• Reliability, Manufacturability
• Power Dissipation
• Clock distribution.
Everything Looks a Little Different
“Macroscopic Issues”
• Time-to-Market
• Millions of Gates
• High-Level Abstractions
• Reuse & IP: Portability
• Predictability
• etc.
…and There’s a Lot of Them!
 DSM  1/DSM
?

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Productivity Trends
Productivity Trends
1
10
100
1,000
10,000
100,000
1,000,000
10,000,000
2003
1981
1983
1985
1987
1989
1991
1993
1995
1997
1999
2001
2005
2007
2009
10
100
1,000
10,000
100,000
1,000,000
10,000,000
100,000,000
Logic Tr./Chip
Tr./Staff Month.
x
x
x
x
x
x
x
21%/Yr. compound
Productivity growth rate
x
58%/Yr. compounded
Complexity growth rate
10,000
1,000
100
10
1
0.1
0.01
0.001
Logic
Transistor
per
Chip
(M)
0.01
0.1
1
10
100
1,000
10,000
100,000
Productivity
(K)
Trans./Staff
-
Mo.
Source: Sematech
Complexity outpaces design productivity
Complexity
Courtesy, ITRS Roadmap

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Why Scaling?
Why Scaling?
 Technology shrinks by 0.7/generation
 With every generation can integrate 2x more
functions per chip; chip cost does not increase
significantly
 Cost of a function decreases by 2x
 But …
 How to design chips with more and more functions?
 Design engineering population does not double every
two years…
 Hence, a need for more efficient design methods
 Exploit different levels of abstraction

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Design Abstraction Levels
Design Abstraction Levels
n+
n+
S
G
D
+
DEVICE
CIRCUIT
GATE
MODULE
SYSTEM

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Design Metrics
Design Metrics
 How to evaluate performance of a
digital circuit (gate, block, …)?
 Cost
 Reliability
 Scalability
 Speed (delay, operating frequency)
 Power dissipation
 Energy to perform a function

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Cost of Integrated Circuits
Cost of Integrated Circuits
 NRE (non-recurrent engineering) costs
 design time and effort, mask generation
 one-time cost factor
 Recurrent costs
 silicon processing, packaging, test
 proportional to volume
 proportional to chip area

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NRE Cost is Increasing
NRE Cost is Increasing

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Die Cost
Die Cost
Single die
Wafer
From http://www.amd.com
Going up to 12” (30cm)

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Cost per Transistor
Cost per Transistor
0.0000001
0.0000001
0.000001
0.000001
0.00001
0.00001
0.0001
0.0001
0.001
0.001
0.01
0.01
0.1
0.1
1
1
1982
1982 1985
1985 1988
1988 1991
1991 1994
1994 1997
1997 2000
2000 2003
2003 2006
2006 2009
2009 2012
2012
cost:
cost:
¢-per-
¢-per-transistor
transistor
Fabrication capital cost per transistor (Moore’s law)

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Yield
Yield
%
100
per wafer
chips
of
number
Total
per wafer
chips
good
of
No.


Y
yield
Die
per wafer
Dies
cost
Wafer
cost
Die


 
area
die
2
diameter
wafer
area
die
diameter/2
wafer
per wafer
Dies
2








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Defects
Defects












area
die
area
unit
per
defects
1
yield
die
 is approximately 3
4
area)
(die
cost
die f


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Some Examples (1994)
Some Examples (1994)
Chip Metal
layers
Line
width
Wafer
cost
Def./
cm2
Area
mm2
Dies/
wafer
Yield Die
cost
386DX 2 0.90 $900 1.0 43 360 71% $4
486 DX2 3 0.80 $1200 1.0 81 181 54% $12
Power PC
601
4 0.80 $1700 1.3 121 115 28% $53
HP PA 7100 3 0.80 $1300 1.0 196 66 27% $73
DEC Alpha 3 0.70 $1500 1.2 234 53 19% $149
Super Sparc 3 0.70 $1700 1.6 256 48 13% $272
Pentium 3 0.80 $1500 1.5 296 40 9% $417

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Reliability―
Reliability―
Noise in Digital Integrated Circuits
Noise in Digital Integrated Circuits
i(t)
Inductive coupling Capacitive coupling Power and ground
noise
v(t) VDD

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DC Operation
DC Operation
Voltage Transfer Characteristic
Voltage Transfer Characteristic
V(x)
V(y)
V
OH
VOL
VM
V
OH
VOL
f
V(y)=V(x)
Switching Threshold
Nominal Voltage Levels
VOH = f(VOL)
VOL = f(VOH)
VM = f(VM)

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Mapping between analog and digital signals
Mapping between analog and digital signals
V
IL
V
IH
V
in
Slope = -1
Slope = -1
V
OL
V
OH
V
out
“ 0” V
OL
V
IL
V
IH
V
OH
Undefined
Region
“ 1”

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Definition of Noise Margins
Definition of Noise Margins
Noise margin high
Noise margin low
V
IH
V
IL
Undefined
Region
"1"
"0"
V
OH
V
OL
NMH
NML
Gate Output Gate Input

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Noise Budget
Noise Budget
 Allocates gross noise margin to
expected sources of noise
 Sources: supply noise, cross talk,
interference, offset
 Differentiate between fixed and
proportional noise sources

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Key Reliability Properties
Key Reliability Properties
 Absolute noise margin values are deceptive
 a floating node is more easily disturbed than a
node driven by a low impedance (in terms of
voltage)
 Noise immunity is the more important metric –
the capability to suppress noise sources
 Key metrics: Noise transfer functions, Output
impedance of the driver and input impedance of the
receiver;

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Regenerative Property
v0
v1
v3
finv(v)
f(v)
v3
out
v
Regenerative Non-Regenerative
v2
v1
f(v)
finv(v)
v3
out
v

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A chain of inverters
v0 v1 v2 v3 v4 v5 v6
2
V
(Volt)
4
v0
v1
v2
t (nsec)
0
2 1
1
3
5
6 8 10
Simulated response

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Fan-in and Fan-out
Fan-in and Fan-out
N
Fan-out N Fan-in M
M

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The Ideal Gate
The Ideal Gate
Ri = 
Ro = 0
Fanout = 
NMH = NML = VDD/2
g = 
V in
V out

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An Old-time Inverter
An Old-time Inverter
NM H
Vin (V)
NM L
VM
0.0
1.0
2.0
3.0
4.0
5.0
1.0 2.0 3.0 4.0 5.0

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Delay Definitions
Delay Definitions
V out
tf
tpHL tpLH
tr
t
V in
t
90%
10%
50%
50%

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Ring Oscillator
Ring Oscillator
v0 v1 v5
v1 v2
v0 v3 v4 v5
T = 2 tp
N

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A First-Order RC Network
vout
vin C
R
tp = ln (2)  = 0.69 RC
Important model – matches delay of inverter

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Power Dissipation
Power Dissipation
Instantaneous power:
p(t) = v(t)i(t) = Vsupplyi(t)
Peak power:
Ppeak = Vsupplyipeak
Average power:
 
 
 


T
t
t
T
t
t supply
supply
ave dt
t
i
T
V
dt
t
p
T
P )
(
1

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Energy and Energy-Delay
Energy and Energy-Delay
Power-Delay Product (PDP) =
E = Energy per operation = Pav  tp
Energy-Delay Product (EDP) =
quality metric of gate = E  tp

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Vdd
Vout
isupply
CL
E0->1 = CLVdd
2
PMOS
NETWORK
NMOS
A1
AN
NETWORK
E0 1
 P t
 dt
0
T
 Vdd isupply t
 dt
0
T
 Vdd CLdVout
0
Vdd
 CL Vdd
 2
= = = =
E
cap
P
cap
t
 dt
0
T
 V
out
i
cap
t
 dt
0
T
 C
L
V
out
dV
out
0
Vdd

1
2
--
-C
L
V
dd

2
= = = =
vout
vin CL
R

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Summary
Summary
 Digital integrated circuits have come a long
way and still have quite some potential left for
the coming decades
 Some interesting challenges ahead
 Getting a clear perspective on the challenges and
potential solutions is the purpose of this book
 Understanding the design metrics that govern
digital design is crucial
 Cost, reliability, speed, power and energy
dissipation

chapter 1 digital integrated circuits_Introduction

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