CMOS Digital Integrated Circuits - Ch 01_Introduction

1 © CMOS Digital Integrated Circuits – 3rd Edition
CMOS Digital Integrated Circuits
Chapter 1
Introduction
S.M. Kang and Y. Leblebici
Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.

Some History
Invention of the transistor (BJT) 1947
Shockley, Bardeen, Brattain – Bell Labs
Single-transistor integrated circuit 1958
Jack Kilby – Texas Instruments
Invention of CMOS logic gates 1963
Wanlass & Sah – Fairchild Semiconductor
First microprocessor (Intel 4004) 1970
2,300 MOS transistors, 740 kHz clock frequency
Very Large Scale Integration 1978
Chips with more than ~20,000 devices

More Recently
Ultra Large Scale Integration
System on Chip (SoC)
20 ~ 30 million transistors in 2002
The chip complexity has increased by a factor of 1000
since its first introduction, but the term VLSI remained
virtually universal to denote digital integrated systems
with high complexity.

As a result of the continuously increasing integration
density and decreasing unit costs, the semiconductor
industry has been one of the fastest growing sectors
in the worldwide economy.
Economic Impact

Large
Centralized
Expensive
Industry Trends
Small / Portable
Distributed
Inexpensive

More portable, wearable, and more powerful devices
for ubiquitous and pervasive computing…
Industry Trends
High performance
Low power dissipation
Wireless capability
etc…

Some Leading-Edge Examples

Some Leading-Edge Examples
IBM S/390 Microprocessor
0.13 µm CMOS process
7 layers Cu interconnect
47 million transistors
1 GHz clock
180 mm2

Evolution of Minimum Feature Size

Evolution of Minimum Feature Size
2002: 130 nm
2003: 90 nm
…
2010: 35 nm (?)

Moore’s Law

Evolution of Memory Capacity

YEAR 2002 2005 2008 2011 2014
TECHNOLOGY 130 nm 100 nm 70 nm 50 nm 35 nm
CHIP SIZE 400 mm
2
600 mm
2
750 mm
2
800 mm
2
900 mm
2
NUMBER OF
TRANSISTORS
(LOGIC)
400 M 1 Billion 3 Billion 6 Billion 16 Billion
DRAM
CAPACITY
2 Gbits 10 Gbits 25 Gbits 70 Gbits 200 Gbits
MAXIMUM
CLOCK
FREQUENCY
1.6 GHz 2.0 GHz 2.5 GHz 3.0 GHz 3.5 GHz
MINIMUM
SUPPLY
VOLTAGE
1.5 V 1.2 V 0.9 V 0.6 V 0.6 V
MAXIMUM
POWER
DISSIPATION
130 W 160 W 170 W 175 W 180 W
MAXIMUM
NUMBER OF
I/O PINS
2500 4000 4500 5500 6000
ITRS - International Technology Roadmap for
Semiconductors
Predictions of the worldwide semiconductor / IC
industry about its own future prospects...

YEAR 2002 2005 2008 2011 2014
CHIP SIZE 400 mm
2
600 mm
2
750 mm
2
800 mm
2
900 mm
2
NUMBER OF
TRANSISTORS
(LOGIC)
DRAM
CAPACITY
MAXIMUM
CLOCK
FREQUENCY
MINIMUM
SUPPLY
VOLTAGE
1.5 V 1.2 V 0.9 V 0.6 V 0.6 V
MAXIMUM
POWER
DISSIPATION
130 W 160 W 170 W 175 W 180 W
MAXIMUM
NUMBER OF
I/O PINS
2500 4000 4500 5500 6000
Shrinking Device Dimensions

YEAR 2002 2005 2008 2011 2014
CHIP SIZE 400 mm
2
600 mm
2
750 mm
2
800 mm
2
900 mm
2
NUMBER OF
TRANSISTORS
(LOGIC)
DRAM
CAPACITY 2 Gbits 10 Gbits 25 Gbits 70 Gbits 200 Gbits
MAXIMUM
CLOCK
FREQUENCY
MINIMUM
SUPPLY
VOLTAGE
1.5 V 1.2 V 0.9 V 0.6 V 0.6 V
MAXIMUM
POWER
DISSIPATION
130 W 160 W 170 W 175 W 180 W
MAXIMUM
NUMBER OF
I/O PINS
2500 4000 4500 5500 6000
Increasing Function Density

YEAR 2002 2005 2008 2011 2014
CHIP SIZE 400 mm
2
600 mm
2
750 mm
2
800 mm
2
900 mm
2
NUMBER OF
TRANSISTORS
(LOGIC)
DRAM
CAPACITY
MAXIMUM
CLOCK
FREQUENCY
MINIMUM
SUPPLY
VOLTAGE
1.5 V 1.2 V 0.9 V 0.6 V 0.6 V
MAXIMUM
POWER
DISSIPATION
130 W 160 W 170 W 175 W 180 W
MAXIMUM
NUMBER OF
I/O PINS
2500 4000 4500 5500 6000
Increasing Clock Frequency

YEAR 2002 2005 2008 2011 2014
CHIP SIZE 400 mm
2
600 mm
2
750 mm
2
800 mm
2
900 mm
2
NUMBER OF
TRANSISTORS
(LOGIC)
DRAM
CAPACITY
MAXIMUM
CLOCK
FREQUENCY
MINIMUM
SUPPLY
VOLTAGE
1.5 V 1.2 V 0.9 V 0.6 V 0.6 V
MAXIMUM
POWER
DISSIPATION
130 W 160 W 170 W 175 W 180 W
MAXIMUM
NUMBER OF
I/O PINS
2500 4000 4500 5500 6000
Decreasing Supply Voltage

5-layer cross-section of chip

System-on-Chip
Integrating all or most of the components of a hybrid
system on a single substrate (silicon or MCM), rather
than building a conventional printed circuit board.
1. More compact system realization
2. Higher speed / performance
• Better reliability
• Less expensive !

New Direction: System-on-Chip (SoC)
ASIC Core
Memory
Embedded
Processor
Core
Analog
Functions
Communication
Sensor
Interface

Products have a shorter life-cycle !

Better strategy

The Y-Chart
Notice: There is a
need for structured
design methodologies
to handle the high
level of complexity !

Simplified VLSI
Design Flow
Top-down
Bottom-up

Structured Design Principles
Hierarchy: “Divide and conquer” technique involves dividing a module into sub-
modules and then repeating this operation on the sub-modules until the
complexity of the smaller parts becomes manageable.
Regularity: The hierarchical decomposition of a large system should result in not only
simple, but also similar blocks, as much as possible. Regularity usually
reduces the number of different modules that need to be designed and
verified, at all levels of abstraction.
Modularity: The various functional blocks which make up the larger system must have
well-defined functions and interfaces.
Locality: Internal details remain at the local level. The concept of locality also
ensures that connections are mostly between neighboring modules,
avoiding long-distance connections as much as possible.

Hierarchy of a 4-bit Carry Ripple Adder

Hierarchy of a 16-bit Manchester Adder

Regularity
2-input MUX
DFF

VLSI Design Styles
FPGA

Full Custom Design
Following the partitioning, the
transistor level design of the
building block is generated
and simulated.
The example shows a 1-bit
full-adder schematic and its
SPICE simulation results.

Full Custom Design
The main objective of full custom design is to ensure fine-grained
regularity and modularity.

Full Custom Design
A carefully crafted
full custom block
can be placed both
along the X and Y
axis to form an
interconnected
two-dimensional
array.
Example:
Data-path cells

Full Custom SRAM Cell Design

Mapping the Design into Layout
Manual full-custom
design can be very
challenging and
time consuming,
especially if the
low level regularity
is not well defined !

VLSI Design Styles
FPGA

HDL-Based Design
1980’s
Hardware Description Languages (HDL) were conceived to
facilitate the information exchange between design
groups.
1990’s
The increasing computation power led to the introduction
of logic synthesizers that can translate the description in
HDL into a synthesized gate-level net-list of the design.
2000’s
Modern synthesis algorithms can optimize a digital design
and explore different alternatives to identify the design
that best meets the requirements.

HDL-Based Design
The design is
synthesized and
mapped into the
target technology.
The logic gates
have one-to-one
equivalents as
standard cells
in the target
technology.

Standard Cells
AND DFF INV XOR

Standard Cells

Standard Cells
Rows of standard
cells with routing
channels between
them
Memory array

Standard Cells

VLSI Design Styles
FPGA

Mask Gate Array

Mask Gate Array
Before customization

VLSI Design Styles
FPGA

Field Programmable Gate Array

Internal structure of a CLB

CMOS Digital Integrated Circuits - Ch 01_Introduction

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