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This document introduces CMOS VLSI design and fabrication. It discusses how transistors are built on a silicon substrate using doping to create n-type and p-type semiconductors. MOS transistors act as electrically controlled switches that can be combined to build logic gates. The fabrication process is then overviewed, from depositing and patterning layers through lithography to form the transistor structures and connect them with metal wires. Design rules are also introduced to specify transistor dimensions and chip layout. The goal is to explain the basics of designing and fabricating simple CMOS integrated circuits.

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Lecture 0: Introduction
CMOS VLSI Design 4th Ed. 0: Introduction 2 Introduction  Integrated circuits: many transistors on one chip.  Very Large Scale Integration (VLSI): bucketloads!  Complementary Metal Oxide Semiconductor – Fast, cheap, low power transistors  Today: How to build your own simple CMOS chip – CMOS transistors – Building logic gates from transistors – Transistor layout and fabrication  Rest of the course: How to build a good CMOS chip
CMOS VLSI Design 4th Ed. 0: Introduction 3 Silicon Lattice  Transistors are built on a silicon substrate  Silicon is a Group IV material  Forms crystal lattice with bonds to four neighbors Si Si Si Si Si Si Si Si Si
CMOS VLSI Design 4th Ed. 0: Introduction 4 Dopants  Silicon is a semiconductor  Pure silicon has no free carriers and conducts poorly  Adding dopants increases the conductivity  Group V: extra electron (n-type)  Group III: missing electron, called hole (p-type) As Si Si Si Si Si Si Si Si B Si Si Si Si Si Si Si Si - + + -
CMOS VLSI Design 4th Ed. 0: Introduction 5 p-n Junctions  A junction between p-type and n-type semiconductor forms a diode.  Current flows only in one direction p-type n-type anode cathode
CMOS VLSI Design 4th Ed. 0: Introduction 6 nMOS Transistor  Four terminals: gate, source, drain, body  Gate – oxide – body stack looks like a capacitor – Gate and body are conductors – SiO2 (oxide) is a very good insulator – Called metal – oxide – semiconductor (MOS) capacitor – Even though gate is no longer made of metal* * Metal gates are returning today! n+ p Gate Source Drain bulk Si SiO2 Polysilicon n+ Body
CMOS VLSI Design 4th Ed. 0: Introduction 7 nMOS Operation  Body is usually tied to ground (0 V)  When the gate is at a low voltage: – P-type body is at low voltage – Source-body and drain-body diodes are OFF – No current flows, transistor is OFF n+ p Gate Source Drain bulk Si SiO2 Polysilicon n+ D 0 S
CMOS VLSI Design 4th Ed. 0: Introduction 8 nMOS Operation Cont.  When the gate is at a high voltage: – Positive charge on gate of MOS capacitor – Negative charge attracted to body – Inverts a channel under gate to n-type – Now current can flow through n-type silicon from source through channel to drain, transistor is ON n+ p Gate Source Drain bulk Si SiO2 Polysilicon n+ D 1 S
CMOS VLSI Design 4th Ed. 0: Introduction 9 pMOS Transistor  Similar, but doping and voltages reversed – Body tied to high voltage (VDD) – Gate low: transistor ON – Gate high: transistor OFF – Bubble indicates inverted behavior SiO2 n Gate Source Drain bulk Si Polysilicon p+ p+
CMOS VLSI Design 4th Ed. 0: Introduction 10 Power Supply Voltage  GND = 0 V  In 1980’s, VDD = 5V  VDD has decreased in modern processes – High VDD would damage modern tiny transistors – Lower VDD saves power  VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …
CMOS VLSI Design 4th Ed. 0: Introduction 11 Transistors as Switches  We can view MOS transistors as electrically controlled switches  Voltage at gate controls path from source to drain g s d g = 0 s d g = 1 s d g s d s d s d nMOS pMOS OFF ON ON OFF
CMOS VLSI Design 4th Ed. 0: Introduction 12 0 VDD A Y GND CMOS Inverter A Y 0 1 1 0 A Y OFF ON 1 ON OFF
CMOS VLSI Design 4th Ed. 0: Introduction 13 CMOS NAND Gate A B Y 0 0 1 0 1 1 1 0 1 1 1 0 OFF OFF ON ON 1 1 OFF ON OFF ON 0 1 ON OFF ON OFF 1 0 ON ON OFF OFF 0 0 A B Y
CMOS VLSI Design 4th Ed. 0: Introduction 14 CMOS NOR Gate A B Y 0 0 1 0 1 0 1 0 0 1 1 0 A B Y
CMOS VLSI Design 4th Ed. 0: Introduction 15 3-input NAND Gate  Y pulls low if ALL inputs are 1  Y pulls high if ANY input is 0 A B Y C
CMOS VLSI Design 4th Ed. 0: Introduction 16 CMOS Fabrication  CMOS transistors are fabricated on silicon wafer  Lithography process similar to printing press  On each step, different materials are deposited or etched  Easiest to understand by viewing both top and cross-section of wafer in a simplified manufacturing process
CMOS VLSI Design 4th Ed. 0: Introduction 17 Inverter Cross-section  Typically use p-type substrate for nMOS transistors  Requires n-well for body of pMOS transistors n+ p substrate p+ n well A Y GND VDD n+ p+ SiO2 n+ diffusion p+ diffusion polysilicon metal1 nMOS transistor pMOS transistor
CMOS VLSI Design 4th Ed. 0: Introduction 18 Well and Substrate Taps  Substrate must be tied to GND and n-well to VDD  Metal to lightly-doped semiconductor forms poor connection called Shottky Diode  Use heavily doped well and substrate contacts / taps n+ p substrate p+ n well A Y GND VDD n+ p+ substrate tap well tap n+ p+
CMOS VLSI Design 4th Ed. 0: Introduction 19 Inverter Mask Set  Transistors and wires are defined by masks  Cross-section taken along dashed line GND VDD Y A substrate tap well tap nMOS transistor pMOS transistor
CMOS VLSI Design 4th Ed. 0: Introduction 20 Detailed Mask Views  Six masks – n-well – Polysilicon – n+ diffusion – p+ diffusion – Contact – Metal Metal Polysilicon Contact n+ Diffusion p+ Diffusion n well
CMOS VLSI Design 4th Ed. 0: Introduction 21 Fabrication  Chips are built in huge factories called fabs  Contain clean rooms as large as football fields Courtesy of International Business Machines Corporation. Unauthorized use not permitted.
CMOS VLSI Design 4th Ed. 0: Introduction 22 Fabrication Steps  Start with blank wafer  Build inverter from the bottom up  First step will be to form the n-well – Cover wafer with protective layer of SiO2 (oxide) – Remove layer where n-well should be built – Implant or diffuse n dopants into exposed wafer – Strip off SiO2 p substrate
CMOS VLSI Design 4th Ed. 0: Introduction 23 Oxidation  Grow SiO2 on top of Si wafer – 900 – 1200 C with H2O or O2 in oxidation furnace p substrate SiO2
CMOS VLSI Design 4th Ed. 0: Introduction 24 Photoresist  Spin on photoresist – Photoresist is a light-sensitive organic polymer – Softens where exposed to light p substrate SiO2 Photoresist
CMOS VLSI Design 4th Ed. 0: Introduction 25 Lithography  Expose photoresist through n-well mask  Strip off exposed photoresist p substrate SiO2 Photoresist
CMOS VLSI Design 4th Ed. 0: Introduction 26 Etch  Etch oxide with hydrofluoric acid (HF) – Seeps through skin and eats bone; nasty stuff!!!  Only attacks oxide where resist has been exposed p substrate SiO2 Photoresist
CMOS VLSI Design 4th Ed. 0: Introduction 27 Strip Photoresist  Strip off remaining photoresist – Use mixture of acids called piranah etch  Necessary so resist doesn’t melt in next step p substrate SiO2
CMOS VLSI Design 4th Ed. 0: Introduction 28 n-well  n-well is formed with diffusion or ion implantation  Diffusion – Place wafer in furnace with arsenic gas – Heat until As atoms diffuse into exposed Si  Ion Implanatation – Blast wafer with beam of As ions – Ions blocked by SiO2, only enter exposed Si n well SiO2
CMOS VLSI Design 4th Ed. 0: Introduction 29 Strip Oxide  Strip off the remaining oxide using HF  Back to bare wafer with n-well  Subsequent steps involve similar series of steps p substrate n well
CMOS VLSI Design 4th Ed. 0: Introduction 30 Polysilicon  Deposit very thin layer of gate oxide – < 20 Å (6-7 atomic layers)  Chemical Vapor Deposition (CVD) of silicon layer – Place wafer in furnace with Silane gas (SiH4) – Forms many small crystals called polysilicon – Heavily doped to be good conductor Thin gate oxide Polysilicon p substrate n well
CMOS VLSI Design 4th Ed. 0: Introduction 31 Polysilicon Patterning  Use same lithography process to pattern polysilicon Polysilicon p substrate Thin gate oxide Polysilicon n well
CMOS VLSI Design 4th Ed. 0: Introduction 32 Self-Aligned Process  Use oxide and masking to expose where n+ dopants should be diffused or implanted  N-diffusion forms nMOS source, drain, and n-well contact p substrate n well
CMOS VLSI Design 4th Ed. 0: Introduction 33 N-diffusion  Pattern oxide and form n+ regions  Self-aligned process where gate blocks diffusion  Polysilicon is better than metal for self-aligned gates because it doesn’t melt during later processing p substrate n well n+ Diffusion
CMOS VLSI Design 4th Ed. 0: Introduction 34 N-diffusion cont.  Historically dopants were diffused  Usually ion implantation today  But regions are still called diffusion n well p substrate n+ n+ n+
CMOS VLSI Design 4th Ed. 0: Introduction 35 N-diffusion cont.  Strip off oxide to complete patterning step n well p substrate n+ n+ n+
CMOS VLSI Design 4th Ed. 0: Introduction 36 P-Diffusion  Similar set of steps form p+ diffusion regions for pMOS source and drain and substrate contact p+ Diffusion p substrate n well n+ n+ n+ p+ p+ p+
CMOS VLSI Design 4th Ed. 0: Introduction 37 Contacts  Now we need to wire together the devices  Cover chip with thick field oxide  Etch oxide where contact cuts are needed p substrate Thick field oxide n well n+ n+ n+ p+ p+ p+ Contact
CMOS VLSI Design 4th Ed. 0: Introduction 38 Metalization  Sputter on aluminum over whole wafer  Pattern to remove excess metal, leaving wires p substrate Metal Thick field oxide n well n+ n+ n+ p+ p+ p+ Metal
CMOS VLSI Design 4th Ed. 0: Introduction 39 Layout  Chips are specified with set of masks  Minimum dimensions of masks determine transistor size (and hence speed, cost, and power)  Feature size f = distance between source and drain – Set by minimum width of polysilicon  Feature size improves 30% every 3 years or so  Normalize for feature size when describing design rules  Express rules in terms of l = f/2 – E.g. l = 0.3 mm in 0.6 mm process
CMOS VLSI Design 4th Ed. 0: Introduction 40 Simplified Design Rules  Conservative rules to get you started
CMOS VLSI Design 4th Ed. 0: Introduction 41 Inverter Layout  Transistor dimensions specified as Width / Length – Minimum size is 4l / 2l, sometimes called 1 unit – In f = 0.6 mm process, this is 1.2 mm wide, 0.6 mm long
CMOS VLSI Design 4th Ed. 0: Introduction 42 Summary  MOS transistors are stacks of gate, oxide, silicon  Act as electrically controlled switches  Build logic gates out of switches  Draw masks to specify layout of transistors  Now you know everything necessary to start designing schematics and layout for a simple chip!
CMOS VLSI Design 4th Ed. 0: Introduction 43 About these Notes  Lecture notes © 2011 David Money Harris  These notes may be used and modified for educational and/or non-commercial purposes so long as the source is attributed.

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Lect 0 - intro.ppt

  • 2. CMOS VLSI Design 4th Ed. 0: Introduction 2 Introduction  Integrated circuits: many transistors on one chip.  Very Large Scale Integration (VLSI): bucketloads!  Complementary Metal Oxide Semiconductor – Fast, cheap, low power transistors  Today: How to build your own simple CMOS chip – CMOS transistors – Building logic gates from transistors – Transistor layout and fabrication  Rest of the course: How to build a good CMOS chip
  • 3. CMOS VLSI Design 4th Ed. 0: Introduction 3 Silicon Lattice  Transistors are built on a silicon substrate  Silicon is a Group IV material  Forms crystal lattice with bonds to four neighbors Si Si Si Si Si Si Si Si Si
  • 4. CMOS VLSI Design 4th Ed. 0: Introduction 4 Dopants  Silicon is a semiconductor  Pure silicon has no free carriers and conducts poorly  Adding dopants increases the conductivity  Group V: extra electron (n-type)  Group III: missing electron, called hole (p-type) As Si Si Si Si Si Si Si Si B Si Si Si Si Si Si Si Si - + + -
  • 5. CMOS VLSI Design 4th Ed. 0: Introduction 5 p-n Junctions  A junction between p-type and n-type semiconductor forms a diode.  Current flows only in one direction p-type n-type anode cathode
  • 6. CMOS VLSI Design 4th Ed. 0: Introduction 6 nMOS Transistor  Four terminals: gate, source, drain, body  Gate – oxide – body stack looks like a capacitor – Gate and body are conductors – SiO2 (oxide) is a very good insulator – Called metal – oxide – semiconductor (MOS) capacitor – Even though gate is no longer made of metal* * Metal gates are returning today! n+ p Gate Source Drain bulk Si SiO2 Polysilicon n+ Body
  • 7. CMOS VLSI Design 4th Ed. 0: Introduction 7 nMOS Operation  Body is usually tied to ground (0 V)  When the gate is at a low voltage: – P-type body is at low voltage – Source-body and drain-body diodes are OFF – No current flows, transistor is OFF n+ p Gate Source Drain bulk Si SiO2 Polysilicon n+ D 0 S
  • 8. CMOS VLSI Design 4th Ed. 0: Introduction 8 nMOS Operation Cont.  When the gate is at a high voltage: – Positive charge on gate of MOS capacitor – Negative charge attracted to body – Inverts a channel under gate to n-type – Now current can flow through n-type silicon from source through channel to drain, transistor is ON n+ p Gate Source Drain bulk Si SiO2 Polysilicon n+ D 1 S
  • 9. CMOS VLSI Design 4th Ed. 0: Introduction 9 pMOS Transistor  Similar, but doping and voltages reversed – Body tied to high voltage (VDD) – Gate low: transistor ON – Gate high: transistor OFF – Bubble indicates inverted behavior SiO2 n Gate Source Drain bulk Si Polysilicon p+ p+
  • 10. CMOS VLSI Design 4th Ed. 0: Introduction 10 Power Supply Voltage  GND = 0 V  In 1980’s, VDD = 5V  VDD has decreased in modern processes – High VDD would damage modern tiny transistors – Lower VDD saves power  VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …
  • 11. CMOS VLSI Design 4th Ed. 0: Introduction 11 Transistors as Switches  We can view MOS transistors as electrically controlled switches  Voltage at gate controls path from source to drain g s d g = 0 s d g = 1 s d g s d s d s d nMOS pMOS OFF ON ON OFF
  • 12. CMOS VLSI Design 4th Ed. 0: Introduction 12 0 VDD A Y GND CMOS Inverter A Y 0 1 1 0 A Y OFF ON 1 ON OFF
  • 13. CMOS VLSI Design 4th Ed. 0: Introduction 13 CMOS NAND Gate A B Y 0 0 1 0 1 1 1 0 1 1 1 0 OFF OFF ON ON 1 1 OFF ON OFF ON 0 1 ON OFF ON OFF 1 0 ON ON OFF OFF 0 0 A B Y
  • 14. CMOS VLSI Design 4th Ed. 0: Introduction 14 CMOS NOR Gate A B Y 0 0 1 0 1 0 1 0 0 1 1 0 A B Y
  • 15. CMOS VLSI Design 4th Ed. 0: Introduction 15 3-input NAND Gate  Y pulls low if ALL inputs are 1  Y pulls high if ANY input is 0 A B Y C
  • 16. CMOS VLSI Design 4th Ed. 0: Introduction 16 CMOS Fabrication  CMOS transistors are fabricated on silicon wafer  Lithography process similar to printing press  On each step, different materials are deposited or etched  Easiest to understand by viewing both top and cross-section of wafer in a simplified manufacturing process
  • 17. CMOS VLSI Design 4th Ed. 0: Introduction 17 Inverter Cross-section  Typically use p-type substrate for nMOS transistors  Requires n-well for body of pMOS transistors n+ p substrate p+ n well A Y GND VDD n+ p+ SiO2 n+ diffusion p+ diffusion polysilicon metal1 nMOS transistor pMOS transistor
  • 18. CMOS VLSI Design 4th Ed. 0: Introduction 18 Well and Substrate Taps  Substrate must be tied to GND and n-well to VDD  Metal to lightly-doped semiconductor forms poor connection called Shottky Diode  Use heavily doped well and substrate contacts / taps n+ p substrate p+ n well A Y GND VDD n+ p+ substrate tap well tap n+ p+
  • 19. CMOS VLSI Design 4th Ed. 0: Introduction 19 Inverter Mask Set  Transistors and wires are defined by masks  Cross-section taken along dashed line GND VDD Y A substrate tap well tap nMOS transistor pMOS transistor
  • 20. CMOS VLSI Design 4th Ed. 0: Introduction 20 Detailed Mask Views  Six masks – n-well – Polysilicon – n+ diffusion – p+ diffusion – Contact – Metal Metal Polysilicon Contact n+ Diffusion p+ Diffusion n well
  • 21. CMOS VLSI Design 4th Ed. 0: Introduction 21 Fabrication  Chips are built in huge factories called fabs  Contain clean rooms as large as football fields Courtesy of International Business Machines Corporation. Unauthorized use not permitted.
  • 22. CMOS VLSI Design 4th Ed. 0: Introduction 22 Fabrication Steps  Start with blank wafer  Build inverter from the bottom up  First step will be to form the n-well – Cover wafer with protective layer of SiO2 (oxide) – Remove layer where n-well should be built – Implant or diffuse n dopants into exposed wafer – Strip off SiO2 p substrate
  • 23. CMOS VLSI Design 4th Ed. 0: Introduction 23 Oxidation  Grow SiO2 on top of Si wafer – 900 – 1200 C with H2O or O2 in oxidation furnace p substrate SiO2
  • 24. CMOS VLSI Design 4th Ed. 0: Introduction 24 Photoresist  Spin on photoresist – Photoresist is a light-sensitive organic polymer – Softens where exposed to light p substrate SiO2 Photoresist
  • 25. CMOS VLSI Design 4th Ed. 0: Introduction 25 Lithography  Expose photoresist through n-well mask  Strip off exposed photoresist p substrate SiO2 Photoresist
  • 26. CMOS VLSI Design 4th Ed. 0: Introduction 26 Etch  Etch oxide with hydrofluoric acid (HF) – Seeps through skin and eats bone; nasty stuff!!!  Only attacks oxide where resist has been exposed p substrate SiO2 Photoresist
  • 27. CMOS VLSI Design 4th Ed. 0: Introduction 27 Strip Photoresist  Strip off remaining photoresist – Use mixture of acids called piranah etch  Necessary so resist doesn’t melt in next step p substrate SiO2
  • 28. CMOS VLSI Design 4th Ed. 0: Introduction 28 n-well  n-well is formed with diffusion or ion implantation  Diffusion – Place wafer in furnace with arsenic gas – Heat until As atoms diffuse into exposed Si  Ion Implanatation – Blast wafer with beam of As ions – Ions blocked by SiO2, only enter exposed Si n well SiO2
  • 29. CMOS VLSI Design 4th Ed. 0: Introduction 29 Strip Oxide  Strip off the remaining oxide using HF  Back to bare wafer with n-well  Subsequent steps involve similar series of steps p substrate n well
  • 30. CMOS VLSI Design 4th Ed. 0: Introduction 30 Polysilicon  Deposit very thin layer of gate oxide – < 20 Å (6-7 atomic layers)  Chemical Vapor Deposition (CVD) of silicon layer – Place wafer in furnace with Silane gas (SiH4) – Forms many small crystals called polysilicon – Heavily doped to be good conductor Thin gate oxide Polysilicon p substrate n well
  • 31. CMOS VLSI Design 4th Ed. 0: Introduction 31 Polysilicon Patterning  Use same lithography process to pattern polysilicon Polysilicon p substrate Thin gate oxide Polysilicon n well
  • 32. CMOS VLSI Design 4th Ed. 0: Introduction 32 Self-Aligned Process  Use oxide and masking to expose where n+ dopants should be diffused or implanted  N-diffusion forms nMOS source, drain, and n-well contact p substrate n well
  • 33. CMOS VLSI Design 4th Ed. 0: Introduction 33 N-diffusion  Pattern oxide and form n+ regions  Self-aligned process where gate blocks diffusion  Polysilicon is better than metal for self-aligned gates because it doesn’t melt during later processing p substrate n well n+ Diffusion
  • 34. CMOS VLSI Design 4th Ed. 0: Introduction 34 N-diffusion cont.  Historically dopants were diffused  Usually ion implantation today  But regions are still called diffusion n well p substrate n+ n+ n+
  • 35. CMOS VLSI Design 4th Ed. 0: Introduction 35 N-diffusion cont.  Strip off oxide to complete patterning step n well p substrate n+ n+ n+
  • 36. CMOS VLSI Design 4th Ed. 0: Introduction 36 P-Diffusion  Similar set of steps form p+ diffusion regions for pMOS source and drain and substrate contact p+ Diffusion p substrate n well n+ n+ n+ p+ p+ p+
  • 37. CMOS VLSI Design 4th Ed. 0: Introduction 37 Contacts  Now we need to wire together the devices  Cover chip with thick field oxide  Etch oxide where contact cuts are needed p substrate Thick field oxide n well n+ n+ n+ p+ p+ p+ Contact
  • 38. CMOS VLSI Design 4th Ed. 0: Introduction 38 Metalization  Sputter on aluminum over whole wafer  Pattern to remove excess metal, leaving wires p substrate Metal Thick field oxide n well n+ n+ n+ p+ p+ p+ Metal
  • 39. CMOS VLSI Design 4th Ed. 0: Introduction 39 Layout  Chips are specified with set of masks  Minimum dimensions of masks determine transistor size (and hence speed, cost, and power)  Feature size f = distance between source and drain – Set by minimum width of polysilicon  Feature size improves 30% every 3 years or so  Normalize for feature size when describing design rules  Express rules in terms of l = f/2 – E.g. l = 0.3 mm in 0.6 mm process
  • 40. CMOS VLSI Design 4th Ed. 0: Introduction 40 Simplified Design Rules  Conservative rules to get you started
  • 41. CMOS VLSI Design 4th Ed. 0: Introduction 41 Inverter Layout  Transistor dimensions specified as Width / Length – Minimum size is 4l / 2l, sometimes called 1 unit – In f = 0.6 mm process, this is 1.2 mm wide, 0.6 mm long
  • 42. CMOS VLSI Design 4th Ed. 0: Introduction 42 Summary  MOS transistors are stacks of gate, oxide, silicon  Act as electrically controlled switches  Build logic gates out of switches  Draw masks to specify layout of transistors  Now you know everything necessary to start designing schematics and layout for a simple chip!
  • 43. CMOS VLSI Design 4th Ed. 0: Introduction 43 About these Notes  Lecture notes © 2011 David Money Harris  These notes may be used and modified for educational and/or non-commercial purposes so long as the source is attributed.