CMOS_design.ppt
- 2. Outline Introduction Silicon, pn-junctions and transistors A Brief History Operation of MOS Transistors CMOS circuits Fabrication steps for CMOS circuits
- 3. Introduction Integrated circuits: many transistors on one chip. Very Large Scale Integration (VLSI) Complementary Metal Oxide Semiconductor (CMOS) Fast, cheap, “low-power” transistors circuits
- 4. WHY VLSI DESIGN? Money, technology, civilization
- 5. Annual Sales 1018 transistors manufactured in 2003 100 million for every human on the planet 0 50 100 150 200 1982 1984 1986 1988 1990 1992 1994 1996 1998 2000 2002 Year Global Semiconductor Billings (Billions of US$)
- 6. Digression: Silicon Semiconductors Modern electronic chips are built mostly on silicon substrates Silicon is a Group IV semiconducting material crystal lattice: covalent bonds hold each atom to four neighbors Si Si Si Si Si Si Si Si Si http://onlineheavytheory.net/silicon.html
- 7. Dopants Silicon is a semiconductor at room temperature Pure silicon has few free carriers and conducts poorly Adding dopants increases the conductivity drastically Dopant from Group V (e.g. As, P): extra electron (n- type) Dopant from Group III (e.g. B, Al): missing electron, called hole (p-type) As Si Si Si Si Si Si Si Si B Si Si Si Si Si Si Si Si - + + -
- 8. p-n Junctions First semiconductor (two terminal) devices A junction between p-type and n-type semiconductor forms a diode. Current flows only in one direction p-type n-type anode cathode
- 9. A Brief History Invention of the Transistor Vacuum tubes ruled in first half of 20th century Large, expensive, power-hungry, unreliable 1947: first point contact transistor (3 terminal devices) Shockley, Bardeen and Brattain at Bell Labs
- 10. A Brief History, contd.. 1958: First integrated circuit Flip-flop using two transistors Built by Jack Kilby (Nobel Laureate) at Texas Instruments Robert Noyce (Fairchild) is also considered as a co-inventor smithsonianchips.si.edu/ augarten/ Kilby’s IC
- 11. A Brief History, contd. First Planer IC built in 1961 2003 Intel Pentium 4 processor (55 million transistors) 512 Mbit DRAM (> 0.5 billion transistors) 53% compound annual growth rate over 45 years No other technology has grown so fast so long Driven by miniaturization of transistors Smaller is cheaper, faster, lower in power! Revolutionary effects on society
- 12. 1970’s processes usually had only nMOS transistors Inexpensive, but consume power while idle 1980s-present: CMOS processes for low idle power MOS Integrated Circuits Intel 1101 256-bit SRAM Intel 4004 4-bit Proc
- 13. Moore’s Law 1965: Gordon Moore plotted transistor on each chip Fit straight line on semilog scale Transistor counts have doubled every 26 months Year Transistors 4004 8008 8080 8086 80286 Intel386 Intel486 Pentium Pentium Pro Pentium II Pentium III Pentium 4 1,000 10,000 100,000 1,000,000 10,000,000 100,000,000 1,000,000,000 1970 1975 1980 1985 1990 1995 2000 Integration Levels SSI: 10 gates MSI: 1000 gates LSI: 10,000 gates VLSI: > 10k gates http://www.intel.com/technology/silicon/mooreslaw/
- 14. Corollaries Many other factors grow exponentially Ex: clock frequency, processor performance Year 1 10 100 1,000 10,000 1970 1975 1980 1985 1990 1995 2000 2005 4004 8008 8080 8086 80286 Intel386 Intel486 Pentium Pentium Pro/II/III Pentium 4 Clock Speed (MHz)
- 16. Ref: http://micro.magnet.fsu.edu/creatures/technical/sizematters.html • Modern transistors are few microns wide and approximately 0.1 micron or less in length • Human hair is 80-90 microns in diameter
- 17. Transistor Types Bipolar transistors npn or pnp silicon structure Small current into very thin base layer controls large currents between emitter and collector Base currents limit integration density Metal Oxide Semiconductor Field Effect Transistors nMOS and pMOS MOSFETS Voltage applied to insulated gate controls current between source and drain Low power allows very high integration First patent in the ’20s in USA and Germany Not widely used until the ’60s or ’70s
- 18. MOS Transistors Four terminal device: gate, source, drain, body Gate – oxide – body stack looks like a capacitor Gate and body are conductors (body is also called the substrate) SiO2 (oxide) is a “good” insulator (separates the gate from the body Called metal–oxide–semiconductor (MOS) capacitor, even though gate is mostly made of poly-crystalline silicon (polysilicon) n+ p Gate Source Drain bulk Si SiO2 Polysilicon n+ SiO2 n Gate Source Drain bulk Si Polysilicon p+ p+ NMOS PMOS
- 19. NMOS Operation Body is commonly tied to ground (0 V) Drain is at a higher voltage than Source When the gate is at a low voltage: P-type body is at low voltage Source-body and drain-body “diodes” are OFF No current flows, transistor is OFF n+ p Gate Source Drain bulk Si SiO2 Polysilicon n+ D 0 S
- 20. NMOS Operation Cont. When the gate is at a high voltage: Positive charge on gate of MOS capacitor Negative charge is attracted to body under the gate Inverts a channel under gate to “n-type” (N-channel, hence called the NMOS) if the gate voltage is above a threshold voltage (VT) Now current can flow through “n-type” silicon from source through channel to drain, transistor is ON n+ p Gate Source Drain bulk Si SiO2 Polysilicon n+ D 1 S
- 21. PMOS Transistor Similar, but doping and voltages reversed Body tied to high voltage (VDD) Drain is at a lower voltage than the Source Gate low: transistor ON Gate high: transistor OFF Bubble indicates inverted behavior SiO2 n Gate Source Drain bulk Si Polysilicon p+ p+
- 22. Power Supply Voltage GND = 0 V In 1980’s, VDD = 5V VDD has decreased in modern processes High VDD would damage modern tiny transistors Lower VDD saves power VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, Effective power supply voltage can be lower due to IR drop across the power grid.
- 23. Transistors as Switches In Digital circuits, MOS transistors are electrically controlled switches Voltage at gate controls path from source to drain g s d g = 0 s d g = 1 s d g s d s d s d nMOS pMOS OFF ON ON OFF
- 24. CMOS Inverter 1 0 Y A VDD A Y GND A Y
- 25. CMOS Inverter 0 1 0 Y A VDD A=1 Y=0 GND ON OFF A Y Y is pulled low by the turned on NMOS Device. Hence NMOS is the pull- down device.
- 26. CMOS Inverter 0 1 1 0 Y A VDD A=0 Y=1 GND OFF ON A Y Y is pulled high by the turned on PMOS Device. Hence PMOS is the pull-up device.
- 33. 3-input NAND Gate Y is pulled low if ALL inputs are 1 Y is pulled high if ANY input is 0 A B Y C
- 34. CMOS Fabrication CMOS transistors are fabricated on silicon wafer Wafers diameters (200-300 mm) Lithography process similar to printing press On each step, different materials are deposited, or patterned or etched Easiest to understand by viewing both top and cross-section of wafer in a simplified manufacturing process
- 35. Inverter Cross-section Typically use p-type substrate for nMOS transistors Requires to make an n-well for body of pMOS transistors n+ p substrate p+ n well A Y GND VDD n+ p+ SiO2 n+ diffusion p+ diffusion polysilicon metal1 nMOS transistor pMOS transistor
- 36. Well and Substrate Taps Substrate must be tied to GND and n-well to VDD Metal to lightly-doped semiconductor forms poor connection called Schottky Diode Use heavily doped well and substrate contacts/taps (or ties) n+ p substrate p+ n well A Y GND VDD n+ p+ substrate tap well tap n+ p+
- 37. Inverter Mask Set Top view Transistors and wires are defined by masks Cross-section taken along dashed line GND VDD Y A substrate tap well tap nMOS transistor pMOS transistor
- 38. Detailed Mask Views Six masks n-well Polysilicon n+ diffusion p+ diffusion Contact Metal Metal Polysilicon Contact n+ Diffusion p+ Diffusion n well In In reality >40 masks may be needed
- 39. Fabrication Steps Start with blank wafer (typically p-type where NMOS is created) Build inverter from the bottom up First step will be to form the n-well (where PMOS would reside) Cover wafer with protective layer of SiO2 (oxide) Remove oxide layer where n-well should be built Implant or diffuse n dopants into exposed wafer to form n-well Strip off SiO2 p substrate
- 40. Oxidation Grow SiO2 on top of Si wafer 900 – 1200 C with H2O or O2 in oxidation furnace p substrate SiO2
- 41. Photoresist Spin on photoresist Photoresist is a light-sensitive organic polymer Property changes where exposed to light Two types of photoresists (positive or negative) Positive resists can be removed if exposed to UV light Negative resists cannot be removed if exposed to UV light _ p substrate SiO2 Photoresist
- 42. Lithography Expose photoresist to Ultra-violate (UV) light through the n-well mask Strip off exposed photoresist with chemicals p substrate SiO2 Photoresist
- 43. Etch Etch oxide with hydrofluoric acid (HF) Seeps through skin and eats bone; nasty stuff!!! Only attacks oxide where resist has been exposed N-well pattern is transferred from the mask to silicon-di-oxide surface; creates an opening to the silicon surface p substrate SiO2 Photoresist
- 44. Strip Photoresist Strip off remaining photoresist Use mixture of acids called piranah etch Necessary so resist doesn’t melt in next step p substrate SiO2
- 45. n-well n-well is formed with diffusion or ion implantation Diffusion Place wafer in furnace with arsenic-rich gas Heat until As atoms diffuse into exposed Si Ion Implanatation Blast wafer with beam of As ions Ions blocked by SiO2, only enter exposed Si SiO2 shields (or masks) areas which remain p-type n well SiO2
- 46. Strip Oxide Strip off the remaining oxide using HF Back to bare wafer with n-well Subsequent steps involve similar series of steps p substrate n well
- 47. Polysilicon (self-aligned gate technology) Deposit very thin layer of gate oxide < 20 Å (6-7 atomic layers) Chemical Vapor Deposition (CVD) of silicon layer Place wafer in furnace with Silane gas (SiH4) Forms many small crystals called polysilicon Heavily doped to be good conductor Thin gate oxide Polysilicon p substrate n well
- 48. Polysilicon Patterning Use same lithography process discussed earlier to pattern polysilicon Polysilicon p substrate Thin gate oxide Polysilicon n well
- 49. Self-Aligned Process Use gate-oxide/polysilicon and masking to expose where n+ dopants should be diffused or implanted N-diffusion forms nMOS source, drain, and n- well contact p substrate n well
- 50. N-diffusion/implantation Pattern oxide and form n+ regions Self-aligned process where gate blocks n-dopants Polysilicon is better than metal for self-aligned gates because it doesn’t melt during later processing p substrate n well n+ Diffusion
- 51. N-diffusion/implantation cont. Historically dopants were diffused Usually high energy ion-implantation used today But n+ regions are still called diffusion n well p substrate n+ n+ n+
- 52. N-diffusion cont. Strip off oxide to complete patterning step n well p substrate n+ n+ n+
- 53. P-Diffusion/implantation Similar set of steps form p+ “diffusion” regions for PMOS source and drain and substrate contact p+ Diffusion p substrate n well n+ n+ n+ p+ p+ p+
- 54. Contacts Now we need to wire together the devices Cover chip with thick field oxide (FO) Etch oxide where contact cuts are needed p substrate Thick field oxide n well n+ n+ n+ p+ p+ p+ Contact
- 55. Metalization Sputter on aluminum over whole wafer Copper is used in newer technology Pattern to remove excess metal, leaving wires p substrate Metal Thick field oxide n well n+ n+ n+ p+ p+ p+ Metal
- 56. Physical Layout Chips are specified with set of masks Minimum dimensions of masks determine transistor size (and hence speed, cost, and power) Feature size f = distance between source and drain Set by minimum width of polysilicon Feature size improves 30% every 3 years or so Normalize for feature size when describing design rules Express rules in terms of = f/2 E.g. = 0.3 m in 0.6 m process
- 57. Simplified Design Rules Conservative rules to get you started
- 58. Inverter Layout Transistor dimensions specified as Width / Length Minimum size is 4-6/ 2sometimes called 1 unit In f = 0.25 m process, this is 0.5-0.75 m wide (W), 0.25 m long (L) Since =f/2=0.125m.
- 59. http://public.itrs.net/Files/2003ITRS/Home2003.htm The Future? International Technology Roadmap for Semiconductors
- 62. Summary MOS Transistors are stack of gate, oxide, silicon and p-n junctions Can be viewed as electrically controlled switches Build logic gates out of switches Draw masks to specify layout of transistors Now you know everything necessary to start designing schematics and layout for a simple chip!