![2 CMOS Time-Mode Circuits and Systems: Fundamentals and Applications
time quantizers, and time-mode arithmetic units. Section 1.5 briefly explores the
applications of time-based approaches in mixed-mode signal processing. These
applications include analog-to-digital converters, phase-locked loops, frequency
synthesizers, and temperature measurement. The detailed analysis of these
building blocks and applications will be provided in later chapters. The chapter
is summarized in Section 1.6.
1.1â•… WHAT IS TIME-MODE?
Time-mode circuits depict an analog signal using the difference between the time
instants at which two digital events take place. The amount of the time difference is
linearly proportional to the amplitude of the analog signal ideally. A time variable
is a pulse-width-modulated signal with its pulse width directly proportional to the
amplitude of the signal that it represents. A time variable possesses a unique duality
characteristic; specifically, it is an analog signal as the continuous amplitude of the
analog signal is represented by the duration of the pulse, but, it is also a digital signal
as it only has two largely distinct values. The duality of time variables enables them
to conduct analog signal processing in a digital environment. This unique character-
istic is clearly not possessed by neither analog nor digital variables.
Time-mode signal processing deals with addition, multiplication, amplifica-
tion, integration, quantization, etc., of time variables. It is interesting to note that
�
time-based signal processing is quite similar to information transmission through
the neuron systems of human brains [1]. Since information to be processed by time-
mode circuits is represented by the time difference of digital signals, these circuits
are essentially digital systems that perform analog and mixed analog–digital signal
processing without using power-greedy and speed-impaired digital signal processors.
1.2â•… WHY TIME-MODE?
The advancement of CMOS technology is always geared toward optimizing the
performance of digital systems. As a result, CMOS analog circuits are continu-
ously losing the benefits of specialized and process-controlled components critical
to the performance of these circuits. In addition, they must also cope with a rapidly
decreasing voltage headroom, that is, the difference between the given supply volt-
age of a circuit and the minimum supply voltage of the circuit required for MOS
transistors to operate in saturation, caused by the slow decline of the device thresh-
old voltage and the aggressive reduction of the supply voltage while meeting ever-
stringent performance specifications [2–4]. The shrinking voltage headroom not
only limits the maximum achievable signal-to-noise ratio (SNR), it also signifies
that the effect of the nonlinear characteristics of MOS devices subsequently reduces
the dynamic range of voltage-mode circuits. Further, technology scaling raises the
thermal noise floor quantified by kT/C where k is Boltzmann’s constant, T is tem-
perature in Kelvin, and C is the minimum capacitance. As a result, the accuracy of
voltage-mode circuits, loosely defined as the ratio of the minimum detectable volt-
age, typically set by the noise floor, to the maximum available voltage headroom,
scales poorly with technology.](https://image.slidesharecdn.com/2616755-250518113039-87896857/85/Cmos-Timemode-Circuits-And-Systems-Fundamentals-And-Applications-Fei-Yuan-32-320.jpg)
![3
Introduction to Time-Mode Signal Processing
Current-mode approaches where analog information to be processed is represented
by the branch current of electric networks offer an alternative means to cope with
the challenges induced by the dropping voltage headroom. These circuits achieve
a low nodal voltage swing by lowering the impedance of nodes. The existence of
low-impedance nodes throughout current-mode circuits, however, gives rise to large
branch currents. As a result, current-mode circuits typically consume more power as
compared with their voltage-mode counterparts. Lowering the power consumption
of current-mode circuits while meeting other design constraints at the same time is
rather difficult [5]. The characteristics of the low-impedance nodes of current-mode
circuits, on the other hand, offer an intrinsic advantage of a low time constant at
every node of the circuits. As a result, current-mode circuits are suitable for applica-
tions where speed rather than power consumption is most critical. These applications
include high-speed serial links, current-steering logic, and current-mode arithmetic
units such as current-mode adders in decision feedback equalization (DFE), to name
a few. Since voltages and currents are inherently related to each other via impedance
or conductance, the characteristics of voltage-mode circuits and current-mode cir-
cuits do not differ fundamentally. As a result, the performance of both circuits does
not scale well with technology.
Although the detrimental effect of technology scaling on the performance of ana-
log circuits, regardless of whether they are voltage-mode or current-mode, can be
compensated to some extent using digitally assisted means, such as digitally tuned
resistor arrays for the calibration of impedance matching of serial links, digitally
tuned capacitor arrays or current arrays for the cancellation of the offset voltage of
comparators, and digitally tuned capacitor arrays for the coarse frequency tuning of
oscillators; these approaches are costly both in terms of silicon and power consump-
tion as the switching transistors in these digital networks must be sufficiently large
in order to minimize the effect of the channel resistance of these switches. The addi-
tion of digitally assistance blocks also has a negative impact on the performance of
analog circuits such as increasing the capacitance of the critical nodes through which
high-frequency signals propagate. On top of that, the performance of voltage-mode
analog or mixed analog-digital circuits continues to decline with technology scaling,
further demanding for more digitally assisted compensation.
The intrinsic gate delay of digital circuits, on the other hand, has been the primary
beneficiary of technology scaling. The improved switching characteristics of MOS tran-
sistors offer an excellent timing accuracy such that the time resolution of digital circuits
has well surpassed the voltage resolution of analog circuits implemented in nanoscale
CMOS technologies. “In a deep-submicron CMOS process, the time-domain resolu-
tion of a digital signal edge transition is superior to the voltage resolution of an analog
signal” as stated by Dr. R. Staszewski [6]. Time-mode approaches where information
is represented by the difference between the time instants at which digital events take
place rather than the nodal voltages or branch currents of electric networks offer a new
means to neutralize the scaling-induced challenges that once seemed unconquerable.
Since time-mode circuits perform analog signal processing in the digital domain, not
only the performance of these circuits scales well with technology, time-mode circuits
also offer a number of attractive characteristics including full programmability, the ease
of portability, low-power consumption, and high-speed operation.](https://image.slidesharecdn.com/2616755-250518113039-87896857/85/Cmos-Timemode-Circuits-And-Systems-Fundamentals-And-Applications-Fei-Yuan-33-320.jpg)
![6 CMOS Time-Mode Circuits and Systems: Fundamentals and Applications
1.4.2â•…Time-to-Digital Converters
TDCs map a time variable to a digital code. The deployment of TDCs in nuclear sci-
ence research dates back to 1970s [7,8]. The application of TDCs has extended well
beyond nuclear science to digital storage oscillators [9,10], laser range finders [11],
and digital frequency synthesizers [12], to name a few. Similar to analog-to-digital
converters, the performance of TDCs is quantified by a number of parameters such
as SNR and signal-to-noise-plus-distortion ratio (SNDR) for noise-shaping TDCs,
and differential nonlinearity (DNL) and integral nonlinearity (INL) for sampling
TDCs. To compare the performance of TDCs of different architectures, the amount
of the power consumption per conversion step of TDCs is the most widely used
figure-of-merit (FOM).
1.4.3â•… Digital-to-Time Converters
The opposite of time-to-digital conversion is digital-to-time conversion. DTCs map a
digital code to a time variable. A digital-to-time operation is needed in applications
such as time-mode successive approximation TDCs. A DTC assumes a similar role
as that of a digital-to-analog converter in voltage-mode successive approximation
analog-to-digital converters (ADCs) or multibit ΔΣ modulators to establish negative
feedback.
1.4.4â•…Time Amplifiers
Similar to a voltage amplifier that amplifies a voltage, a time amplifier amplifies a
time variable. Time amplification is often needed in applications such as the precision
measurement of the width of a narrow pulse where the pulse width is often too small
to be quantized accurately. Time amplification can also be employed for accurately
quantizing the output of TDC-based phase detectors in the vicinity of the lock state so
as to establish a precision phase lock. Time amplifiers play a pivotal role in improving
the resolution of time-mode circuits. Similar to voltage amplifiers, the gain and lin-
earity of time amplifiers are the most important design specifications. For high-speed
time digitization, the bandwidth of time amplifiers is also of a great importance.
1.4.5â•…Time Quantizers
A single-bit voltage quantizer maps a voltage to a Boolean variable by comparing
it with a reference voltage. Similarly, a single-bit time quantizer maps a time vari-
able to a Boolean output by comparing it with a time reference. Time quantizers
can be realized using a time comparator with the time reference with which the
input compares coming from a voltage-controlled oscillator (VCO) of a constant
frequency. To conduct the multibit quantization of a time variable, the time variable
can be used as a gating signal to activate or deactivate a multistage ring oscillator
of a constant oscillation frequency, known as gated ring oscillator (GRO). Since
the number of the oscillation cycles of the oscillator and the output of each stage
of the oscillator uniquely correspond to the duration of the gating signal, a multibit](https://image.slidesharecdn.com/2616755-250518113039-87896857/85/Cmos-Timemode-Circuits-And-Systems-Fundamentals-And-Applications-Fei-Yuan-36-320.jpg)
![7
Introduction to Time-Mode Signal Processing
time quantizer can be constructed. GRO-based multibit time quantizers offer
the intrinsic advantage of first-order noise-shaping. In addition, as compared with
voltage-mode multibit quantization, which requires a total of 2N voltage compara-
tors where N is the number of quantization bits, VCO-based multibit time quanti-
zation offers the advantage of low-power consumption, fast quantization resulting
in a large oversampling ratio (OSR), good linearity, first-order noise-shaping, and
all-digital realization.
1.4.6â•…Time-Mode Arithmetic Units
Time-mode arithmetic units such as time adders and time integrators are critically
needed in time-based signal processing. The accumulation of a variable in the volt-
age domain can be realized by representing the variable as a current and integrating
the current onto a capacitor, that is,
v t
C
i d
c c
t
( ) ( )
=
ò
1
0
t t
The resultant voltage of the capacitor is the integration of the variable. Similarly, the
accumulation of a variable in the current domain can be implemented by representing
the variable as a voltage and integrating the resultant voltage onto an inductor, that is,
i t
L
v d
L L
t
( ) ( )
=
ò
1
0
t t
The resultant current of the inductor is the integration of the variable. Withholding a
time variable, on the other hand, is rather difficult due to the irretrievable nature of
time. Recent work by Hong et al. [13] and Kim et al. [14] has opened the door for time
registers and later time integrators, a key component of all-digital ΔΣ modulators.
1.5â•… APPLICATIONS OF TIME-MODE SIGNAL PROCESSING
In this section, we briefly browse through some of the key applications of time-based
signal processing. These applications include analog-to-digital converters, phase-
locked loops, frequency synthesizers, and temperature measurement. An in-depth
investigation of them will be given in later chapters.
1.5.1â•…Analog-to-Digital Converters
Driven by the benefits of time-mode signal processing, analog-to-digital conversion
using time-mode approaches has received a special attention from both academia
and industry recently. A key difference between conventional voltage-mode ADCs
and time-mode ADCs is the replacement of voltage comparator-based quantiz-
ers with VCO-based quantizers as the former suffer from a number of drawbacks
including high power consumption especially for multibit quantization and the need](https://image.slidesharecdn.com/2616755-250518113039-87896857/85/Cmos-Timemode-Circuits-And-Systems-Fundamentals-And-Applications-Fei-Yuan-37-320.jpg)
![9
Introduction to Time-Mode Signal Processing
One might argue that the same can be achieved by lowering the capacitance of the
loop filter. Lowering the capacitance of the loop filter, however, will degrade the
ability of the loop filter to filter out high-frequency components present on the con-
trol voltage line of the oscillator. It is therefore highly desirable from a low-power
consumption point of view to have the charge pump removed. The removal of the
charge pump also eliminates the source of reference spurs. As the output of the phase
detector is a pulse with its pulse width directly proportional to the phase difference
between the input of the phase-locked loop and the output of the VCO, this time
variable can be digitized by a TDC. The digital output of the TDC can then be fed
to a digital loop filter. As a result, not only power-greedy charge pump and silicon-
consuming loop filter are removed, the loop bandwidth can also be made fully pro-
grammable. The resultant phase-locked loop is now all-digital and enjoys the full
merits of technology scaling. If noise-shaping TDCs are used, the low quantization
noise of the TDCs will also improve the overall phase noise of the phase-locked loop.
1.5.3â•…All-Digital Frequency Synthesizers
Frequency synthesizers are one of the core subsystems of wireless systems. An all-
digital phase-locked loop can be migrated to an all-digital frequency synthesizer by
including a frequency divider in the feedback path. Integer-N frequency synthesizers
suffer from a large frequency adjustment step dictated by the reference frequency,
while fractional-N frequency synthesizers yield a fine frequency resolution but suffer
from fractional spurs [15,16]. Randomizing the control bits of the frequency divider
widens the output of the frequency divider so that fractional spurs are reduced. This,
however, is at the expense of increased in-band noise [17]. To reduce the in-band
noise, a noise-shaping ΔΣ modulator with a DC input can be employed to generate
the random bits for selecting the modulus of the frequency divider [18]. The noise-
shaping characteristics of the ΔΣ modulator ensure a low level of in-band quantiza-
tion noise is achieved by moving the excessive quantization noise to high frequencies
outside the signal band, which can be removed effectively by the loop dynamics
[19,20]. The recent architecture of all-digital frequency synthesizers places a TDC
in the feedback path [6,21]. The TDC performs frequency division. The removal of
an explicit frequency divider in the feedback path and its associated performance
enhancement blocks such as ΔΣ modulators not only greatly simplifies synthesizers,
it also eliminates the source of fractional spurs [20,22,23].
1.5.4â•…Time-Based Temperature Sensors
Integrated temperature sensors are very important in applications such as medical
implants, smart sensors for environment monitoring, and on-chip temperature moni-
toring of VLSI (very-large-scale integration) systems, to name a few. Traditionally,
integrated temperature sensors are manufactured using a temperature-dependent
voltage-mode circuit whose output voltage is a linear function of temperature, a
temperature reference circuit whose output voltage is independent of temperature
and whose temperature set point can be adjusted, and a voltage comparator that
compares the output voltage of the temperature-dependent circuit and that of the](https://image.slidesharecdn.com/2616755-250518113039-87896857/85/Cmos-Timemode-Circuits-And-Systems-Fundamentals-And-Applications-Fei-Yuan-39-320.jpg)
![10 CMOS Time-Mode Circuits and Systems: Fundamentals and Applications
temperature reference circuit. The continuous dip in supply voltage greatly reduces
the resolution of voltage-mode circuits, making it very difficult to improve the mea-
surement accuracy of these temperature sensors.
Temperature can be measured by comparing the frequency of a PTAT (propor-
tional to absolute temperature) oscillator whose frequency is proportional to tempera-
ture with that of a reference oscillator whose frequency is independent of temperature
[24–26]. Alternatively, one can first convert temperature to a pulse with pulse width
proportional to temperature and then digitize the width of the resultant pulse using a
low-power TDC such as a pulse-shrinking TDC. The removal of oscillators greatly
lowers the power consumption, making TDC-based temperature sensors particularly
attractive in low-power-requiring applications [12,27]. A time-mode integrated tem-
perature sensor can also be realized using a temperature-dependent delay line whose
delay is a linear function of temperature, a temperature reference line whose delay
is independent of temperature and can be adjusted by changing its temperature set-
point, and a time comparator that discriminates the delay of the two delay lines. For
a given temperature, the delay of the temperature reference can be made identical to
that of the temperature-dependent delay line by digitally adjusting the delay of the
temperature reference, that is, the temperature set point of the temperature reference
line. Once this occurs, the digital code for adjusting the temperature set point of the
temperature reference line gives the digital representation of the temperature [28,29].
1.6â•…SUMMARY
In this chapter, we briefly examined technology scaling-induced challenges encoun-
tered in design of voltage-mode or current-mode circuits for mixed-mode signal
processing. We showed that although technology scaling results in a reduced volt-
age accuracy, which leads to the deteriorating performance of both voltage-mode
and current-mode circuits, it sharply improves the switching accuracy of digital
circuits at the same time. As a result, the performance of time-based signal process-
ing not only scales well with technology, it also surpasses that of voltage-mode or
current-mode circuits. The challenges encountered in design of time-mode circuits
such as device mismatches, PVT effect, and the storage of time-mode variables
were explored. The key building blocks of time-mode circuits including VTCs,
TDCs, DTCs, time amplifiers, time quantizers, and time-mode arithmetic units
were examined briefly. The applications of time-mode circuits in analog-to-digital
converters, phase-locked loops, frequency synthesizers, and temperature measure-
ment were briefly explored.
REFERENCES
)>> 1.)>>V. Ravinuthula, V. Garg, J. Harris, and J. Fortes. Time-mode circuits for analog com-
putation. International Journal of Circuit Theory and Applications, 37:631–659, 2009.
)>> 2.)>>G. Shahidi. Challenges of CMOS scaling at below 0.1 μm. In Proceedings of
International Microelectronics Conference, 2000, Tehran, pp. 5–8.
)>> 3.)>> R. Gera and D. Hoe. An evaluation of CMOS adders in deep sub-micron processes. In
Proceedings of Southeastern Symposium on System Theory, 2012, Jacksonville, FL,
pp. 126–129.](https://image.slidesharecdn.com/2616755-250518113039-87896857/85/Cmos-Timemode-Circuits-And-Systems-Fundamentals-And-Applications-Fei-Yuan-40-320.jpg)
![13
2 Voltage-to-Time
Converters
Fei Yuan
One of the key building blocks of time-mode systems for processing analog signals
is voltage-to-time converters (VTCs) that map a voltage to a time variable with its
value directly proportional to the amplitude of the voltage. Although VTCs can be
realized using complex circuits to achieve good performance such as a large conver-
sion range and a good linearity, operational amplifiers whose performance scales
poorly with technology are often required [1–3]. As time-mode circuits are digi-
tal circuits, the linearity of a time-mode system that processes analog quantities is
largely dominated by that of its VTC. VTCs whose performance scales well with
technology are critical to time-based signal processing.
This chapter deals with VTCs with an emphasis on the techniques that improve
the linearity of the converters. The chapter is organized as follows: Section 2.1 inves-
tigates VTCs implemented using the voltage-controlled delay units (VCDUs). VTCs
using VCDUs and source degeneration are discussed in Section 2.2. Section 2.3
looks into relaxation voltage-to-time converters. Reference VTCs are examined in
Section 2.4. The applications of VTCs in time-mode comparators are investigated in
Section 2.5. The chapter is summarized in Section 2.6.
2.1â•… VCDU VOLTAGE-TO-TIME CONVERTERS
A voltage can be mapped to a time variable using the VCDU shown in Figure 2.1
[4–11]. The VCDU consists of a current-starved inverter, that is, a static inverter
with its charging or discharging current controlled by a current source, a load
capacitor, and a static inverter. The load capacitor should be linear and its capaci-
tance should be much larger as compared with the capacitances of the transistors
such that the effect of the nonlinearity of the device capacitances is negligible as
CONTENTS
2.1)>> VCDU Voltage-to-Time Converters................................................................13
2.2)>> VCDU Voltage-to-Time Converters with Source Degeneration......................19
2.3)>> Relaxation Voltage-to-Time Converters..........................................................21
2.4)>> Reference Voltage-to-Time Converters...........................................................23
2.5)>> Time-Mode Comparators................................................................................24
2.6)>>Summary.........................................................................................................30
References.................................................................................................................30](https://image.slidesharecdn.com/2616755-250518113039-87896857/85/Cmos-Timemode-Circuits-And-Systems-Fundamentals-And-Applications-Fei-Yuan-43-320.jpg)
![14 CMOS Time-Mode Circuits and Systems: Fundamentals and Applications
compared with that of the load capacitor. The current-starved inverter is clocked
by a periodic signal ϕ that presets the VCDU prior to a conversion operation. In
the precharge phase where ϕ is low, the load capacitor is precharged to VDD and
the output of the static inverter is set to logic-0. The input voltage vin is sampled
by Cin. In the following discharge phase where ϕ = 1, the load capacitor is dis-
charged by the current of M3 whose value is set by the input voltage vin(kT) at the
end of the precharge phase.
The voltage of the gate of M3 is kept unchanged during the discharge phase
and so is the discharge current of the load capacitor. As a result, the voltage of
the capacitor C decreases linearly with time. When vc drops below the threshold
voltage VT,inv of the following static inverter, vo will be set to logic-1. The value of
the resultant time variable Tin, which is measured from the time instant at which
ϕ = 1 to the time instant at which vc is submerged by the threshold voltage of the
inverter, is given by
T kT
C
i kT
V V
in
DS
DD T inv
( )
( )
,
,
= -
( )
3
(2.1)
where
VDD is the supply voltage
iDS3(kT) is the channel current of M3 in kth period and is given by
i kT k v kT V v
DS n in T DS
3 3
2
3
1
( ) ( ) ,
= -
é
ë ù
û +
( )
l (2.2)
M1
M2
M3
vin
vc vo
vc
vo
VDD
VT,inv
vG3
kT
vin(kT)
M4
C
Precharge
Sampling
(k+1)T
vin[(k+1)T]
Tin(kT+T)
Tin(kT)
t
t
t
t
Cin
FIGURE 2.1â•… Voltage-to-time converter using voltage-controlled delay cells.](https://image.slidesharecdn.com/2616755-250518113039-87896857/85/Cmos-Timemode-Circuits-And-Systems-Fundamentals-And-Applications-Fei-Yuan-44-320.jpg)
![15
Voltage-to-Time Converters
where
k C
W
L
n n ox
3
3
1
2
=
æ
è
ç
ö
ø
÷
m , (2.3)
where
μn is the surface mobility of free electrons
Cox is gate-oxide capacitance per unit area
W3 and L3 are the width and length of M3, respectively
VT is the threshold voltage of MOSFETs
λ is the channel-length modulator constant
vDS3 is the drain-source voltage of M3
For simplicity, we assume that NMOS and PMOS transistors have the same thresh-
old voltage, that is, VTn = |VTp| = VT. Substituting Equation 2.2 into Equation 2.1 yields
T kT
C V V
k v kT V v
in
DD T inv
n in T DS
( )
( )
( )
.
,
=
-
-
é
ë ù
û +
( )
3
2
3
1 l
(2.4)
It is observed from Equation 2.4 that for each vin(kT), there is a corresponding
Tin(kT). The need for the sample-and-hold operation of vin becomes apparent. Also it is
observed from Equation 2.4 that the relation between Tin and vin is inherently nonlinear.
Further, not only is Tin set by vin, Tin also varies with vc as vc = vDS2 + vDS3 ≈ vDS3, further
signifying the effect of the nonlinearity of the transconductance. Figure 2.2a shows
the dependence of Tin on the input voltage of Figure 2.1. The nonlinear characteristic
observed in the figure is consistent with our findings in the investigation of the nonlin-
ear relation between Tin and vin. As can be seen, an excessive amount of delay exists
when the input voltage is low. Also, linearity improves when the input voltage is large.
To improve the performance, an additional transistor M4 can be added in paral-
lel with M3, as shown in Figure 2.1 [12–14]. To understand the effect of M4, let us
examine its mode of operation. To ensure that M4 is in triode, vDS4 < vGS4 − VT is
required. This translates to vc < VDD − VT. In the precharge phase where ϕ = 0, we
have vc = VDD. In the discharge phase where ϕ = 1, the load capacitor is discharged
through M3 with part of the discharge current controlled by the input and the other
part set by M4. If VDD − VT < vc, M4 will be in saturation. It will be in triode if
vc < VDD − VTâ•›. We use the typical parameters of a 130 nm CMOS technology as an
example to exemplify the region of the operation of M4. Since for a typical 130 nm
CMOS technology, VDD = 1.2 V and VT ≈ 0.4 V, M4 will be in saturation if vc < 0.8 V
and in triode if vc < 0.8 V. It is evident from Equation 2.1 that since the discharge
current of the load capacitor consists of both the channel current of M3, which is set
by vin, and the channel current of M4, which is independent of vin, we have
T kT
C
i kT i kT
V V
in
DS DS
DD T inv
( )
( ) ( )
.
,
=
+
-
( )
3 4
(2.5)](https://image.slidesharecdn.com/2616755-250518113039-87896857/85/Cmos-Timemode-Circuits-And-Systems-Fundamentals-And-Applications-Fei-Yuan-45-320.jpg)
![16 CMOS Time-Mode Circuits and Systems: Fundamentals and Applications
It is seen from Equation 2.5 that when iDS3(kT) ≪ iDS4(kT),
T kT
C
i
V V
in
DS kT
DD T inv
( ) .
( )
,
» -
( )
4
(2.6)
Also, when iDS3(kT) ≫ iDS4(kT),
T kT
C
i kT
V V
in
DS
DD T inv
( )
( )
.
,
» -
( )
3
(2.7)
Since hyperbolic function f(x) = 1/x exhibits a good linearity if x ≪ 1 or x ≫ 1 and a
poor linearity in the neighborhood of x = 1, the addition of M4 improves the linearity
of Tin when iDS3 is small. When iDS3 is large, a better linearity is also obtained. This
is evident in Figure 2.2b where the dependence of the time delay on the input voltage
of Figure 2.1 with M4 added is shown. When iDS3 is small, Tin is dominated by iDS4,
the dependence of Tin on iDS3 is reduced, so is the conversion gain. The larger iDS4, the
worse is the loss of the conversion gain.
To further improve the linearity, a differentially configured VTC consisting of
two identical single-ended VTCs of Figure 2.1 can be used, as shown in Figure 2.3
[15]. To demonstrate the improvement of linearity, we neglect the effect of channel
length modulation and assume a perfect match between the two transconductors
40
30
20
10
0.45 0.5 0.55
Vin (V)
(a)
(b)
0.6 0.65 0.7
0.3
Delay
(ns)
0.35 0.4
Delay
(ns)
0.45 0.5 0.55
Vin (V)
0.6 0.65 0.7
0.3
7
8
12
11
10
9
0.35 0.4
FIGURE 2.2â•… Dependence of the delay of VCDU of Figure 2.1 implemented in an 130 nm
CMOS technology. (a) Without M4. (b) With M4.](https://image.slidesharecdn.com/2616755-250518113039-87896857/85/Cmos-Timemode-Circuits-And-Systems-Fundamentals-And-Applications-Fei-Yuan-46-320.jpg)
![17
Voltage-to-Time Converters
forming the differential configuration. Let v V v
in in
+
= + D and v V v
in in
-
= - D where Δv
denotes the variation of vin from its nominal value Vin. From Equation 2.4, we have
D
D
T kT T kT T kT
C V V
k
v v kT V
in in in
DD T inv
n
in
( ) ( ) ( )
( ) ( ) ( )
,
= -
= -
- -
+ -
3
4 T
T
in T
v kT V v
[ ]
[ ]
- -
{ }
( ) ( )
.
2 2
2
D
(2.8)
If (Δv)2 is negligibly small as compared with [Vin(kT) − VT]2, we have
D D
T kT
C V V
k v kT V
v
in
DD T inv
n in T
( )
( )
( )
.
,
» -
-
-
é
ë ù
û
ì
í
ï
î
ï
ü
ý
ï
þ
ï
4
3
3
(2.9)
It is seen from Equation 2.9 that as long as Δv ≪ Vin − VT, a linear relation between
ΔTin and Δv will exist. It should be emphasized that the relation between Tin and
vin given by Equation 2.4 is nonlinear, while that between ΔTin and Δv given by
Equation 2.9 is linear.
Another approach to improve the linearity is to use the symmetrical load pro-
posed by Maneatis in [16], as shown in Figure 2.4a [17]. Although voltage-to-cur-
rent conversion is solely carried out by M3, the addition of diode-connected M4
improves the linearity of ic ~ vc relation, as illustrated graphically in Figure 2.4c. It
should be noted that since the discharge current should be solely set by the input,
vo
+ vc
+
vc
–
vo
–
v–
in
v+
in
vin
vo
VDD
VT,inv
kT (k+1)T
v+
in[(k+1)T]
t
v+
in(kT)
v–
in(kT)
v–
c
v+
c
v–
in[(k+1)T]
T–
in(kT)
ΔTin(kT)
T+
in(kT)
ΔTin(kT +T)
FIGURE 2.3â•… Voltage-to-time converter using differential voltage-controlled delay cells.
(From Macpherson, A. et al., A 5 GS/s 4-bit time-based single-channel CMOS ADC for
radio astronomy, Proceedings of IEEE Custom Integrated Circuit Conference, 2013, pp. 1–4.)](https://image.slidesharecdn.com/2616755-250518113039-87896857/85/Cmos-Timemode-Circuits-And-Systems-Fundamentals-And-Applications-Fei-Yuan-47-320.jpg)
![18 CMOS Time-Mode Circuits and Systems: Fundamentals and Applications
the dependence of ic on vc introduces unwanted distortion. Konishi et al. pointed out
that the voltage of the drain of M3 and M4 in Figure 2.4a cannot be fully recovered
to the supply voltage when ϕ = 0, resulting in the variation of the propagation delay
[18]. This is because when ϕ = 1, although C is fully charged, the charge sharing
between C and the parasitic capacitor at the drain of M3 and M4 will result in a dip
of vc immediately after ϕ becomes logic-1. To demonstrate this, let the capacitance
at the drains of M3 and M4 be CA. Further let the voltage of C and CA be vC(0−) =
VDD and vA(0−), respectively, when ϕ = 0. If we neglect the channel resistance of all
transistors when they are in triode, then immediately after ϕ = 1, C and CA will have
the same voltage, that is, vC(0+) = vA(0+) = v(0+). Using charge conservation, we have
C C v CV C v
A DD A A
+ = +
( ) ( ) ( )
+ -
0 0 , (2.10)
from which we obtain
v
CV C v
C C
DD A A
A
( )
( )
.
0
0
+
-
=
+
+
(2.11)
M1
M2
vc vo
vin
ic
C
CA
M3 M4
(a)
M2 M3
vc
vin
vo
M1
C
(b)
ic
ic
vin
vc
iDS4
iDS3
(c)
FIGURE 2.4â•… (a) Voltage-to-time converter. (From Taillefer, C. and Roberts, G., IEEE
Trans. Circuits Syst. I, 56(9), 1908, 2009.) (b) Voltage-to-time converter. (From Konishi, T.
et al., A 40-nm 640-μm2 45-dB opampless all-digital second-order MASH ΔΣ ADC, in
Proceedings of IEEE International Symposium on Circuits and Systems, 2011, pp. 518–521.)](https://image.slidesharecdn.com/2616755-250518113039-87896857/85/Cmos-Timemode-Circuits-And-Systems-Fundamentals-And-Applications-Fei-Yuan-48-320.jpg)
![19
Voltage-to-Time Converters
The instantaneous change of vc immediately after ϕ = 1 is evident in Equation 2.11.
Equation 2.11 also reveals that if C ≫ CA, then the effect of charge sharing will be
negligible. The modified VTC shown in Figure 2.4b eliminates this drawback.
2.2â•…
VCDU VOLTAGE-TO-TIME CONVERTERS
WITH SOURCE DEGENERATION
It is well understood that negative feedback improves linearity [19]. To improve
the linearity of the preceding VCDU, negative feedback formed by the source
degeneration shown in Figure 2.5a can be used [20]. Source degeneration is an
effective and economical means to improve the linearity of MOS transconductors
and is widely used in a broad range of applications such as radio-frequency down-
conversion mixers for linearity improvement. The mechanism of source degen-
eration on improving the linearity of the MOSFET transconductor can be briefly
depicted as follows: When vin rises, vGS3 will rise accordingly. The increase of vGS3
will signify the nonlinear effect of vGS3 ~ iDS3 relation as MOSFETs are inherently
nonlinear transconductors and will exhibit a good linearity only when vGS is small.
To demonstrate this, we neglect the effect of channel length modulation and let
vGS = VGS + vgs where VGS and vgs are the dc and ac components of vGS, respectively.
Notice that
)
i k V v V
I g v k v
DS n GS gs T
DS m gs n gs
3 3 3 3
2
3 3 3 3 3
2
= + -
( )
= + + ,
)
(2.12)
M1
M2
M3
Rs
(a)
vs
vin
C
vc vo
(b)
M1
M2
M3
M4 Rs Cs
vin
C
vc vo
FIGURE 2.5â•… Voltage-to-time converter using voltage-controlled delay cells with source
degeneration. (a) Without residual charge removal. (From Belloni, M. et al., A voltage-to-
pulse converter for very high frequency DC-DC converters, Proceedings of International
Symposium on Power Electronics, Electrical Devices, Automation, and Motion, 2008,
pp. 789–791.) (b) With residual charge removal. (Agnes, A. et al., Analog Integrated Circuits
and Signal Process, 54, 183, 2010.)](https://image.slidesharecdn.com/2616755-250518113039-87896857/85/Cmos-Timemode-Circuits-And-Systems-Fundamentals-And-Applications-Fei-Yuan-49-320.jpg)
![20 CMOS Time-Mode Circuits and Systems: Fundamentals and Applications
where
I k V V
DS n GS T
3 3 3
2
= -
( ) (2.13)
is the dc current of M3, and
g k V V
m n GS T
3 3 3
2
= -
( ) (2.14)
is the transconductance of M3. It is seen from Equation 2.12 that the second-order
term can be neglected if vGS3 is small. The increase of vGS3 will give rise to an increase
in iDS3, which will in turn boost the voltage of the source of M3. vGS3 will then drop
due to the negative voltage feedback provided by the source degeneration resistor
Rs. The reduced swing of vGS will improve the linearity of iDS3 ~ vGS3 characteristics.
Like any negative feedback, source degeneration reduces the conversion gain. This
is the price paid for linearity improvement.
In addition to linearity improvement, another added bonus of source degeneration
is the improved bandwidth of the transconductor. In fact, source degeneration is a
technique widely used to boost the bandwidth of continuous-time linear equalizers
in multi-Gbps serial links [21].
To provide a quantitative comparison of the improvement of linearity obtained
from source degeneration, we examine the current of the transconductor with and
without source degeneration resistor Rs. To simplify analysis, we again neglect the
effect of channel length modulation. When Rs is absent, we have
i k v V
DS n in T
3 3
2
= -
( ) . (2.15)
When Rs is present, we have
i k v R i V
DS n in s DS T
3 3 3
2
= - -
( ) , (2.16)
Rearranging Equation 2.16 in the standard quadratic equation of iDS3
k R i k v V R i k v V
n s DS n in T s DS n in T
3
2
3
2
3 3 3
2
1 2 0
- + -
é
ë ù
û + - =
( ) ( ) , (2.17)
and solving Equation 2.17 for iDS3 yield
i
k R
k v V
k v V k R
DS
n s
n in T
n in T n
3
3
2 3
3
2
3
2
1
2
1 2
1 2 4
= + -
é
ë ù
û
± + -
é
ë ù
û -
( )
( ) s
s in T
v V
2 2
-
( ) . (2.18)
It becomes evident from Equation 2.18 that the second-order relation between iDS3
and vin present in Equation 2.15 vanishes in Equation 2.18.](https://image.slidesharecdn.com/2616755-250518113039-87896857/85/Cmos-Timemode-Circuits-And-Systems-Fundamentals-And-Applications-Fei-Yuan-50-320.jpg)
![21
Voltage-to-Time Converters
The residual charge of the parasitic capacitor Cs, which consists of the gate-source
capacitance and source-substrate junction capacitance of M3, as well as the parasitic
capacitance of Rs, exists at the end of the discharge phase. This is particularly true if
the duration of the discharge phase, which is often constrained by sampling rate, is
short and the time constant RsCs is large. Note that a large Rs is desired in providing a
strong negative feedback, and subsequently the better linearity of the transconductor.
As a result, a large source voltage of M3 might exist at the onset of the next discharge
phase. This initial voltage sets the lower bound of the gate voltage of M3 to
v v V
in C T
s
, ( )
min = +
-
0 (2.19)
where vCs
(0−) is the voltage of Cs at the beginning of the discharge phase. Also, the
current of M3 is no longer solely determined by vin but rather by both vin and vCs
(0−)
i k v v V v
DS n in C T DS
S
3 3
2
3
0 1
= - -
é
ë
ù
û +
( )
-
( ) .
l (2.20)
The residual charge of Cs can be removed by adding a reset transistor M4 in paral-
lel with Rs, as shown in Figure 2.5b [22]. M4 is gated by ϕ. In the precharge phase
where ϕ = 0, Cs is fully reset and vs = 0. In the discharge phase where ϕ = 1, the
reset operation is disabled so that M4 has no effect on the discharge of the load
capacitor. Note that M4 needs to be sufficiently large in order to minimize its ON
resistance so that the reset operation can be completed in the precharge phase, that is,
(Rs ∥Ron4) Cs should be much smaller as compared with the duration of the precharge
phase. A downside of large M4 is the increase of Cs.
2.3â•… RELAXATION VOLTAGE-TO-TIME CONVERTERS
The preceding VTCs precharge the load capacitor first and then drain the charge of
the capacitor with the current controlled by the input voltage. Alternatively, voltage-
to-time conversion can be performed by first charging the load capacitor with the
input voltage and then discharging the capacitor with a constant current, as shown in
Figure 2.6 [8,11,23,24]. We term these VTCs relaxation VTCs due to their resemblance
to the operation of relaxation oscillators. Note that at the onset of the discharge phase,
vc Vref must be satisfied. vo is thus at logic-0 initially. The comparator will change its
output when vc drops below the reference voltage Vref. The value of the resultant time
variable Tin, which is defined from the time instant at which ϕ1 = 0 to the time instant
at which vc drops below Vref, depends upon the input voltage vin, the drain current I, and
the reference voltage Vref. For a given I in kth period, it can be shown that
T kT
C
I
v kT V
in in ref
( ) ( ) .
= -
é
ë ù
û (2.21)
It is evident from Equation 2.21 that Tin(kT) is directly proportional to the sampled
value of the input voltage vin(kT).](https://image.slidesharecdn.com/2616755-250518113039-87896857/85/Cmos-Timemode-Circuits-And-Systems-Fundamentals-And-Applications-Fei-Yuan-51-320.jpg)
![23
Voltage-to-Time Converters
residual charge of the sampling capacitor at the end of each clock cycle becomes vital
to ensure the one-to-one mapping between vin and vc in each clock cycle.
The VCDU-based VTCs in Figure 2.1 perform voltage-to-time conversion in two
steps: They first perform voltage-to-current conversion using a transconductor and
then current-to-time conversion using a current-starved delay cell. Although the lat-
ter exhibits a perfect linearity ensured by both the constant discharge current and
the linear load capacitor, the voltage-to-time conversion performed in the first step
suffers from a poor linearity. The VTC in Figure 2.6 offers the advantage of a bet-
ter linearity as the input voltage vin is sampled by a linear capacitor C directly. No
voltage-to-current conversion is performed on vin. Another distinct characteristic of
the relaxation VTC is that the gain of the VTC can be adjusted by varying I. For a
given vin(kT), the larger the discharge current I, the smaller is the resultant time vari-
able and the lower the conversion gain. On the other hand, the larger the discharge
current I, the faster is the voltage-to-time conversion. The gain and conversion time
of VCDU-based VTCs, however, cannot be adjusted.
2.4â•… REFERENCE VOLTAGE-TO-TIME CONVERTERS
The preceding VTC uses a fixed reference voltage with which input-dependent
voltage vc compares. Alternatively, one can perform voltage-to-time conversion by
making the input voltage vin the reference voltage and the voltage that compares
with vin comes from a ramping voltage generator with a constant slope, as shown in
Figure 2.7 [25]. We term these VTCs reference VTCs, as the voltage to be converted
is now the reference voltage with which the ramping voltage compares. Reference
VTCs are also known as pulse-width-modulation generators as they map the ampli-
tude of an input voltage to the width of a pulse linearly [26].
vin
1
1
vc
C
I
–
+
vo
2
1
vin(kT)
Tin(kT) Tin(kT+T)
vin(kT+T)
t
t
t
t
kT (k+1)T (k+2)T
vc
vo
2
FIGURE 2.7â•… Voltage-to-time converter with input the reference voltage. (From Oh, T. and
Hwang, I., IEEE Trans. VLSI Syst., 2014.)](https://image.slidesharecdn.com/2616755-250518113039-87896857/85/Cmos-Timemode-Circuits-And-Systems-Fundamentals-And-Applications-Fei-Yuan-53-320.jpg)
![24 CMOS Time-Mode Circuits and Systems: Fundamentals and Applications
The input voltage vin is fed to the noninverting terminal of the comparator. At the
assertion of ϕ1 = 1, capacitor C is reset and vin is sampled by the input capacitor of
the comparator. The output voltage vo is set to logic-1. When ϕ2 = 1, the capacitor
is charged by a constant current I and vc rises linearly with time. When vc exceeds
vin(kT), the output of the comparator will change from logic-1 to logic-0. The resul-
tant time variable Tin, which is measured from the time instant at which ϕ2 = 1 is
asserted to the time instant at which vc exceeds vin(kT), is given by
T kT
C
I
v kT
in in
( ) ( ).
= (2.24)
It is evident from Equation 2.24 that Tin(kT) is directly proportional to the sampled
input voltage vin(kT).
Reference VTCs possess the similar properties as those of relaxation VTCs in
Figure 2.6, specifically, a good linearity as no voltage-to-current conversion is per-
formed on vin and a tunable conversion gain obtained by adjusting I. In addition,
reference VTCs offer an infinite input impedance, an attractive property for many
applications.
2.5â•… TIME-MODE COMPARATORS
Having investigated VTCs, in this section, we explore the applications of VTCs in
time-mode comparators. It is well understood that voltage-mode comparators suffer
from a number of drawbacks, in particular, the mismatch-induced offset voltage that
deteriorates with technology scaling [27]. To improve the accuracy of voltage-mode
comparators, digitally assisted calibration, which is typically power and area hungry,
is needed. It was shown by Agnes et al. that voltage-mode comparators can also be
implemented first by converting both the input and reference voltages to time vari-
ables using VTCs. The resultant time variables are then compared using a single-bit
time quantizer, which accepts two time-mode inputs A and B and outputs a logic-1 if
A leads B or a logic-0 otherwise. Figure 2.8 shows the schematic of the time-mode
comparator proposed by Agnes et al. [22,28]. The waveforms of the critical nodes
are sketched in Figure 2.9. The operation of the comparator is briefly depicted here:
In the precharge phase where ϕ = 0, both C1 and C2 are fully charged (vc1, vc2 = VDD).
M6a and M6b, in the mean time, short the output nodes to the ground (vo1, vo2 = 0).
The parasitic capacitors at the nodes of Rs1 and Rs2 are reset by M4a and M4b, respec-
tively. In the discharge phase where ϕ = 1, C1 and C2 are discharged with their
discharge currents controlled by vin and vref, respectively. Assume in kth discharge
phase, vin vref, C1 will be discharged slower than C2 and vc1 vc2 will follow. When
vc2 VDD − VT, M5b will turn on. Cout2 will be charged, and vo2 will arise. Similarly,
when vc1 VDD − VT, M5a will turn on. Cout1 will be charged, and vo1 will arise. Since
vo2 rises first, it will reach the threshold voltage VT,inv of the downstream inverter first.
As a result, Clk of the DFF is reset first and Q = 1 is set when Clk = 0. Similarly one
can show in (k + 1)th sampling period, Clk will be reset after D = 0 is set. The dura-
tion of Q is bordered by the time instants at which by Clk = 0.](https://image.slidesharecdn.com/2616755-250518113039-87896857/85/Cmos-Timemode-Circuits-And-Systems-Fundamentals-And-Applications-Fei-Yuan-54-320.jpg)
![The estate and castle of Doña Maria passed in time, as a pious
donation, to the Cathedral of Seville, the chapter of which has, in
our days, sold it to a private gentleman. The associations passed for
nothing, since a little while afterward, the withered, old, and
furrowed Doña Maria appeared clothed in the whitest of lime, and
adorned with brilliants of crystal.
Let us follow the road which advances, opening its way through the
palmettos and evergreens of some pasture-lands, until it enters the
village of Dos-Hermanas, [Footnote 85] situated in the midst of a
sandy plain, two leagues from Seville.
[Footnote 85: Dos-Hermanas, two sisters. ]
One sees here neither river, nor lake, nor umbrageous trees, nor
rural houses with green blinds, nor arbors covered with twining
plants, nor peacocks and Guinea fowls picking the green turf, nor
grand avenues of trees in straight lines, like slaves holding parasols,
to provide a constant shade for those who walk beneath. All these
are wanting here. Sad it is to confess it! All is common, rude, and
inelegant, but instead, one meets good and contented faces, which
prove how little those things are needed to make happiness. One
sees, beside, flowers in the yards of the houses, and at their doors
gay and healthy children, even more numerous than the flowers,
and finds that sweet peace of the country, made up of silence and
solitude, an atmosphere of Eden and the sky of paradise.
The village consists of houses of a single story, arranged in long,
straight, though not parallel streets, which open upon the large,
sandy market-place, spread out like a yellow carpet before a fine
church, which lifts its lofty tower, surmounted by a cross, like a
soldier elevating his standard.
{498}
Behind the church we shall find the oasis of this desert. Supported
by the rear wall of the edifice is a gate, opening into a wide and vast](https://image.slidesharecdn.com/2616755-250518113039-87896857/85/Cmos-Timemode-Circuits-And-Systems-Fundamentals-And-Applications-Fei-Yuan-73-320.jpg)
Cmos Timemode Circuits And Systems Fundamentals And Applications Fei Yuan
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- 10. Mixed-Signal Circuits Thomas Noulis Mobile Point-of-Care Monitors and Diagnostic Device Design Walter Karlen Multisensor Data Fusion: From Algorithm and Architecture Design to Applications Hassen Fourati Nano-Semiconductors: Devices and Technology Krzysztof Iniewski Nanoelectronic Device Applications Handbook James E. Morris and Krzysztof Iniewski Nanomaterials: A Guide to Fabrication and Applications Sivashankar Krishnamoorthy Nanopatterning and Nanoscale Devices for Biological Applications Šeila Selimovic´ Nanoplasmonics: Advanced Device Applications James W. M. Chon and Krzysztof Iniewski Nanoscale Semiconductor Memories: Technology and Applications Santosh K. Kurinec and Krzysztof Iniewski Novel Advances in Microsystems Technologies and Their Applications Laurent A. Francis and Krzysztof Iniewski Optical, Acoustic, Magnetic, and Mechanical Sensor Technologies Krzysztof Iniewski Optical Fiber Sensors: Advanced Techniques and Applications Ginu Rajan Optical Imaging Devices: New Technologies and Applications Ajit Khosla and Dongsoo Kim Organic Solar Cells: Materials, Devices, Interfaces, and Modeling Qiquan Qiao Physical Design for 3D Integrated Circuits Aida Todri-Sanial and Chuan Seng Tan Radiation Detectors for Medical Imaging Jan S. Iwanczyk Radiation Effects in Semiconductors Krzysztof Iniewski Reconfigurable Logic: Architecture, Tools, and Applications Pierre-Emmanuel Gaillardon Semiconductor Radiation Detection Systems Krzysztof Iniewski PUBLISHED TITLES:
- 11. Smart Grids: Clouds, Communications, Open Source, and Automation David Bakken Smart Sensors for Industrial Applications Krzysztof Iniewski Soft Errors: From Particles to Circuits Jean-Luc Autran and Daniela Munteanu Solid-State Radiation Detectors: Technology and Applications Salah Awadalla Technologies for Smart Sensors and Sensor Fusion Kevin Yallup and Krzysztof Iniewski Telecommunication Networks Eugenio Iannone Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits Sandeep K. Goel and Krishnendu Chakrabarty VLSI: Circuits for Emerging Applications Tomasz Wojcicki Wireless Technologies: Circuits, Systems, and Devices Krzysztof Iniewski Wireless Transceiver Circuits: System Perspectives and Design Aspects Woogeun Rhee FORTHCOMING TITLES: Advances in Imaging and Sensing Shuo Tang, Dileepan Joseph, and Krzysztof Iniewski Analog Electronics for Radiation Detection Renato Turchetta Circuits and Systems for Security and Privacy Farhana Sheikh and Leonel Sousa Magnetic Sensors: Technologies and Applications Kirill Poletkin MRI: Physics, Image Reconstruction, and Analysis Angshul Majumdar and Rabab Ward Multisensor Attitude Estimation: Fundamental Concepts and Applications Hassen Fourati and Djamel Eddine Chouaib Belkhiat Nanoelectronics: Devices, Circuits, and Systems Nikos Konofaos Power Management Integrated Circuits and Technologies Mona M. Hella and Patrick Mercier PUBLISHED TITLES:
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- 13. CRC Press is an imprint of the Taylor & Francis Group, an informa business Boca Raton London NewYork CMOS Time-Mode Circuits and Systems EDITED BY FEI YUAN Ryerson University, Toronto, Canada Fundamentals and Applications KRZYSZTOF INIEWSKI MANAGING EDITOR CMOS Emerging Technologies Research Inc. Vancouver, British Columbia, Canada
- 14. MATLAB® is a trademark of The MathWorks, Inc. and is used with permission. The MathWorks does not warrant the accuracy of the text or exercises in this book. This book’s use or discussion of MAT- LAB® software or related products does not constitute endorsement or sponsorship by The MathWorks of a particular pedagogical approach or particular use of the MATLAB® software. CRC Press Taylor & Francis Group 6000 Broken Sound Parkway NW, Suite 300 Boca Raton, FL 33487-2742 © 2016 by Taylor & Francis Group, LLC CRC Press is an imprint of Taylor & Francis Group, an Informa business No claim to original U.S. Government works Version Date: 20151012 International Standard Book Number-13: 978-1-4822-9874-1 (eBook - PDF) This book contains information obtained from authentic and highly regarded sources. Reasonable efforts have been made to publish reliable data and information, but the author and publisher cannot assume responsibility for the validity of all materials or the consequences of their use. The authors and publishers have attempted to trace the copyright holders of all material reproduced in this publication and apologize to copyright holders if permission to publish in this form has not been obtained. If any copyright material has not been acknowledged please write and let us know so we may rectify in any future reprint. Except as permitted under U.S. Copyright Law, no part of this book may be reprinted, reproduced, transmitted, or utilized in any form by any electronic, mechanical, or other means, now known or hereafter invented, including photocopying, microfilming, and recording, or in any information stor- age or retrieval system, without written permission from the publishers. For permission to photocopy or use material electronically from this work, please access www.copy- right.com (http://www.copyright.com/) or contact the Copyright Clearance Center, Inc. (CCC), 222 Rosewood Drive, Danvers, MA 01923, 978-750-8400. CCC is a not-for-profit organization that pro- vides licenses and registration for a variety of users. For organizations that have been granted a photo- copy license by the CCC, a separate system of payment has been arranged. Trademark Notice: Product or corporate names may be trademarks or registered trademarks, and are used only for identification and explanation without intent to infringe. Visit the Taylor & Francis Web site at http://www.taylorandfrancis.com and the CRC Press Web site at http://www.crcpress.com
- 15. ix Contents Preface.......................................................................................................................xi Acknowledgments.....................................................................................................xv Editors.....................................................................................................................xvii Contributors.............................................................................................................xix Symbols and Abbreviations.....................................................................................xxi Chapter 1)>> Introduction to Time-Mode Signal Processing.....................................1 Fei Yuan Chapter 2)>> Voltage-to-Time Converters................................................................13 Fei Yuan Chapter 3)>> Fundamentals of Time-to-Digital Converters.....................................33 Fei Yuan Chapter 4)>> A Novel Three-Step Time-to-Digital Converter with Phase Interpolation...................................................................................... 121 Kang-Yoon Lee Chapter 5)>> Design Principles for Accurate, Long-Range Interpolating Time-to-Digital Converters............................................................... 141 Pekka Keränen, Jussi-Pekka Jansson, Antti Mäntyniemi, and Juha Kostamovaara Chapter 6)>> Fundamentals of Time-Mode Analog-to-Digital Converters........... 177 Fei Yuan Chapter 7)>> Time-Mode Delta-Sigma Converters................................................237 Soheyl Ziabakhsh, Ghyslain Gagnon, and Gordon W. Roberts Chapter 8)>> Fundamentals of Time-Mode Phase-Locked Loops.........................301 Fei Yuan
- 16. x Contents Chapter 9 Time-Mode Circuit Concepts and Their Transition to All-Digital Synthesizable Circuits................................................ 331 Moataz Abdelfattah and Gordon W. Roberts Chapter 10 Time-Mode Temperature Sensors.....................................................377 Fei Yuan Index.......................................................................................................................393
- 17. xi Preface The rapid scaling of complementary metal oxide semiconductor (CMOS) technol- ogy has resulted in the sharp increase of time resolution and the continuous decrease of voltage headroom. As a result, time-mode circuits where information is repre- sented by the time difference between the occurrence of digital events, rather than the nodal voltages or branch currents of electric networks, offer a viable and technol- ogy-friendly means to combat scaling-induced difficulties encountered in the design of mixed-mode systems. Time-mode approaches have found a broad spectrum of applications since their inception in time-of-flight measurement several decades ago. These applications include digital storage oscillators, laser-based vehicle naviga- tion systems, analog-to-digital data converters, signal processing, medical imaging, instrumentation, infinite and finite impulse response filters, all digital phase-locked loops, giga-bit-per-second (Gbps) serial links, and channel select filters for software- defined radio, to name a few. Various architectures and design techniques of time- mode circuits have emerged recently; a comprehensive examination of the principles of time-based signal processing and the design techniques of time-mode circuits, however, is not available. This book provides the fundamentals of time-based signal processing with an emphasis on the design techniques and applications of CMOS time-mode circuits. Chapter 1 examines the fundamentals of time-mode circuits. The definition of time-based signal processing is provided. The characteristics of time-mode circuits are examined and compared with those of their voltage-mode and current-mode counterparts. Challenges encountered in time-based signal processing are investi- gated. The key building blocks of time-mode circuits are briefly examined with a detailed study of these building blocks in later chapters. The applications of time- based approaches in mixed-mode signal processing are discussed briefly. Chapter 2 deals with voltage-to-time converters. An emphasis is given to the tech- niques that improve the linearity of voltage-to-time converters. Voltage-to-time con- verters using voltage-controlled delay units are studied, and their pros and cons are examined in detail. Voltage-to-time converters using voltage-controlled delay units and source degeneration are also investigated. Relaxation voltage-to-time convert- ers that provide a better linearity are studied. Reference voltage-to-time converters that also exhibit a good linearity are examined. The applications of voltage-to-time converters in time-mode comparators are investigated. Chapter 3 provides a comprehensive treatment of the principles, architectures, and design techniques of time-to-digital converters (TDCs) with an emphasis on the critical assessment of the advantages and limitations of each class of TDCs. It first provides the classification of TDCs. The key performance indicators of TDCs are then depicted. Sampling TDCs where time variables are digitized directly such as counter TDCs, delay line TDCs, TDCs with interpolation, vernier delay line TDCs, pulse-shrinking TDCs, pulse-stretching TDCs, successive approximation TDCs, flash TDCs, and pipelined TDCs are investigated in detail. Noise-shaping TDCs that suppress in-band quantization noise such as gated ring oscillator TDCs,
- 18. xii Preface switched ring oscillator TDCs, gated relaxation oscillator TDCs, MASH TDCs, and ΔΣ TDCs are studied. Chapter 4 starts with a brief review of TDC architectures. A three-step TDC with phase interpolation is introduced to improve the resolution and reduce the power consumption and die area. The resolution of the three-step TDC with phase interpo- lation is improved by using a phase interpolator and a time amplifier for the improve- ment of the in-band phase noise when used in all-digital phase-locked loops. Chapter 5 introduces some important performance parameters of time inter- val measurements. It is followed by the presentation of basic counting methods for time measurement. Interpolation methods for performance improvement are presented and analyzed in a greater detail. We show that the combination of the counter method with the interpolation of timing pulse positions within the clock period provides a very efficient method for realizing a high-precision, accurate TDC with a wide operation range. This approach combines the inherently good single-shot resolution of a short-range interpolator based on digital delay line techniques with the excellent accuracy and wide linear range of the counting method. It is shown that in a general measurement situation where the timing pulses are asynchronous with respect to the system clock, the effect of interpola- tor nonlinearities on the final averaged output is strongly suppressed due to the inherent averaging effect of the interpolation method. On the other hand, these nonlinearities widen the distribution of the measured single-shot results and in many cases limit the single-shot precision of the TDC. It is also pointed out that the careful synchronization of the timing signals is needed in order to get unam- biguous measurement results that are free from systematic errors. Finally, two case studies show that, with the aforementioned approaches, a TDC realized in standard nonaggressive CMOS technologies can achieve a ps-level resolution and a single-shot precision better than 10 ps (sigma value) over a wide operation range of hundreds of microseconds. Chapter 6 explores the time-mode techniques that overcome the difficulties encountered in the realization of multibit voltage-mode analog-to-digital convert- ers. The chapter starts with the close examination of the key parameters and figure of merits that quantify the performance of analog-to-digital converters. It is fol- lowed by the detailed study of the principles and properties of multibit quantizers realized using voltage-controlled ring oscillators. Both voltage-controlled oscilla- tor (VCO)-based phase and frequency quantizers are studied. The chapter contin- ues with the investigation of open-loop analog-to-digital converters utilizing VCO phase and frequency quantizers. The chapter first reviews the fundamentals of ΔΣ modulators in closed-loop time-mode analog-to-digital converters. Time-mode ΔΣ modulators are then introduced, and their characteristics are investigated in detail. Time-mode ΔΣ modulators with VCO phase and frequency quantizers are explored. ΔΣ modulators with phase feedback are also examined. ΔΣ modulators with pulse- width modulation for linearity improvement are explored. Multistage, also known as MASH time-mode ΔΣ modulators, both single-rate and multirate are examined. Dynamic element matching, an effective technique to minimize the effect of the mismatch of digital-to-analog converters, is briefly studied with the inclusion of an exhaustive list of published studies on dynamic element matching. The chapter ends
- 19. xiii Preface with the comparison of the performance of some recently reported time-mode ΔΣ modulators. Chapter 7 describes ΔΣ converters that adopt time-mode signal processing tech- niques. A key advantage of time-mode ΔΣ converters is that they are realized using digital circuits and process information in the form of time-difference intervals. As a consequence of using digital circuits, this technique benefits from low-voltage opera- tion without concern for reduced signal swings, sensitivities to thermal noise effects, or switching noise sensitivity. Recently, several studies on time-mode ΔΣ convert- ers are conducted showing that such methodology has high potential in low-voltage design. The noise-shaping behavior demonstrated by this technique can be imple- mented and extended in various ways, including voltage-controlled delay unit or gated-ring-oscillator-based implementations of TM ΔΣ converters. In this chapter, after a brief review of ΔΣ ADC specifications, the different architectures of TM ΔΣ converters that have been recently proposed are examined. Chapter 8 covers the fundamentals of all-digital phase-locked loops. The chapter starts with a close examination of the drawbacks of charge-pump phase-locked loops. It is followed by a detailed examination of the phase noise of phase-locked loops. The basic configuration of all-digital phase-locked loops is then studied. An inves- tigation of digitally controlled oscillators is followed. The phase noise of all-digital phase-locked loops is studied. The chapter ends with a brief examination of all- digital frequency synthesizers. Chapter 9 outlines the general concepts related to time-mode signal processing and some of its state-of-the-art applications. These provide a very good alternative to conventional techniques, which suffer from problems such as linearity and accuracy limitations among others. The ultimate goal of this chapter is to arrive at all-digital time-domain circuits that can be synthesized using existing digital computer-aided design tools and to make the design process fully automated in contrast to its con- ventional analog counterpart. Chapter 10 studies time-mode-integrated temperature sensors. Both relaxation oscillator temperature sensors and ring oscillator temperature sensors are investi- gated. Temperature sensors that utilize TDCs are also studied. It further investigates digital set point temperature sensors. The chapter ends with a comparison of the performance of some recently reported time-mode temperature sensors. The book provides a comprehensive treatment of the principles and design tech- niques of CMOS time-mode circuits. Readers are assumed to have a fundamental knowledge of electrical networks, semiconductor devices, CMOS analog and digi- tal integrated circuits, feedback systems, signals and systems, and communication systems. As time-mode circuits and systems are still a domain of active research, new architectures and implementations continue to emerge. The book by no means attempts to provide a complete collection of time-mode circuits and systems; it rather provides the fundamentals of time-based signal processing and the design techniques of CMOS time-mode circuits and systems and, therefore, is intended to serve as a source for those who are interested in time-based signal processing to explore fur- ther in this exciting field of research. A rich collection of recently published work on time-mode circuits and systems is provided at the end of each chapter so that readers can seek further information on the subjects covered in the book.
- 20. xiv Preface Although an immense amount of effort was made in the preparation of the manu- script, flaws and errors might exist due to erring human nature and time constraints. Suggestions and corrections from readers are gratefully appreciated by the editors and authors. Fei Yuan Krzysztof (Kris) Iniewski Toronto, Ontario, Canada MATLAB® is a registered trademark of The MathWorks, Inc. For product informa- tion, please contact: The MathWorks, Inc. 3 Apple Hill Drive Natick, MA 01760-2098 USA Tel: 508-647-7000 Fax: 508-647-7001 E-mail: info@mathworks.com Web: www.mathworks.com
- 21. xv Acknowledgments The editors are deeply grateful to all the authors for their contributions to this book. A special thank-you goes to Professor Juha Kostamovaara of the University of Oulu, Finland, and Professor Gordon Roberts of McGill University, Canada, who are great pioneers in the fields of time-to-digital conversion and time-based signal � processing, for their contributions to this book. The editorial staff of Taylor & Francis Group/CRC Press, especially Nora Konopka, the publisher of engineering and environmental sciences; Jessica Vakili, senior � project coordinator, editorial project development; and Michele Smith, senior editorial assistant (engineering), have been warmly supportive from the initial approval of the book proposal to the publishing of the book. It has been a wonderful experience working with Taylor & Francis Group/CRC Press. Finally, and most importantly, this book could not have been possible without the unconditional support of our families.
- 23. xvii Editors Dr. Fei Yuan earned his BEng in electrical engineering from Shandong University, Jinan, Shandong, China, in 1985, and MASc in chemical engineering and PhD in electrical engineering from the University of Waterloo, Canada, in 1995 and 1999, respectively. He was a lecturer in the Department of Electrical Engineering, Changzhou Institute of Technology, Jiangsu, China, during 1985–1989. In 1989, he was a visiting professor at Humber College of Applied Arts and Technology, Toronto, Ontario,Canada,andLambtonCollegeofAppliedArtsandTechnology,Sarnia, Ontario, Canada. He worked with Paton Controls Limited, Sarnia, Ontario, Canada, as a con- trols engineer during 1989–1994. Since 1999, he has been with the Department of Electrical and Computer Engineering, Ryerson University, Ontario, Canada, where he is currently a professor and the chair. Dr. Yuan is the author of CMOS Current- Mode Circuits for Data Communications (Springer, 2007), CMOS Active Inductors and Transformers: Principle, Implementation, and Applications (Springer, 2008), and CMOS Circuits for Passive Wireless Microsystems (Springer, 2010) and the principal coauthor of Computer Methods for Analysis of Mixed-Mode Switching Circuits (Kluwer Academic, 2004). In addition, he has authored/coauthored approx- imately 200 research papers in refereed journals and conference proceedings. Dr. Yuan was awarded a postgraduate scholarship by Natural Science and Engineering Research Council of Canada during 1997–1998, the Teaching Excellence Award by Changzhou Institute of Technology in 1988, and the Dean’s Research Excellence Award and the Ryerson Research Chair Award in 2004 and 2005, respectively, by Ryerson University. Dr. Yuan is a registered professional engineer in the province of Ontario, Canada. He can be reached at fyuan@ryerson.ca. Dr. Krzysztof (Kris) Iniewski manages R&D at Redlen Technologies Inc., a start- up company in Vancouver, Canada. Redlen’s revolutionary production process of advanced semiconductor materials enables a new generation of more accurate, all- digital, radiation-based imaging solutions. Dr. Iniewski is also president of CMOS Emerging Technologies Research Inc. (www.cmosetr.com), an organization covering high-tech events on communications, microsystems, optoelectronics, and sensors. In his career, Dr. Iniewski has held numerous faculty and management positions at the University of Toronto, the University of Alberta, Simon Fraser University, and PMC-Sierra Inc. He has published more than 100 research papers in international journals and conferences. He holds 18 international patents granted in the United States, Canada, France, Germany, and Japan. He is a frequent invited speaker and has consulted for multiple organizations worldwide. He has written and edited sev- eral books for publishers such as CRC Press, Cambridge University Press, IEEE Press, Wiley, McGraw Hill, Artech House, and Springer. His personal goal is to con- tribute to healthy living and sustainability through innovative engineering solutions. In his leisure time, he can be reached at kris.iniewski@gmail.com.
- 25. xix Contributors Moataz Abdelfattah Department of Electrical and Computer Engineering McGill University Montréal, Québec, Canada Ghyslain Gagnon École de Technologie Supèrieure Universitè du Quèbec Montrèal, Quèbec, Canada Jussi-Pekka Jansson Electronics Laboratory Department of Electrical Engineering University of Oulu Linnanmaa, Finland Pekka Keränen Electronics Laboratory Department of Electrical Engineering University of Oulu Linnanmaa, Finland Juha Kostamovaara Electronics Laboratory Department of Electrical Engineering University of Oulu Linnanmaa, Finland Kang-Yoon Lee College of Information and Communication Engineering Sungkyunkwan University Seoul, Republic of Korea Antti Mäntyniemi Electronics Laboratory Department of Electrical Engineering University of Oulu Linnanmaa, Finland Gordon W. Roberts Department of Electrical and Computer Engineering McGill University Montrèal, Quèbec, Canada Fei Yuan Department of Electrical and Computer Engineering Ryerson University Toronto, Ontario, Canada Soheyl Ziabakhsh École de Technologie Supèrieure Universitè du Quèbec Montrèal, Quèbec, Canada
- 27. xxi Symbols and Abbreviations Symbol)>>Description Cox)>> Gate-oxide capacitance per unit area gm)>>Transconductance go)>> Output conductance IDS)>> Drain-source channel current (DC) iDS)>> Drain-source channel current (DC + AC) ids)>> Drain-source channel current (AC) k)>> Boltzmann constant (1.38066 × 10−23 J/K) KLF)>> Gain of loop filters KPD)>> Gain of phase detectors KVCO)>> Phase-voltage gain of voltage-controlled oscillators L)>> Channel length of MOS transistors ni)>> Concentration of intrinsic charge carriers in silicon (1.5 × 1010 at 300 K) Pe)>> Power of quantization error pe)>> Probability density function of quantization error q)>> Charge of electron (1.60217657 × 10−19 C) Q)>> Quality factor Ron)>> Channel resistance of MOS transistors in triode To)>> Reference temperature, typically 300 K or 27°C (room temperature) tox)>> Thickness of gate oxide VDD)>> Supply voltage VGS)>> Gate-source voltage (DC) vGS)>> Gate-source voltage (DC + AC) vgs)>> Gate-source voltage (AC) V T)>> Threshold voltage of MOS transistors VTn)>> Threshold voltage of NMOS transistors VTp)>> Threshold voltage of PMOS transistors W)>> Channel width of MOS transistors aVT )>> Temperature coefficient of threshold voltage of MOS transistors γ)>> Body effect coefficient of MOSFETs Γ(ωoτ) Impulse sensitivity function Δ Quantization error ϵox)>> Dielectric constant of oxide (3.5 × 1013 F/cm) ϵsi)>> Dielectric constant of silicon (1.05 × 1012 F/cm) λ)>> Channel length modulation coefficient μn)>> Surface mobility of electrons μp)>> Surface mobility of poles ξ)>> Damping factor of phase-locked loops τPHL)>> High-to-low propagation delay
- 28. xxii Symbols and Abbreviations τPLH)>> Low-to-high propagation delay ϕF)>> Fermi potential ωn)>> Loop bandwidth of phase-locked loops Abbreviations ΔΣ)>>Delta-sigma AAF)>> Antialiasing filter AC)>> Alternating current ADC)>> Analog-to-digital converter ADPLL)>> All-digital phase-locked loop ASP)>> Analog signal processing BiDWA)>> Bidirectional data-weighted averaging BP)>> Band pass CAD)>> Computer-aided design CLA)>> Conventional clocked average CMOS)>> Complementary metal oxide semiconductor CRO)>> Coupled ring oscillator CP)>> Charge pumps CT)>> Continuous time DAC)>> Digital-to-analog converter dB)>>Decibel DC)>> Direct current DCDL)>> Digital-controlled delay line DCO)>> Digitally controlled oscillator DD)>> Double delay DEM)>> Dynamic element matching DFE)>> Decision feedback equalization DFF)>> D-type flip-flip DLL)>> Delay-locked loop DNL)>> Differential nonlinearity DR)>> Dynamic range DT)>> Discrete time DTC)>> Digital-to-time converter DTF)>> Distortion transfer function DWA)>> Data-weighted averaging ED)>> Edge detector ENOB)>> Effective number of bits FCW)>> Frequency control word FE)>> Forward Euler FET)>> Field effect transistor FFT)>> Fast Fourier transform FGRO)>> Fast gated-ring oscillator FIR)>> Finite impulse filter FOM)>> Figure of merit FSR)>> Full-scale range
- 29. xxiii Symbols and Abbreviations Gbps)>> Giga bit per second GHz)>>Gigahertz GRO)>> Gated-ring oscillator GSRO)>> Gated switched ring oscillator HP)>> High pass Hz)>>Hertz IC)>> Integrated circuit IIR)>> Infinite impulse filter ILA)>> Individual level averaging INL)>> Integral nonlinearity ISF)>> Impulse sensitivity function KHz)>>Kilohertz LDI)>> Lossless discrete integrator LP)>> Low pass LSB)>> Least significant bit LTI)>> Linear time-invariant LUT)>> Look-up table MASH)>> Multistage noise-shaping MDLL)>> Multiplying delay-locked loop MHz)>>Megahertz MIM)>>Metal-insulator-metal MOS)>> Metal oxide semiconductor MSB)>> Most significant bit MUX)>>Multiplexer NMOS)>> n-type metal oxide semiconductor NTF)>> Noise transfer function OPAMP)>> Operational amplifier OSR)>> Oversampling ratio OTA)>> Operational transconductance amplifier PD)>> Phase detector PFD)>> Phase frequency detector PHL)>> Propagation delay high-to-low PI)>> Phase interpolator PLH)>> Propagation delay low-to-high PLL)>> Phase-locked loop PMOS)>> p-type metal oxide semiconductor PSD)>> Power spectral density PTAT)>> Proportional to absolute temperature PVT)>> Process, voltage, and temperature PWM)>> Pulse-width modulation QPSK)>> Quadrature phase shift keying RC)>>Resistor–capacitor RDA)>> Random averaging RDWA)>> Rotated data-weighted averaging RF)>> Radio frequency RFID)>> Radio frequency identification
- 30. xxiv Symbols and Abbreviations RJ)>> Random jitter RLC)>> Resistor, inductor (L), and capacitor RMS)>> Root mean square RnDWA)>> Randomized data-weighted averaging RS)>>Reset-set RTA)>> Resistor tuning array SA)>> Successive approximation SAR)>> Successive approximation register SC)>> Switched capacitor SDU)>> Switched delay unit SFDR)>> Spurious-free dynamic range SGRO)>> Slow gated-ring oscillator S/H)>> Sample and hold SNDR)>> Signal-to-noise-plus-distortion ratio SNR)>> Signal-to-noise ratio SPICE)>> Simulation program with integrated circuit emphasis SR)>>Set-reset SRO)>> Switched ring oscillator SSB)>> Single side band STF)>> Signal transfer function T2B)>> Thermometer to binary TA)>> Time amplifier TAC)>> Time-to-amplitude converters TCC)>> Temperature coefficient of current TDC)>> Time-to-digital converter TM)>> Time mode TMSP)>> Time-mode signal processing T-Reg)>> Time register TSPC)>> True single phase logic TVC)>> Time-to-voltage converter VCDU)>> Voltage-controlled delay unit VC-GRO)>> Voltage-controlled gated ring oscillator VCO)>> Voltage-controlled oscillator ZTC)>> Zero temperature coefficient
- 31. 1 1 Introduction to Time-Mode Signal Processing Fei Yuan The rapid scaling of CMOS technology has resulted in the sharp increase of time resolution and the continuous reduction of voltage resolution. As a result, � time-mode circuits where information is represented by the time difference between the occurrences of digital events rather than the nodal voltages or branch currents of electric networks offer a viable and technology-friendly way to reduce scaling-induced performance degradation of mixed-mode systems. This chapter � examines the fundamentals of time-mode circuits. The definition of time-based signal processing is provided in Section 1.1. Section 1.2 examines the characteristics of time-mode circuits and compares them with those of their voltage-mode and current-mode counterparts. Challenges encountered in time- based signal processing are investigated in Section 1.3. Section 1.4 browses through the key building blocks of time-mode circuits. These building blocks include time-to-digital converters (TDCs), � digital-to-time converters (DTCs), time amplifiers, CONTENTS 1.1)>> What Is Time-Mode?.........................................................................................2 1.2)>> Why Time-Mode?..............................................................................................2 1.3)>> Challenges in Time-Mode Signal Processing....................................................4 1.4)>> Building Blocks of Time-Mode Circuits...........................................................5 1.4.1)>> Voltage-to-Time Converters..................................................................5 1.4.2)>> Time-to-Digital Converters...................................................................6 1.4.3)>> Digital-to-Time Converters....................................................................6 1.4.4)>> Time Amplifiers.....................................................................................6 1.4.5)>> Time Quantizers....................................................................................6 1.4.6)>> Time-Mode Arithmetic Units................................................................7 1.5)>> Applications of Time-Mode Signal Processing.................................................7 1.5.1)>> Analog-to-Digital Converters................................................................7 1.5.2)>> All-Digital Phase-Locked Loops...........................................................8 1.5.3)>> All-Digital Frequency Synthesizers......................................................9 1.5.4)>> Time-Based Temperature Sensors.........................................................9 1.6)>>Summary......................................................................................................... 10 References................................................................................................................. 10
- 32. 2 CMOS Time-Mode Circuits and Systems: Fundamentals and Applications time quantizers, and time-mode arithmetic units. Section 1.5 briefly explores the applications of time-based approaches in mixed-mode signal processing. These applications include analog-to-digital converters, phase-locked loops, frequency synthesizers, and temperature measurement. The detailed analysis of these building blocks and applications will be provided in later chapters. The chapter is summarized in Section 1.6. 1.1â•… WHAT IS TIME-MODE? Time-mode circuits depict an analog signal using the difference between the time instants at which two digital events take place. The amount of the time difference is linearly proportional to the amplitude of the analog signal ideally. A time variable is a pulse-width-modulated signal with its pulse width directly proportional to the amplitude of the signal that it represents. A time variable possesses a unique duality characteristic; specifically, it is an analog signal as the continuous amplitude of the analog signal is represented by the duration of the pulse, but, it is also a digital signal as it only has two largely distinct values. The duality of time variables enables them to conduct analog signal processing in a digital environment. This unique character- istic is clearly not possessed by neither analog nor digital variables. Time-mode signal processing deals with addition, multiplication, amplifica- tion, integration, quantization, etc., of time variables. It is interesting to note that Â� time-based signal processing is quite similar to information transmission through the neuron systems of human brains [1]. Since information to be processed by time- mode circuits is represented by the time difference of digital signals, these circuits are essentially digital systems that perform analog and mixed analog–digital signal processing without using power-greedy and speed-impaired digital signal processors. 1.2â•… WHY TIME-MODE? The advancement of CMOS technology is always geared toward optimizing the performance of digital systems. As a result, CMOS analog circuits are continu- ously losing the benefits of specialized and process-controlled components critical to the performance of these circuits. In addition, they must also cope with a rapidly decreasing voltage headroom, that is, the difference between the given supply volt- age of a circuit and the minimum supply voltage of the circuit required for MOS transistors to operate in saturation, caused by the slow decline of the device thresh- old voltage and the aggressive reduction of the supply voltage while meeting ever- stringent performance specifications [2–4]. The shrinking voltage headroom not only limits the maximum achievable signal-to-noise ratio (SNR), it also signifies that the effect of the nonlinear characteristics of MOS devices subsequently reduces the dynamic range of voltage-mode circuits. Further, technology scaling raises the thermal noise floor quantified by kT/C where k is Boltzmann’s constant, T is tem- perature in Kelvin, and C is the minimum capacitance. As a result, the accuracy of voltage-mode circuits, loosely defined as the ratio of the minimum detectable volt- age, typically set by the noise floor, to the maximum available voltage headroom, scales poorly with technology.
- 33. 3 Introduction to Time-Mode Signal Processing Current-mode approaches where analog information to be processed is represented by the branch current of electric networks offer an alternative means to cope with the challenges induced by the dropping voltage headroom. These circuits achieve a low nodal voltage swing by lowering the impedance of nodes. The existence of low-impedance nodes throughout current-mode circuits, however, gives rise to large branch currents. As a result, current-mode circuits typically consume more power as compared with their voltage-mode counterparts. Lowering the power consumption of current-mode circuits while meeting other design constraints at the same time is rather difficult [5]. The characteristics of the low-impedance nodes of current-mode circuits, on the other hand, offer an intrinsic advantage of a low time constant at every node of the circuits. As a result, current-mode circuits are suitable for applica- tions where speed rather than power consumption is most critical. These applications include high-speed serial links, current-steering logic, and current-mode arithmetic units such as current-mode adders in decision feedback equalization (DFE), to name a few. Since voltages and currents are inherently related to each other via impedance or conductance, the characteristics of voltage-mode circuits and current-mode cir- cuits do not differ fundamentally. As a result, the performance of both circuits does not scale well with technology. Although the detrimental effect of technology scaling on the performance of ana- log circuits, regardless of whether they are voltage-mode or current-mode, can be compensated to some extent using digitally assisted means, such as digitally tuned resistor arrays for the calibration of impedance matching of serial links, digitally tuned capacitor arrays or current arrays for the cancellation of the offset voltage of comparators, and digitally tuned capacitor arrays for the coarse frequency tuning of oscillators; these approaches are costly both in terms of silicon and power consump- tion as the switching transistors in these digital networks must be sufficiently large in order to minimize the effect of the channel resistance of these switches. The addi- tion of digitally assistance blocks also has a negative impact on the performance of analog circuits such as increasing the capacitance of the critical nodes through which high-frequency signals propagate. On top of that, the performance of voltage-mode analog or mixed analog-digital circuits continues to decline with technology scaling, further demanding for more digitally assisted compensation. The intrinsic gate delay of digital circuits, on the other hand, has been the primary beneficiary of technology scaling. The improved switching characteristics of MOS tran- sistors offer an excellent timing accuracy such that the time resolution of digital circuits has well surpassed the voltage resolution of analog circuits implemented in nanoscale CMOS technologies. “In a deep-submicron CMOS process, the time-domain resolu- tion of a digital signal edge transition is superior to the voltage resolution of an analog signal” as stated by Dr. R. Staszewski [6]. Time-mode approaches where information is represented by the difference between the time instants at which digital events take place rather than the nodal voltages or branch currents of electric networks offer a new means to neutralize the scaling-induced challenges that once seemed unconquerable. Since time-mode circuits perform analog signal processing in the digital domain, not only the performance of these circuits scales well with technology, time-mode circuits also offer a number of attractive characteristics including full programmability, the ease of portability, low-power consumption, and high-speed operation.
- 34. 4 CMOS Time-Mode Circuits and Systems: Fundamentals and Applications As information to be processed by time-mode circuits is represented by the time difference between the occurrence of digital events, time-mode circuits are essen- tially digital circuits. The detrimental effect of technology scaling on the perfor- mance of voltage-mode or current-mode analog signal processing disappears in time-mode circuits. Time-mode circuits are less sensitive to interferences such as cross talk, switching noise, and substrate coupling, which have a severe impact on the performance of voltage-mode or current-mode circuits. The full programmability of time-mode circuits, attributable to their digital real- ization, allows them to be deployed in a broad spectrum of applications where tun- able characteristics are mandatory. If voltage-mode or current-mode circuits are used in these applications, complex digitally assisted tuning mechanisms will be required. In addition to programmability, portability is of a critical importance in order to minimize design turn-around time. The digital nature of time-mode circuits allows them to be migrated from one generation of technology to another with the mini- mum design time, subsequently lowering the cost. As the intrinsic gate delay of digital circuits benefits the most from technology scaling, time-mode circuits are capable of carrying out rapid signal processing. For example, the oscillation frequency of ring oscillators implemented in state-of-the-art CMOS technologies has reached tens of GHz. Voltage-controlled oscillator (VCO)- based multibit quantizers can provide a large oversampling ratio while consuming a small amount of power. It is evident from the preceding experiment that time-based signal processing has many desirable characteristics such as excellent scalability with technology, good immunity from interferences and imperfections, full programmability, the ease of portability, low-power consumption, and high-speed operation. All are vital to mixed analog-to-digital signal processing and all are not possessed by either voltage- mode or current-mode circuits. 1.3â•… CHALLENGES IN TIME-MODE SIGNAL PROCESSING Although time-based signal processing possesses a number of critical advantages as compared with its voltage-mode or current-mode counterparts, a number of stiff challenges are yet to be overcome in order for time-mode circuits to be deployed in a broad range of applications. In this section, we briefly examine these challenges. Although the intrinsic gate delay of digital circuits benefits the most from technol- ogy scaling, device mismatch arising mainly from process spread deteriorates with technology scaling. In order to minimize the effect of device mismatch, minimum- sized unit delay cells should be avoided. This inevitably has a detrimental impact on the speed and subsequently on the resolution of time-mode circuits. As most time-mode circuits are built upon basic delay cells, such as static CMOS inverters and current-starved CMOS inverters, the propagation delay of these delay cells is a strong function of supply voltage fluctuation. In design of analog circuits, cascode is a convenient, economical, and effective means to minimize the effect of a fluctuating supply voltage. For time-mode circuits, delay-locked loops (DLLs) are widely used to minimize the effect of process, supply, and temperature (PVT)
- 35. 5 Introduction to Time-Mode Signal Processing variations on the delay of delay lines. Although DLLs can be conveniently used to stabilize the delay of the delay lines, it is difficult to use them to minimize the effect of PVT on the delay of the logic gates that are often also part of time-mode circuits and control the operation of time-mode circuits. For example, in cyclic ver- nier TDCs, the delay of the control logic gates has to be made negligibly small as compared with that of the delay cells in order to minimize their effect. Perhaps one of the stiffest challenges in time-based signal processing is the design of time-mode arithmetic units, especially time integrators. The accumulation of a variable in the voltage domain can be conveniently realized by representing the variable as a current and integrating the current onto a capacitor. The voltage of the capacitor gives the result of the integration v t C i d c c t ( ) ( ) = ò 1 0 t t Withholding or storing a time variable is rather difficult due to the irretrievable nature of time. In contrast, a voltage-mode analog variable can be conveniently stored indefinitely using a capacitor if the leakage of the capacitor is negligible. A voltage-mode discrete variable can be stored even more conveniently using a latch. Time registers that store time variables and read out the stored time variables upon the arrival of a readout command become critical. 1.4â•… BUILDING BLOCKS OF TIME-MODE CIRCUITS A complex analog circuit is typically constructed from a set of building blocks such as common-source amplifiers, common-gate amplifiers, common-drain amplifiers (source followers), cascode amplifiers, and differentially configured amplifiers, to name a few. Similarly, a time-based signal-processing system is made of a set of build- ing blocks that perform tasks such as interfacing with voltage-mode and current-mode circuits, time amplification, time arithmetic operations, time quantization, time-to- digital, and digital-to-time conversion. We briefly browse through them in this section. A detailed examination of these building blocks will be provided in later chapters. 1.4.1â•… Voltage-to-Time Converters One of the key building blocks of time-mode circuits is voltage-to-time converters (VTCs) that map a voltage to a time variable. A VTC serves as a gateway bridging voltage-mode and time-mode domains. The most important performance indicators of VTCs are linearity and conversion gain. As time-mode circuits are digital circuits, the linearity of a time-mode system is largely dominated by that of its VTC. The dynamic range of a delay-line TDC is lower-bound by the per-stage time delay and upper-bound by the total delay of the delay line of the TDC. Since the former scales well with tech- nology, the resolution of a time-mode system is largely determined by the conversion gain of VTCs. The higher the conversion gain, the better is the resolution.
- 36. 6 CMOS Time-Mode Circuits and Systems: Fundamentals and Applications 1.4.2â•…Time-to-Digital Converters TDCs map a time variable to a digital code. The deployment of TDCs in nuclear sci- ence research dates back to 1970s [7,8]. The application of TDCs has extended well beyond nuclear science to digital storage oscillators [9,10], laser range finders [11], and digital frequency synthesizers [12], to name a few. Similar to analog-to-digital converters, the performance of TDCs is quantified by a number of parameters such as SNR and signal-to-noise-plus-distortion ratio (SNDR) for noise-shaping TDCs, and differential nonlinearity (DNL) and integral nonlinearity (INL) for sampling TDCs. To compare the performance of TDCs of different architectures, the amount of the power consumption per conversion step of TDCs is the most widely used figure-of-merit (FOM). 1.4.3â•… Digital-to-Time Converters The opposite of time-to-digital conversion is digital-to-time conversion. DTCs map a digital code to a time variable. A digital-to-time operation is needed in applications such as time-mode successive approximation TDCs. A DTC assumes a similar role as that of a digital-to-analog converter in voltage-mode successive approximation analog-to-digital converters (ADCs) or multibit ΔΣ modulators to establish negative feedback. 1.4.4â•…Time Amplifiers Similar to a voltage amplifier that amplifies a voltage, a time amplifier amplifies a time variable. Time amplification is often needed in applications such as the precision measurement of the width of a narrow pulse where the pulse width is often too small to be quantized accurately. Time amplification can also be employed for accurately quantizing the output of TDC-based phase detectors in the vicinity of the lock state so as to establish a precision phase lock. Time amplifiers play a pivotal role in improving the resolution of time-mode circuits. Similar to voltage amplifiers, the gain and lin- earity of time amplifiers are the most important design specifications. For high-speed time digitization, the bandwidth of time amplifiers is also of a great importance. 1.4.5â•…Time Quantizers A single-bit voltage quantizer maps a voltage to a Boolean variable by comparing it with a reference voltage. Similarly, a single-bit time quantizer maps a time vari- able to a Boolean output by comparing it with a time reference. Time quantizers can be realized using a time comparator with the time reference with which the input compares coming from a voltage-controlled oscillator (VCO) of a constant frequency. To conduct the multibit quantization of a time variable, the time variable can be used as a gating signal to activate or deactivate a multistage ring oscillator of a constant oscillation frequency, known as gated ring oscillator (GRO). Since the number of the oscillation cycles of the oscillator and the output of each stage of the oscillator uniquely correspond to the duration of the gating signal, a multibit
- 37. 7 Introduction to Time-Mode Signal Processing time quantizer can be constructed. GRO-based multibit time quantizers offer the intrinsic advantage of first-order noise-shaping. In addition, as compared with voltage-mode multibit quantization, which requires a total of 2N voltage compara- tors where N is the number of quantization bits, VCO-based multibit time quanti- zation offers the advantage of low-power consumption, fast quantization resulting in a large oversampling ratio (OSR), good linearity, first-order noise-shaping, and all-digital realization. 1.4.6â•…Time-Mode Arithmetic Units Time-mode arithmetic units such as time adders and time integrators are critically needed in time-based signal processing. The accumulation of a variable in the volt- age domain can be realized by representing the variable as a current and integrating the current onto a capacitor, that is, v t C i d c c t ( ) ( ) = ò 1 0 t t The resultant voltage of the capacitor is the integration of the variable. Similarly, the accumulation of a variable in the current domain can be implemented by representing the variable as a voltage and integrating the resultant voltage onto an inductor, that is, i t L v d L L t ( ) ( ) = ò 1 0 t t The resultant current of the inductor is the integration of the variable. Withholding a time variable, on the other hand, is rather difficult due to the irretrievable nature of time. Recent work by Hong et al. [13] and Kim et al. [14] has opened the door for time registers and later time integrators, a key component of all-digital ΔΣ modulators. 1.5â•… APPLICATIONS OF TIME-MODE SIGNAL PROCESSING In this section, we briefly browse through some of the key applications of time-based signal processing. These applications include analog-to-digital converters, phase- locked loops, frequency synthesizers, and temperature measurement. An in-depth investigation of them will be given in later chapters. 1.5.1â•…Analog-to-Digital Converters Driven by the benefits of time-mode signal processing, analog-to-digital conversion using time-mode approaches has received a special attention from both academia and industry recently. A key difference between conventional voltage-mode ADCs and time-mode ADCs is the replacement of voltage comparator-based quantiz- ers with VCO-based quantizers as the former suffer from a number of drawbacks including high power consumption especially for multibit quantization and the need
- 38. 8 CMOS Time-Mode Circuits and Systems: Fundamentals and Applications for digitally assisted mismatch compensation. Unlike voltage comparator-based quantizers, in VCO-based quantization, the voltage to be quantized is the control voltage of the VCO. Since for each control voltage, there exists a corresponding oscillation frequency of the oscillator, the number of the cycles of the oscillator within the duration in which the input voltage is held and the output of the delay stages of the oscillator at the end of the sample-and-hold interval of the control volt- age provide the digital representation of the control voltage. VCO-based quantizers offer a number of attractive intrinsic advantages including built-in first-order noise- shaping, inherent multibit quantization with a good linearity, fast quantization sub- sequently a large over-sampling ratio, low-power consumption, and full scalability with technology. Architecturally, time-mode ADCs can be loosely categorized into open-loop ADCs and closed-loop ADCs. The former perform analog-to-digital conversion in an open-loop fashion, while the latter utilize negative feedback to improve perfor- mance, in particular, to suppress the effect of nonlinearities in the forward path of the feedback loop and in-band noise through the noise-shaping of the quantization noise. Open-loop time-mode ADCs offer the advantages of rapid conversion. They, however, suffer from a small dynamic range largely due to in-band harmonics and a high level of in-band quantization noise. Although closed-loop time-mode ADCs provide a better SNDR as compared with their open-loop counterparts, a high-order operational amplifier (op-amp)-based voltage-mode integrator is still needed in the forward path in most recent designs in order to have an adequate loop gain to suppress the effect of the nonlinearities and quantization noise. These ADCs are therefore not all-digital. As a result, their performance does not scale naturally with technology. As the performance of voltage-mode integrators scales poorly with tech- nology, time integrators with a large in-band gain are critically needed for all-digital time-mode ADCs. 1.5.2â•…All-Digital Phase-Locked Loops Similar to analog-to-digital converters, phase-lock loops are another key building block of mixed analog-digital systems. In a phase-locked loop, a low-pass loop filter with large capacitors is typically needed to filter out high-frequency components of the control voltage of the VCO so as to minimize spurs and improve phase noise performance. The programmability constraint also demands that the loop bandwidth of the phase-locked loop be tunable. It is therefore highly desirable to have the loop filter realized digitally in order to reduce silicon cost and provide programmability. In a conventional phase-locked loop with a linear phase detector, the phase differ- ence between the input reference and the output of the VCO is represented by a pulse obtained using a phase detector with pulse width proportional to the phase difference. The resultant pulse is then converted to an analog signal, specifically the control voltage of the oscillator of the phase-locked loop, using both a charge pump and a low-pass loop filter. The power consumption of the charge pump typically constitutes a large portion of the overall power consumption of the phase-locked loop. This is because in order for the phase-locked loop to provide an adequate and timely correction, the current of the charge pump must be sufficiently large.
- 39. 9 Introduction to Time-Mode Signal Processing One might argue that the same can be achieved by lowering the capacitance of the loop filter. Lowering the capacitance of the loop filter, however, will degrade the ability of the loop filter to filter out high-frequency components present on the con- trol voltage line of the oscillator. It is therefore highly desirable from a low-power consumption point of view to have the charge pump removed. The removal of the charge pump also eliminates the source of reference spurs. As the output of the phase detector is a pulse with its pulse width directly proportional to the phase difference between the input of the phase-locked loop and the output of the VCO, this time variable can be digitized by a TDC. The digital output of the TDC can then be fed to a digital loop filter. As a result, not only power-greedy charge pump and silicon- consuming loop filter are removed, the loop bandwidth can also be made fully pro- grammable. The resultant phase-locked loop is now all-digital and enjoys the full merits of technology scaling. If noise-shaping TDCs are used, the low quantization noise of the TDCs will also improve the overall phase noise of the phase-locked loop. 1.5.3â•…All-Digital Frequency Synthesizers Frequency synthesizers are one of the core subsystems of wireless systems. An all- digital phase-locked loop can be migrated to an all-digital frequency synthesizer by including a frequency divider in the feedback path. Integer-N frequency synthesizers suffer from a large frequency adjustment step dictated by the reference frequency, while fractional-N frequency synthesizers yield a fine frequency resolution but suffer from fractional spurs [15,16]. Randomizing the control bits of the frequency divider widens the output of the frequency divider so that fractional spurs are reduced. This, however, is at the expense of increased in-band noise [17]. To reduce the in-band noise, a noise-shaping ΔΣ modulator with a DC input can be employed to generate the random bits for selecting the modulus of the frequency divider [18]. The noise- shaping characteristics of the ΔΣ modulator ensure a low level of in-band quantiza- tion noise is achieved by moving the excessive quantization noise to high frequencies outside the signal band, which can be removed effectively by the loop dynamics [19,20]. The recent architecture of all-digital frequency synthesizers places a TDC in the feedback path [6,21]. The TDC performs frequency division. The removal of an explicit frequency divider in the feedback path and its associated performance enhancement blocks such as ΔΣ modulators not only greatly simplifies synthesizers, it also eliminates the source of fractional spurs [20,22,23]. 1.5.4â•…Time-Based Temperature Sensors Integrated temperature sensors are very important in applications such as medical implants, smart sensors for environment monitoring, and on-chip temperature moni- toring of VLSI (very-large-scale integration) systems, to name a few. Traditionally, integrated temperature sensors are manufactured using a temperature-dependent voltage-mode circuit whose output voltage is a linear function of temperature, a temperature reference circuit whose output voltage is independent of temperature and whose temperature set point can be adjusted, and a voltage comparator that compares the output voltage of the temperature-dependent circuit and that of the
- 40. 10 CMOS Time-Mode Circuits and Systems: Fundamentals and Applications temperature reference circuit. The continuous dip in supply voltage greatly reduces the resolution of voltage-mode circuits, making it very difficult to improve the mea- surement accuracy of these temperature sensors. Temperature can be measured by comparing the frequency of a PTAT (propor- tional to absolute temperature) oscillator whose frequency is proportional to tempera- ture with that of a reference oscillator whose frequency is independent of temperature [24–26]. Alternatively, one can first convert temperature to a pulse with pulse width proportional to temperature and then digitize the width of the resultant pulse using a low-power TDC such as a pulse-shrinking TDC. The removal of oscillators greatly lowers the power consumption, making TDC-based temperature sensors particularly attractive in low-power-requiring applications [12,27]. A time-mode integrated tem- perature sensor can also be realized using a temperature-dependent delay line whose delay is a linear function of temperature, a temperature reference line whose delay is independent of temperature and can be adjusted by changing its temperature set- point, and a time comparator that discriminates the delay of the two delay lines. For a given temperature, the delay of the temperature reference can be made identical to that of the temperature-dependent delay line by digitally adjusting the delay of the temperature reference, that is, the temperature set point of the temperature reference line. Once this occurs, the digital code for adjusting the temperature set point of the temperature reference line gives the digital representation of the temperature [28,29]. 1.6â•…SUMMARY In this chapter, we briefly examined technology scaling-induced challenges encoun- tered in design of voltage-mode or current-mode circuits for mixed-mode signal processing. We showed that although technology scaling results in a reduced volt- age accuracy, which leads to the deteriorating performance of both voltage-mode and current-mode circuits, it sharply improves the switching accuracy of digital circuits at the same time. As a result, the performance of time-based signal process- ing not only scales well with technology, it also surpasses that of voltage-mode or current-mode circuits. The challenges encountered in design of time-mode circuits such as device mismatches, PVT effect, and the storage of time-mode variables were explored. The key building blocks of time-mode circuits including VTCs, TDCs, DTCs, time amplifiers, time quantizers, and time-mode arithmetic units were examined briefly. The applications of time-mode circuits in analog-to-digital converters, phase-locked loops, frequency synthesizers, and temperature measure- ment were briefly explored. REFERENCES )>> 1.)>>V. Ravinuthula, V. Garg, J. Harris, and J. Fortes. Time-mode circuits for analog com- putation. International Journal of Circuit Theory and Applications, 37:631–659, 2009. )>> 2.)>>G. Shahidi. Challenges of CMOS scaling at below 0.1 μm. In Proceedings of International Microelectronics Conference, 2000, Tehran, pp. 5–8. )>> 3.)>> R. Gera and D. Hoe. An evaluation of CMOS adders in deep sub-micron processes. In Proceedings of Southeastern Symposium on System Theory, 2012, Jacksonville, FL, pp. 126–129.
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- 42. 12 CMOS Time-Mode Circuits and Systems: Fundamentals and Applications )>> 23.)>>E. Temporiti, C. Wu, D. Baldi, R. M. Cusmai, and F. Svelto. A 3.5 GHz wideband ADPLL with fractional spur suppression through TDC dithering and feed-forward compensation. IEEE Journal of Solid-State Circuits, 45(12):2723–2736, 2010. )>> 24.)>>S. Zhou and N. Wu. A novel ultra low power temperature sensor for UHF RFID tag chip. In Proceedings of IEEE Asian Solid-State Circuits Conference, November 2007, Jeju, Korea, pp. 464–467. )>> 25.)>> C. Kim, B. Kong, C. Lee, and Y. Jun. CMOS temperature sensor with ring oscillator for mobile DRAM self-refresh control. In Proceedings of IEEE International Symposium on Circuits and Systems, May 2008, Seattle, WA, pp. 3094–3097. )>> 26.)>>S. Park, C. Min, and S. Cho. A 95 nW ring oscillator-based temperature sensor for RFID tags in 0.13 μ m CMOS. In Proceedings of IEEE International Symposium on Circuits and Systems, May 2009, pp. 1153–1156. )>> 27.)>>P. Chen, C. Hwang, and W. Chang. A precise cyclic CMOS time-to-digital converter with low thermal sensitivity. IEEE Transactions on Nuclear Science, 52(4):834–838, August 2005. )>> 28.)>>P. Chen, T. Chen, Y. Wang, and C. Chen. A time-domain sub-micro watt temperature sensor with digital set-point programming. IEEE Sensors Journal, 9(12):1639–1646, 2009. )>> 29.)>> P. Chen, C. Chen, Y. Peng, K. Wang, and Y. Wang. A time-domain SAR smart tempera- ture sensor with curvature compensation and a 3 σ inaccuracy of 0.4°C–0.6°C over a 0°C to 90°C range. IEEE Journal of Solid-State Circuits, 45(3):600–609, March 2010.
- 43. 13 2 Voltage-to-Time Converters Fei Yuan One of the key building blocks of time-mode systems for processing analog signals is voltage-to-time converters (VTCs) that map a voltage to a time variable with its value directly proportional to the amplitude of the voltage. Although VTCs can be realized using complex circuits to achieve good performance such as a large conver- sion range and a good linearity, operational amplifiers whose performance scales poorly with technology are often required [1–3]. As time-mode circuits are digi- tal circuits, the linearity of a time-mode system that processes analog quantities is largely dominated by that of its VTC. VTCs whose performance scales well with technology are critical to time-based signal processing. This chapter deals with VTCs with an emphasis on the techniques that improve the linearity of the converters. The chapter is organized as follows: Section 2.1 inves- tigates VTCs implemented using the voltage-controlled delay units (VCDUs). VTCs using VCDUs and source degeneration are discussed in Section 2.2. Section 2.3 looks into relaxation voltage-to-time converters. Reference VTCs are examined in Section 2.4. The applications of VTCs in time-mode comparators are investigated in Section 2.5. The chapter is summarized in Section 2.6. 2.1â•… VCDU VOLTAGE-TO-TIME CONVERTERS A voltage can be mapped to a time variable using the VCDU shown in Figure 2.1 [4–11]. The VCDU consists of a current-starved inverter, that is, a static inverter with its charging or discharging current controlled by a current source, a load capacitor, and a static inverter. The load capacitor should be linear and its capaci- tance should be much larger as compared with the capacitances of the transistors such that the effect of the nonlinearity of the device capacitances is negligible as CONTENTS 2.1)>> VCDU Voltage-to-Time Converters................................................................13 2.2)>> VCDU Voltage-to-Time Converters with Source Degeneration......................19 2.3)>> Relaxation Voltage-to-Time Converters..........................................................21 2.4)>> Reference Voltage-to-Time Converters...........................................................23 2.5)>> Time-Mode Comparators................................................................................24 2.6)>>Summary.........................................................................................................30 References.................................................................................................................30
- 44. 14 CMOS Time-Mode Circuits and Systems: Fundamentals and Applications compared with that of the load capacitor. The current-starved inverter is clocked by a periodic signal ϕ that presets the VCDU prior to a conversion operation. In the precharge phase where ϕ is low, the load capacitor is precharged to VDD and the output of the static inverter is set to logic-0. The input voltage vin is sampled by Cin. In the following discharge phase where ϕ = 1, the load capacitor is dis- charged by the current of M3 whose value is set by the input voltage vin(kT) at the end of the precharge phase. The voltage of the gate of M3 is kept unchanged during the discharge phase and so is the discharge current of the load capacitor. As a result, the voltage of the capacitor C decreases linearly with time. When vc drops below the threshold voltage VT,inv of the following static inverter, vo will be set to logic-1. The value of the resultant time variable Tin, which is measured from the time instant at which ϕ = 1 to the time instant at which vc is submerged by the threshold voltage of the inverter, is given by T kT C i kT V V in DS DD T inv ( ) ( ) , , = - ( ) 3 (2.1) where VDD is the supply voltage iDS3(kT) is the channel current of M3 in kth period and is given by i kT k v kT V v DS n in T DS 3 3 2 3 1 ( ) ( ) , = - é ë ù û + ( ) l (2.2) M1 M2 M3 vin vc vo vc vo VDD VT,inv vG3 kT vin(kT) M4 C Precharge Sampling (k+1)T vin[(k+1)T] Tin(kT+T) Tin(kT) t t t t Cin FIGURE 2.1â•… Voltage-to-time converter using voltage-controlled delay cells.
- 45. 15 Voltage-to-Time Converters where k C W L n n ox 3 3 1 2 = æ è ç ö ø ÷ m , (2.3) where μn is the surface mobility of free electrons Cox is gate-oxide capacitance per unit area W3 and L3 are the width and length of M3, respectively VT is the threshold voltage of MOSFETs λ is the channel-length modulator constant vDS3 is the drain-source voltage of M3 For simplicity, we assume that NMOS and PMOS transistors have the same thresh- old voltage, that is, VTn = |VTp| = VT. Substituting Equation 2.2 into Equation 2.1 yields T kT C V V k v kT V v in DD T inv n in T DS ( ) ( ) ( ) . , = - - é ë ù û + ( ) 3 2 3 1 l (2.4) It is observed from Equation 2.4 that for each vin(kT), there is a corresponding Tin(kT). The need for the sample-and-hold operation of vin becomes apparent. Also it is observed from Equation 2.4 that the relation between Tin and vin is inherently nonlinear. Further, not only is Tin set by vin, Tin also varies with vc as vc = vDS2 + vDS3 ≈ vDS3, further signifying the effect of the nonlinearity of the transconductance. Figure 2.2a shows the dependence of Tin on the input voltage of Figure 2.1. The nonlinear characteristic observed in the figure is consistent with our findings in the investigation of the nonlin- ear relation between Tin and vin. As can be seen, an excessive amount of delay exists when the input voltage is low. Also, linearity improves when the input voltage is large. To improve the performance, an additional transistor M4 can be added in paral- lel with M3, as shown in Figure 2.1 [12–14]. To understand the effect of M4, let us examine its mode of operation. To ensure that M4 is in triode, vDS4 < vGS4 − VT is required. This translates to vc < VDD − VT. In the precharge phase where ϕ = 0, we have vc = VDD. In the discharge phase where ϕ = 1, the load capacitor is discharged through M3 with part of the discharge current controlled by the input and the other part set by M4. If VDD − VT < vc, M4 will be in saturation. It will be in triode if vc < VDD − VTâ•›. We use the typical parameters of a 130 nm CMOS technology as an example to exemplify the region of the operation of M4. Since for a typical 130 nm CMOS technology, VDD = 1.2 V and VT ≈ 0.4 V, M4 will be in saturation if vc < 0.8 V and in triode if vc < 0.8 V. It is evident from Equation 2.1 that since the discharge current of the load capacitor consists of both the channel current of M3, which is set by vin, and the channel current of M4, which is independent of vin, we have T kT C i kT i kT V V in DS DS DD T inv ( ) ( ) ( ) . , = + - ( ) 3 4 (2.5)
- 46. 16 CMOS Time-Mode Circuits and Systems: Fundamentals and Applications It is seen from Equation 2.5 that when iDS3(kT) ≪ iDS4(kT), T kT C i V V in DS kT DD T inv ( ) . ( ) , » - ( ) 4 (2.6) Also, when iDS3(kT) ≫ iDS4(kT), T kT C i kT V V in DS DD T inv ( ) ( ) . , » - ( ) 3 (2.7) Since hyperbolic function f(x) = 1/x exhibits a good linearity if x ≪ 1 or x ≫ 1 and a poor linearity in the neighborhood of x = 1, the addition of M4 improves the linearity of Tin when iDS3 is small. When iDS3 is large, a better linearity is also obtained. This is evident in Figure 2.2b where the dependence of the time delay on the input voltage of Figure 2.1 with M4 added is shown. When iDS3 is small, Tin is dominated by iDS4, the dependence of Tin on iDS3 is reduced, so is the conversion gain. The larger iDS4, the worse is the loss of the conversion gain. To further improve the linearity, a differentially configured VTC consisting of two identical single-ended VTCs of Figure 2.1 can be used, as shown in Figure 2.3 [15]. To demonstrate the improvement of linearity, we neglect the effect of channel length modulation and assume a perfect match between the two transconductors 40 30 20 10 0.45 0.5 0.55 Vin (V) (a) (b) 0.6 0.65 0.7 0.3 Delay (ns) 0.35 0.4 Delay (ns) 0.45 0.5 0.55 Vin (V) 0.6 0.65 0.7 0.3 7 8 12 11 10 9 0.35 0.4 FIGURE 2.2â•… Dependence of the delay of VCDU of Figure 2.1 implemented in an 130 nm CMOS technology. (a) Without M4. (b) With M4.
- 47. 17 Voltage-to-Time Converters forming the differential configuration. Let v V v in in + = + D and v V v in in - = - D where Δv denotes the variation of vin from its nominal value Vin. From Equation 2.4, we have D D T kT T kT T kT C V V k v v kT V in in in DD T inv n in ( ) ( ) ( ) ( ) ( ) ( ) , = - = - - - + - 3 4 T T in T v kT V v [ ] [ ] - - { } ( ) ( ) . 2 2 2 D (2.8) If (Δv)2 is negligibly small as compared with [Vin(kT) − VT]2, we have D D T kT C V V k v kT V v in DD T inv n in T ( ) ( ) ( ) . , » - - - é ë ù û ì í ï î ï ü ý ï þ ï 4 3 3 (2.9) It is seen from Equation 2.9 that as long as Δv ≪ Vin − VT, a linear relation between ΔTin and Δv will exist. It should be emphasized that the relation between Tin and vin given by Equation 2.4 is nonlinear, while that between ΔTin and Δv given by Equation 2.9 is linear. Another approach to improve the linearity is to use the symmetrical load pro- posed by Maneatis in [16], as shown in Figure 2.4a [17]. Although voltage-to-cur- rent conversion is solely carried out by M3, the addition of diode-connected M4 improves the linearity of ic ~ vc relation, as illustrated graphically in Figure 2.4c. It should be noted that since the discharge current should be solely set by the input, vo + vc + vc – vo – v– in v+ in vin vo VDD VT,inv kT (k+1)T v+ in[(k+1)T] t v+ in(kT) v– in(kT) v– c v+ c v– in[(k+1)T] T– in(kT) ΔTin(kT) T+ in(kT) ΔTin(kT +T) FIGURE 2.3â•… Voltage-to-time converter using differential voltage-controlled delay cells. (From Macpherson, A. et al., A 5 GS/s 4-bit time-based single-channel CMOS ADC for radio astronomy, Proceedings of IEEE Custom Integrated Circuit Conference, 2013, pp. 1–4.)
- 48. 18 CMOS Time-Mode Circuits and Systems: Fundamentals and Applications the dependence of ic on vc introduces unwanted distortion. Konishi et al. pointed out that the voltage of the drain of M3 and M4 in Figure 2.4a cannot be fully recovered to the supply voltage when ϕ = 0, resulting in the variation of the propagation delay [18]. This is because when ϕ = 1, although C is fully charged, the charge sharing between C and the parasitic capacitor at the drain of M3 and M4 will result in a dip of vc immediately after ϕ becomes logic-1. To demonstrate this, let the capacitance at the drains of M3 and M4 be CA. Further let the voltage of C and CA be vC(0−) = VDD and vA(0−), respectively, when ϕ = 0. If we neglect the channel resistance of all transistors when they are in triode, then immediately after ϕ = 1, C and CA will have the same voltage, that is, vC(0+) = vA(0+) = v(0+). Using charge conservation, we have C C v CV C v A DD A A + = + ( ) ( ) ( ) + - 0 0 , (2.10) from which we obtain v CV C v C C DD A A A ( ) ( ) . 0 0 + - = + + (2.11) M1 M2 vc vo vin ic C CA M3 M4 (a) M2 M3 vc vin vo M1 C (b) ic ic vin vc iDS4 iDS3 (c) FIGURE 2.4â•… (a) Voltage-to-time converter. (From Taillefer, C. and Roberts, G., IEEE Trans. Circuits Syst. I, 56(9), 1908, 2009.) (b) Voltage-to-time converter. (From Konishi, T. et al., A 40-nm 640-μm2 45-dB opampless all-digital second-order MASH ΔΣ ADC, in Proceedings of IEEE International Symposium on Circuits and Systems, 2011, pp. 518–521.)
- 49. 19 Voltage-to-Time Converters The instantaneous change of vc immediately after ϕ = 1 is evident in Equation 2.11. Equation 2.11 also reveals that if C ≫ CA, then the effect of charge sharing will be negligible. The modified VTC shown in Figure 2.4b eliminates this drawback. 2.2â•… VCDU VOLTAGE-TO-TIME CONVERTERS WITH SOURCE DEGENERATION It is well understood that negative feedback improves linearity [19]. To improve the linearity of the preceding VCDU, negative feedback formed by the source degeneration shown in Figure 2.5a can be used [20]. Source degeneration is an effective and economical means to improve the linearity of MOS transconductors and is widely used in a broad range of applications such as radio-frequency down- conversion mixers for linearity improvement. The mechanism of source degen- eration on improving the linearity of the MOSFET transconductor can be briefly depicted as follows: When vin rises, vGS3 will rise accordingly. The increase of vGS3 will signify the nonlinear effect of vGS3 ~ iDS3 relation as MOSFETs are inherently nonlinear transconductors and will exhibit a good linearity only when vGS is small. To demonstrate this, we neglect the effect of channel length modulation and let vGS = VGS + vgs where VGS and vgs are the dc and ac components of vGS, respectively. Notice that ) i k V v V I g v k v DS n GS gs T DS m gs n gs 3 3 3 3 2 3 3 3 3 3 2 = + - ( ) = + + , ) (2.12) M1 M2 M3 Rs (a) vs vin C vc vo (b) M1 M2 M3 M4 Rs Cs vin C vc vo FIGURE 2.5â•… Voltage-to-time converter using voltage-controlled delay cells with source degeneration. (a) Without residual charge removal. (From Belloni, M. et al., A voltage-to- pulse converter for very high frequency DC-DC converters, Proceedings of International Symposium on Power Electronics, Electrical Devices, Automation, and Motion, 2008, pp. 789–791.) (b) With residual charge removal. (Agnes, A. et al., Analog Integrated Circuits and Signal Process, 54, 183, 2010.)
- 50. 20 CMOS Time-Mode Circuits and Systems: Fundamentals and Applications where I k V V DS n GS T 3 3 3 2 = - ( ) (2.13) is the dc current of M3, and g k V V m n GS T 3 3 3 2 = - ( ) (2.14) is the transconductance of M3. It is seen from Equation 2.12 that the second-order term can be neglected if vGS3 is small. The increase of vGS3 will give rise to an increase in iDS3, which will in turn boost the voltage of the source of M3. vGS3 will then drop due to the negative voltage feedback provided by the source degeneration resistor Rs. The reduced swing of vGS will improve the linearity of iDS3 ~ vGS3 characteristics. Like any negative feedback, source degeneration reduces the conversion gain. This is the price paid for linearity improvement. In addition to linearity improvement, another added bonus of source degeneration is the improved bandwidth of the transconductor. In fact, source degeneration is a technique widely used to boost the bandwidth of continuous-time linear equalizers in multi-Gbps serial links [21]. To provide a quantitative comparison of the improvement of linearity obtained from source degeneration, we examine the current of the transconductor with and without source degeneration resistor Rs. To simplify analysis, we again neglect the effect of channel length modulation. When Rs is absent, we have i k v V DS n in T 3 3 2 = - ( ) . (2.15) When Rs is present, we have i k v R i V DS n in s DS T 3 3 3 2 = - - ( ) , (2.16) Rearranging Equation 2.16 in the standard quadratic equation of iDS3 k R i k v V R i k v V n s DS n in T s DS n in T 3 2 3 2 3 3 3 2 1 2 0 - + - é ë ù û + - = ( ) ( ) , (2.17) and solving Equation 2.17 for iDS3 yield i k R k v V k v V k R DS n s n in T n in T n 3 3 2 3 3 2 3 2 1 2 1 2 1 2 4 = + - é ë ù û ± + - é ë ù û - ( ) ( ) s s in T v V 2 2 - ( ) . (2.18) It becomes evident from Equation 2.18 that the second-order relation between iDS3 and vin present in Equation 2.15 vanishes in Equation 2.18.
- 51. 21 Voltage-to-Time Converters The residual charge of the parasitic capacitor Cs, which consists of the gate-source capacitance and source-substrate junction capacitance of M3, as well as the parasitic capacitance of Rs, exists at the end of the discharge phase. This is particularly true if the duration of the discharge phase, which is often constrained by sampling rate, is short and the time constant RsCs is large. Note that a large Rs is desired in providing a strong negative feedback, and subsequently the better linearity of the transconductor. As a result, a large source voltage of M3 might exist at the onset of the next discharge phase. This initial voltage sets the lower bound of the gate voltage of M3 to v v V in C T s , ( ) min = + - 0 (2.19) where vCs (0−) is the voltage of Cs at the beginning of the discharge phase. Also, the current of M3 is no longer solely determined by vin but rather by both vin and vCs (0−) i k v v V v DS n in C T DS S 3 3 2 3 0 1 = - - é ë ù û + ( ) - ( ) . l (2.20) The residual charge of Cs can be removed by adding a reset transistor M4 in paral- lel with Rs, as shown in Figure 2.5b [22]. M4 is gated by ϕ. In the precharge phase where ϕ = 0, Cs is fully reset and vs = 0. In the discharge phase where ϕ = 1, the reset operation is disabled so that M4 has no effect on the discharge of the load capacitor. Note that M4 needs to be sufficiently large in order to minimize its ON resistance so that the reset operation can be completed in the precharge phase, that is, (Rs ∥Ron4) Cs should be much smaller as compared with the duration of the precharge phase. A downside of large M4 is the increase of Cs. 2.3â•… RELAXATION VOLTAGE-TO-TIME CONVERTERS The preceding VTCs precharge the load capacitor first and then drain the charge of the capacitor with the current controlled by the input voltage. Alternatively, voltage- to-time conversion can be performed by first charging the load capacitor with the input voltage and then discharging the capacitor with a constant current, as shown in Figure 2.6 [8,11,23,24]. We term these VTCs relaxation VTCs due to their resemblance to the operation of relaxation oscillators. Note that at the onset of the discharge phase, vc Vref must be satisfied. vo is thus at logic-0 initially. The comparator will change its output when vc drops below the reference voltage Vref. The value of the resultant time variable Tin, which is defined from the time instant at which ϕ1 = 0 to the time instant at which vc drops below Vref, depends upon the input voltage vin, the drain current I, and the reference voltage Vref. For a given I in kth period, it can be shown that T kT C I v kT V in in ref ( ) ( ) . = - é ë ù û (2.21) It is evident from Equation 2.21 that Tin(kT) is directly proportional to the sampled value of the input voltage vin(kT).
- 52. 22 CMOS Time-Mode Circuits and Systems: Fundamentals and Applications The residual charge of the load capacitor is removed in the reset phase where ϕ3 = 1. The removal of the residual charge of the sampling capacitor is important as it enables the establishment of an one-to-one mapping between vin and vc in each clock cycle. To demonstrate this, let the ON resistance of MOSFET switches be Ron. Assume that the residual charge of C at the assertion of the sampling phase where ϕ1 = 1 is vc(0−). It is elementary to show that V s V s sR C R Cv sR C c in on on c on ( ) ( ) ( ) . = + + + - 1 0 1 (2.22) If we assume that the input is a unit step, that is, vin = u(t), it can be shown that v t v e e t c c t R C t R C on on ( ) ( ) , . /( ) /( ) = + - é ë ù û ³ - - - 0 1 0 (2.23) It is evident from Equation 2.23 that the effect of vc(0−) will vanish only when t → ∞. Since the period of the clock is finite, the residual charge of C in kth clock cycle will impact the voltage of the capacitor in (k + 1)th clock cycle. The removal of the vin 1 3 vc Vref C I – + vo 2 1 3 vin(kT) Tin(kT) Tin(kT+T) vin(kT+T) t t t t Vref kT (k+1)T (k+2)T vc vo 2 FIGURE 2.6â•… Relaxation voltage-to-time converter. (From Park, M. and Perrott, M., A Â� single-slope 80 Ms/s ADC using two-step time-to-digital conversion, in IEEE International Symposium on Circuits and Systems, 2009, pp. 1125–1128; Min, Y. et al., A 5-bit 500-Ms/s time-domain flash ADC in 0.18 μm CMOS, in Proceedings of IEEE International Symposium on Circuits and Systems, 2011, pp. 336–339; Huang, H. and Sechen, C., A 22 mW 227 MSps 11b self-tuning ADC based on time-to-digital conversion, in Proceedings of IEEE Circuits and Systems Workshop, 2009, pp. 1–4; Mohamad, S. et al., A low power temperature sensor based on a voltage-to-time converter cell, in Proceedings of IEEE International Conference of Microelectronics, 2013, pp. 1–4.)
- 53. 23 Voltage-to-Time Converters residual charge of the sampling capacitor at the end of each clock cycle becomes vital to ensure the one-to-one mapping between vin and vc in each clock cycle. The VCDU-based VTCs in Figure 2.1 perform voltage-to-time conversion in two steps: They first perform voltage-to-current conversion using a transconductor and then current-to-time conversion using a current-starved delay cell. Although the lat- ter exhibits a perfect linearity ensured by both the constant discharge current and the linear load capacitor, the voltage-to-time conversion performed in the first step suffers from a poor linearity. The VTC in Figure 2.6 offers the advantage of a bet- ter linearity as the input voltage vin is sampled by a linear capacitor C directly. No voltage-to-current conversion is performed on vin. Another distinct characteristic of the relaxation VTC is that the gain of the VTC can be adjusted by varying I. For a given vin(kT), the larger the discharge current I, the smaller is the resultant time vari- able and the lower the conversion gain. On the other hand, the larger the discharge current I, the faster is the voltage-to-time conversion. The gain and conversion time of VCDU-based VTCs, however, cannot be adjusted. 2.4â•… REFERENCE VOLTAGE-TO-TIME CONVERTERS The preceding VTC uses a fixed reference voltage with which input-dependent voltage vc compares. Alternatively, one can perform voltage-to-time conversion by making the input voltage vin the reference voltage and the voltage that compares with vin comes from a ramping voltage generator with a constant slope, as shown in Figure 2.7 [25]. We term these VTCs reference VTCs, as the voltage to be converted is now the reference voltage with which the ramping voltage compares. Reference VTCs are also known as pulse-width-modulation generators as they map the ampli- tude of an input voltage to the width of a pulse linearly [26]. vin 1 1 vc C I – + vo 2 1 vin(kT) Tin(kT) Tin(kT+T) vin(kT+T) t t t t kT (k+1)T (k+2)T vc vo 2 FIGURE 2.7â•… Voltage-to-time converter with input the reference voltage. (From Oh, T. and Hwang, I., IEEE Trans. VLSI Syst., 2014.)
- 54. 24 CMOS Time-Mode Circuits and Systems: Fundamentals and Applications The input voltage vin is fed to the noninverting terminal of the comparator. At the assertion of ϕ1 = 1, capacitor C is reset and vin is sampled by the input capacitor of the comparator. The output voltage vo is set to logic-1. When ϕ2 = 1, the capacitor is charged by a constant current I and vc rises linearly with time. When vc exceeds vin(kT), the output of the comparator will change from logic-1 to logic-0. The resul- tant time variable Tin, which is measured from the time instant at which ϕ2 = 1 is asserted to the time instant at which vc exceeds vin(kT), is given by T kT C I v kT in in ( ) ( ). = (2.24) It is evident from Equation 2.24 that Tin(kT) is directly proportional to the sampled input voltage vin(kT). Reference VTCs possess the similar properties as those of relaxation VTCs in Figure 2.6, specifically, a good linearity as no voltage-to-current conversion is per- formed on vin and a tunable conversion gain obtained by adjusting I. In addition, reference VTCs offer an infinite input impedance, an attractive property for many applications. 2.5â•… TIME-MODE COMPARATORS Having investigated VTCs, in this section, we explore the applications of VTCs in time-mode comparators. It is well understood that voltage-mode comparators suffer from a number of drawbacks, in particular, the mismatch-induced offset voltage that deteriorates with technology scaling [27]. To improve the accuracy of voltage-mode comparators, digitally assisted calibration, which is typically power and area hungry, is needed. It was shown by Agnes et al. that voltage-mode comparators can also be implemented first by converting both the input and reference voltages to time vari- ables using VTCs. The resultant time variables are then compared using a single-bit time quantizer, which accepts two time-mode inputs A and B and outputs a logic-1 if A leads B or a logic-0 otherwise. Figure 2.8 shows the schematic of the time-mode comparator proposed by Agnes et al. [22,28]. The waveforms of the critical nodes are sketched in Figure 2.9. The operation of the comparator is briefly depicted here: In the precharge phase where ϕ = 0, both C1 and C2 are fully charged (vc1, vc2 = VDD). M6a and M6b, in the mean time, short the output nodes to the ground (vo1, vo2 = 0). The parasitic capacitors at the nodes of Rs1 and Rs2 are reset by M4a and M4b, respec- tively. In the discharge phase where ϕ = 1, C1 and C2 are discharged with their discharge currents controlled by vin and vref, respectively. Assume in kth discharge phase, vin vref, C1 will be discharged slower than C2 and vc1 vc2 will follow. When vc2 VDD − VT, M5b will turn on. Cout2 will be charged, and vo2 will arise. Similarly, when vc1 VDD − VT, M5a will turn on. Cout1 will be charged, and vo1 will arise. Since vo2 rises first, it will reach the threshold voltage VT,inv of the downstream inverter first. As a result, Clk of the DFF is reset first and Q = 1 is set when Clk = 0. Similarly one can show in (k + 1)th sampling period, Clk will be reset after D = 0 is set. The dura- tion of Q is bordered by the time instants at which by Clk = 0.
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- 56. proud of, but the master's pride must have been obliterated in his emotion when he listened to such a description of his school as this. But the scholar, after all, will leave with a good heart. There is the Word, the sleepless guardian of all men. He puts his trust in him, and in the good seed that his master has sown; perhaps he may come back again and see him yet once more, when the seed shall have sprung up and produced such fruits as can be expected from a nature which is barren and evil, but which he prays God may never become worse by his own fault. And do thou, O my beloved master ( ), arise and send us forth with thy prayer; thou hast been our saviour by thy holy teachings whilst we were with thee; save us still by thy prayers when we depart. Give us back, master, give us up into the hands of him that sent us to thee, God; thank him for what has befallen us; pray him that in the future he may ever be with us to direct us, that he may keep his laws before our eyes and set in our heart that best of teachers his divine fear. Away from thee, we shall not obey him as freely as we obeyed him here. Keep praying that we may find consolation in him for our loss of thee, that he may send us his angel to go with us; and ask him to bring us back to thee once more; no other consolation could be half so great. And so they depart, the two brothers, never again to see their master more. They both became great bishops, Gregory the greatest; we find Origen writing to him, soon after his departure, a letter full of affection and good counsel; and who can tell how much the teaching of the catechist of Alexandria had to do with that wonderful life and never-dying reputation that distinguish Gregory Thaumaturgus among all the saints of the church? {488} Origen presided at Alexandria for twenty years--that is to say, from 211 to 231. In the latter year he left it for ever. During this period he had been temporarily absent more than once. The governor of the Roman Arabia, or Arabia Petraea, had sent a special messenger to the prefect of Alexandria and the patriarch, to beg that the catechist
- 57. might pay him a visit. What he wanted him for is not recorded; but Petra, the capital of the Roman province, was not so far from the great road between Alexandria and Palestine as to be out of the way of Greek thought and civilization, and its interesting remains of art, belonging to this very period, which startled modern travellers only a short time past, prove that it was itself no inconsiderable centre of intellectual cultivation. We may, therefore, conjecture that his errand was philosophical, or, in other words, religious. The second time that Origen was absent from Alexandria was for a somewhat longer space. The emperor Caracalla, after murdering his brother and indulging in indiscriminate slaughter, in all parts of the world from Rome to Syria, had at last arrived, with his troubled conscience and his well-bribed legions, at Alexandria. The Alexandrians, it is well known, had an irresistible tendency to give nicknames. Caracalla's career was open to a few epithets, and the unfortunate men of Macedon made merry on some salient points in the character of the emperor and his mother. They had better have held their tongues, or plucked them out; for in a fury of vengeance he let loose his bloodthirsty bands on the city. How many were slain in that awful visitation no one ever knew; the dead were thrown into trenches, and hastily covered up, uncounted and unrecorded. The spectre-haunted emperor took special vengeance on the institutions and professors of learning. It would seem that he destroyed a great part of the buildings of the Museum, and put to death or banished the teachers. As for the students, he had the whole youth of the city driven together into the gymnasium, and ordered them to be formed into a Macedonian phalanx for his army--a grim retort, in kind, for their pleasantries at his expense. Origen fled before this storm. Had he remained, he was far too well known now to have been safe for an hour. Doubtless obedience made him conceal himself and escape. He took refuge in Caesarea of Palestine, where the bishop, St. Theoctistus, received him with the utmost honor; and, though he was yet only a layman, made him preach in the church, which he had never done at Alexandria. When
- 58. the tempest in Egypt had gone by, Demetrius wrote for him to come back. He returned, and resumed the duties of his post. After this he took either one or two other journeys. He was sent into Greece, and visited Athens, with letters from his bishop, to refute heresy and confirm the Christian religion. He also stayed awhile at the great central see of Antioch. On his journey to Greece, he had been ordained priest at Caesarea, by his friend St. Theoctistus. When he returned to Alexandria, about the year 231, Demetrius, the patriarch, was pleased to be exceedingly indignant at his ordination. We cannot go into the controversy here; we need only say that a synod of bishops, summoned by the patriarch, decreed that he must leave Alexandria, but retain his priesthood; which seems to show that they thought he had better leave for the sake of peace, though they could not recognize any canonical fault; for if they had, they would have suspended or degraded him. Demetrius, indeed, assembled another synod some time later, and did degrade and excommunicate him. But by this time Origen had left Alexandria, never to return {489} and was quietly living at Caesarea. We dare not pronounce sentence in a cause that has occupied so many learned pens; but we dare confidently say this, that it is impossible to prove Origen to have been knowingly in the wrong. We must now follow him to Caesarea. If some Levantine merchantman, manned by swarthy Greeks or Syrians, in trying to make Beyrout, should be driven by a north wind some fifty miles further along the coast to the southwest, she might possibly find herself, at break of day, in sight of a strange-looking harbor. There would be a wide semi-circular sweep of buildings, or what had once been buildings; there would be a southern promontory, crowned with a tower in ruins; there would be the vestiges of a splendid pier; and there would be rows of granite pillars lying as if a hurricane had come off the land, and blown them bodily into the sea. An Arab or two, in their white cotton clothes, would be grimly looking about them, on some prostrate columns;
- 59. and a stray jackal, caught by the rising sun, would be scampering into some hole in the ruins. Our merchantman would have come upon all that is left of Caesarea of Palestine. If she did not immediately make all sail to Jaffa, or back to Beyrout, it would not be because the place does not look ghostly and dismal enough. And yet it was once the greatest port on that Mediterranean coast, and far more important than either Jaffa, Acre, Sidon, or even Beyrout now. It owed its celebrity to Herod the Great. Twelve years of labor, and the expenditure of vast sums of money, made the ancient Turris Stratonis worthy to be rechristened Caesarea, in honor of Caesar Augustus. Its great pier, constructed of granite blocks of incredible size, afforded at once dwelling-places and hostelries for the sailors and a splendid columned promenade for the wealthy citizens. The half-circle of buildings, all of polished granite, that embraced the sea and the harbor, and terminated in a rocky promontory on either side, shone far out to sea, and showed conspicuous in the midst the great temple of Caesar, crowned with statues of Augustus and of the Roman city. An agora, a praetorium, a circus looking out to sea, and a rock-hewn theatre, were included in Herod's magnificent plans, and fittingly adorned a city that was to become in a few years the capital of Palestine. We see its importance even as early as the days immediately after Pentecost. It was here that the Gentiles were called to the faith, in the person of Cornelius the centurion, a commander of the legionaries stationed at Caesarea. His house, three hundred years later, was turned into a chapel by St. Paulo, and must therefore have been recognizable at the time of which we write. It was here that Herod Agrippa I. planned the apprehension of St. Peter and the execution of St. James the Greater; and it was in the theatre here that the beams of the sun shone upon his glittering apparel, and the people saluted him as a god, only to see him smitten by the hand of the true God, and carried to his palace in the agonies of mortal pain. St. Paul was here several times, and last of all when he was brought from Jerusalem by the fifty horsemen and the two hundred spearmen. Here he was examined before Felix, and before Festus, in the presence of King Agrippa, when he made his celebrated speech; and it was from the harbor of Caesarea that he
- 60. sailed for Rome to be heard before Caesar. For many centuries, even into the times of the crusaders, it continued to be a capital and haven of great importance. Between 195 and 198, it was the scene of one of the earliest councils of the Eastern Church, and, as the see of Eusebius, the founder of church history, and the site of a celebrated library, it must always be interesting in ecclesiastical annals. But perhaps it would require nothing more to make {490} it a place of note in our eyes than the fact that when Origen was driven from Alexandria, in 231, he transferred to Caesarea not the Alexandrian school, it is true, but the teacher whose presence and spirit had contributed so much to make it immortal. Caesarea, indeed, was at that time a literary centre only second to Alexandria or Antioch. It was in direct communication with Jerusalem by an excellent military road, and with Alexandria by a road that was longer, indeed, but in no way inferior. It was not far from Berytus both by land and sea. Like Capharnaum and Ptolemais, but in a yet higher degree, it was one of Herod the Great's model cities, in which he had embodied his scheme of Grecianizing his country by the influence of splendid Greek art and overpowering Greek intellect. It was also the metropolis of Palestine. St. Alexander, bishop of Jerusalem, Origen's fellow-student, was the intimate friend of Theoctistus, bishop of Caesarea; and it is clear that bishops, or their messengers, from the cities all along the coast, as for as Antioch, and even the distant Cappadocia and Pontus, were not unfrequent visitors to this great rallying-point of the church and the empire. When Origen, therefore, left Alexandria and took up his abode in a city that was in a manner the diminished counterpart of one he had abandoned, he did not find himself in a strange land. St. Theoctistus received him with delight. It was not long before he journeyed the short distance to Jerusalem, to renew his acquaintance with St. Alexander; and these two bishops were only too glad to put on his shoulders all the charges that he would accept. They referred to him, says Eusebius, on every occasion as their master; they committed to him alone the charge of interpreting and teaching Holy
- 61. Scripture and everything connected with preaching the Word of God in the church. From the way in which the historian joins the two bishops together, it would appear that Caesarea was a common school for the two dioceses, and a sort of ecclesiastical seminary whither the clerics from Jerusalem came, as to a centre where learning and learned men would abound more than in ruined and fallen AElia. It is certain, however, that Origen, in a short time, was teaching and writing as fast as at Alexandria. His name soon began to draw scholars. Firmilian, bishop of so distant a see as Caesarea of Cappadocia, one of the most stirring minds of his age, who had controversies on his hands all round the sea-coast to Carthage in one direction, and Rome in the other, was a friend of Theoctistus. It is possible that he knew Origen also, perhaps from having seen him at Alexandria, but more probably from having met him when Origen travelled into Greece. At any rate, he conceived an enthusiastic liking for him. Nothing would serve him but to make Origen travel to his own far-off province to teach and stimulate pastors and people; and, not long afterward, we find himself in Judaea, that is, at Caesarea, on a visit to Origen, with whom he is stated to have remained some time, for the sake of bettering himself in divinity. And, as Eusebius sums up, not only those who lived in the same part of the world, but very many others from distant lands, left their country and came flocking to listen to him. We need not mention here again the names Gregory and Athenodorus. The position now occupied by Origen at Caesarea was, therefore, one of the highest importance. He was no longer a private teacher, or even an authorized master teaching in private; he was no less than the substitute for the bishop himself. In the Eastern Church, indeed, the custom by which no one but the Bishop ever preached in the church was not so strictly observed as it was in the West; but if a {491} presbyter did received the commission of preaching, it was always with the understanding that what he said was said on behalf of the pontiff, whose presence in his chair was a guarantee for its orthodoxy. When Origen, therefore, on the Lord's day, after the reading of the holy Gospel, stood forward from his place in the
- 62. presbytery, and began to explain either the Gospel text itself or some passage in the Old Testament which also had formed part of the liturgical service, it was well understood that he was speaking with authority. And this is the first light in which we should view his homilies. It would be saying little to say that Origen's homilies and commentaries (for we need not distinguish them here) marked an era in the exposition of Scripture. They not only were the first of their kind, but they may be said to have created the art, and not only to have created it, but, in certain aspects, to have finished it and to have become like Aristotle in some of his treatises, at once the model and the quarry for future generations. It may be true, as of course it is, that he was not absolutely the first to write expositions of Scripture. The splendid eloquence of Theophilus of Antioch had already been heard on the four Gospels, and his spirit of interpretation seems to have had much more affinity for Origen's own spirit than for that of the school of his own Antioch two centuries later. Melito had written on the Apocalypse, but his direct labors on Scripture were only an insignificant part of his voluminous works, if, indeed, they were not all rather apologetic and hortatory than explanatory. The Mosaic account of the creation had occupied a few fathers with its defence against Gnostic and infidel. But we know from Origen's own words that he had read and used his predecessors, as he calls them. And yet we may truly say that he is the first of commentators, not only because no one before him had dared to undertake the whole Scripture, but on account of his novel and regular method. He is turned by one great authority, Sixtus Senensis, almost self-taught, so little of what he says can he have gleaned from others. But in estimating how much Origen owed to those before him, we should lose a valuable hint towards understanding him if we forgot Clement of Alexandria and the great body of tradition, oral and written, of which the Alexandrian school was the headquarters. We know that the Alexandrian Jew, Philo, two hundred years before Clement's time, had written wonderful lucubrations on the mystical sense of Holy Scripture. The
- 63. Alexandrian catechetical teachers, catching and using the spirit of the place, had always been Alexandrian in their Scriptural teachings. Clement himself had commented on the whole of the Scriptures in his book called the Hypotyposes. Origen entered into inheritance. We see the spirit of the time and place in those questionings with which, in his early years, he used to puzzle his father. The unrivalled industry that made him collect versions of the sacred text from Syria, Asia, and even the shores of Greece, must have scrupulously sought out and exhausted every source of information and every extant document relating to Scripture exposition that was at hand for him in his own city. So that Origen, though in one sense the founder of a school, was really the culmination of a series of learned men, and, by the influence of his name, made common to the universal church that knowledge and method which before had been confined to the pupils that had listened to the Catechisms. Although, however, we may guess, we cannot be certain how progressively or gradually a methodical and scientific exegesis had been growing up at Alexandria; and we come upon the commentaries of Origen with all the freshness of a discovery. Before him we have been accustomed to writings like those of the apostolic fathers: we have been reading apologies of the most wonderful eloquence, whose Greek shames the rhetoricians, {492} or whose Latin has all the spirit, earnestness, and tenderness of new language, but in which Holy Scripture is at the most only summarized and held up to view. Or, again, we have been listening to a venerable priest crushing the heretics with the word of God, or to a philosopher confuting the Jews out of their own mouth. Or, once more, we have heard the pagan intellect of the world convinced that truth was nowhere to be found but in Jesus, that the writings of the prophets were better than those of the philosophers, and that the morality of the New Testament cast far into the shade the sayings of Socrates. Splendid ideas, striking applications, telling proofs, grand views, all these the early fathers found in holy Scripture, and all these they used in the exhortations, apologies, or refutations that were called for by the several necessities of their times. But
- 64. sustained, regular commentary, as such, they have none, or, what is the same to us now, none has come down. The explanation of words, the classification of meanings, the distinction of senses, the answering of difficulties and the solution of objections--all this, done, not for an odd portion of the text here and there, but regularly through the whole Bible, is what distinguishes the labors of Origen from those of all who have gone before him, and makes them so important for all who shall come after him. In making acquaintance with him we feel that we have come across a master, with breadth of view enough to handle masses of materials in a scientific way, and with learning enough never to be in want of materials for his science. We see in his Scripture commentaries the pressure of three forces of unequal strength, but each of them of marked presence, the tradition of the church, the teachings of the great school, and the needs of his own times. To understand him we must understand this pressure under which he wrote. The first two forces may be passed over as requiring no explanation. We must dwell a little on the latter, for unless we vividly realize the necessities under which the Christian teacher in his time lay, of meeting certain enemies and withstanding certain views, we shall be led to join in the cry of those who exclaim against Origen's Scripture exposition as partly useless and partly dangerous. These necessities arose from two phenomena that appeared almost with the birth of Christianity, and which, with a somewhat wide generalization, we may call the Ebionite and the Gnostic. No one can have looked into early church history without being struck by the difficulty the church seems to have had to free herself from the trammels of Judaism. We need not allude to St. Paul, and his Epistles to the Galatians and to the Romans, and his various contentions with friend and foe for the freedom of the Gospel. The Epistle to the Hebrews, with its thoroughness of dogmatic exposition and its grand style, was also addressed to the Judaizants. Nay, if Ebion himself ever had an existence, it is more than probable that he was teaching at Jerusalem about the very time at which the Epistle seems to have been written and sent, if sent, to the Christian Jews
- 65. of that city. It is certain, however, that Alexandria was one of the very earliest of the churches which shook itself free, in a marked manner, from the traditions of the law. The cosmopolitan spirit of the great city was a powerful natural auxiliary in a development which was substantially brought about by the Holy Ghost and the pastors of the patriarchal see. The Hebrew element hardly ever had such a footing at Alexandria as it had at Antioch. We can see in the writing of Justin Martyr, (circa 160,) whose wide experience of all the churches makes his testimony especially valuable, a. picture of Christianity, young and exuberant, with its face joyously set to its destined career, and with the swathing-bands of the synagogue lying neglected behind it. Justin had an {493} Alexandrian training, and among his many-sided gifts shone pre-eminent that intellectual culture which was the most effectual of the human weapons that beat off the spirit of Judaism. And in Clement himself there is no trace of any narrow formalism, but, on the contrary, a grand, world- embracing charity, that can recognize the work of the Divine Logos in all the manifold varieties of human wisdom and human beauty. So that long before the time that Origen succeeded his master, the Alexandrian church was free from all suspicion of clinging to what St. Paul calls the yoke of bondage; and knew no distinction of Jew or Greek. But the party that had troubled the Apostle, and spread itself through the churches almost as soon as the churches were founded, was by no means extinct, even at Alexandria. Since the destruction of Jerusalem, the Jews had become scattered all over the empire. The great towns, such as Antioch, Caesarea, and Alexandria, each contained a strong Jewish community. At Alexandria they were numerous enough to have a quarter to themselves. Now, it is not too much to say that many so-called Jews and Christians in such a city were neither Jews nor Christians, but Ebionites; that is, they acknowledged the divine mission of Christ, which destroyed their genuine Judaism, but denied his divinity, which was still more fatal to their Christianity. The consequences of such a state of things to the interpretation of Scripture are manifest. The law was still good and binding. Jerusalem was still the holy city, the chosen of God, and the spiritual and temporal capital of the world. St. Paul was
- 66. denounced as one who admitted heathen innovations and destroyed the word of God. Everything in holy Scripture, that is, in the Old Testament and in the scanty excerpts from the New, which they admitted, was to be understood in a rigorously literal sense; and the Clementines, once falsely attributed to St. Clement of Rome, but now considered to belong to the second century, and to be the work of an Ebionite, are the only writings of the period in which the allegorical sense is totally and peremptorily denied. Ebionism was not very consistent with itself, and the Ebionites of St. Jerome's time would hardly have saluted their sterner brethren of the apostolic age; but the name may always be truly taken to typify those whose views led them to hold to the carnal letter of the Old Testament. They carried the old Jewish exclusiveness into Christianity. They considered the historical parts of the Scripture to have been written merely because their own history was so important in God's sight that he thought it right to preserve its minutest record. The prophecies were only meant to glorify, to warn, or to terrify themselves, and had no message for the Gentiles. Even the parables and figures that occurred in the imagery of the inspired writer were dragged down to the most absurd and literal significations. The adherents of Ebionism were neither few nor silent in the time of Origen. But if the Ebionite party in Alexandria, and in the Church generally, was strong and stirring, there was a party not less important, perhaps, who, in their zeal for the freedom of Christianity against the bonds of Judaism, were in danger of going quite as far wrong in a different direction. It is always the case in a reaction, that the returning force finds it difficult to stop at its due mark. So it had been with the reaction against the Ebionites, and especially at Alexandria. There was a body of advanced Christians who did not content themselves with not observing the law, but went on to depreciate it. It was not enough for them to see the Old Testament fulfilled by Jesus Christ, but they must needs show that it never had much claim to be even a preparation and a type. It was full of frivolous details, useless records, and absurd narrations. {494} Who
- 67. cared for the minutiae about Pharaoh's butler, Joseph's coat, or Tobias's dog? Of what importance to the world were the marchings and counter-marchings, the stupid obstinacy and the unsavory morality of a few thousand Hebrews? Who was interested to hear how their prophets scolded them, or their enemies destroyed them, or their kings tyrannized over them? How could it edify Christians to know the number and color of the skins of the tabernacles or the names of the masons and blacksmiths that built the Temple, or the fact that the Jewish people considerably varied their carnal piety by intervals of still more carnal crime and idolatry? The state of things represented by the Old Testament had passed away, and they were of no interest save as ancient history; and therefore, it was absurd to treasure up the Pentateuch and the Prophets as if they were anything more, and not rather much less, than the rhapsodies of Homer and the travels of Herodotus. In fact--and to this conclusion a considerable party came before long--the Old Testament was certainly not divine at all; at any rate, it was not the work of the Father of the Lord Jesus, but of some other principle. And here the Gnostic interest was at hand with an opportune idea. Who could have written the Old Testament but the Demiurge? That primary offshoot of the Divinity, just, but not good, (this was their distinction,) can never have been more worthily employed than in concocting a series of writings in which there was some skill, some justice, and very little goodness. The Demiurge was certainly a handy suggestion, and the consigning of the Old Testament to his workmanship made all commentary thereon compressive into a very brief space. Away with it all, for a farrago of nonsense, lies, and nuisances! Of course, neither of these parties, when extremely developed, could lay any claim to Christianity. But the world of that day had in it Ebionites and Gnostics of every degree and every changing hue of error. They were not unrepresented in the very bosom of the Church. Pious Christians might be found who, strong in filial feeling to their Jewish great-grandfathers, would see in the records of the old covenant nothing but a most interesting family history, with
- 68. delightfully long pedigrees and a great deal of strong language about the glory and dignity of the descendants of Israel. On the other hand, equally pious Christians, and among them a great majority, perhaps, of the Gentile converts, would consider it an extravagant compliment to read in the house of God the sayings and doings of such a very unworthy set of people as the Hebrews. And the remarkable fact would be, that both these sets of worthy Christians would begin with the same fundamental error, though arriving at precisely opposite conclusions. That the Old Testament had a literal meaning, and no other was the starting-point of both Ebionite and Gnostic The former concluded, therefore let us honor it, for we are a divine race; the latter, therefore let us reject it, for what are the Jews to us? It would not require many sentences to prove, if our object in these notes were proof of any sort, that Origen's leading idea in his Scripture exposition is to look for the mystical sense. His very name is a synonym for allegory, and he is perhaps as often blamed for it as praised. But even blame, when outspoken and honest, is better than feeble excuse; and and unfortunately not a few of the great Alexandrian's critics have undertaken to excuse him for having such a leaning to allegory. The Neo-Platonists, they say, dealt largely in myths, and allegorized everything; somebody allegorized Homer just about that time. Now Origen was a Platonist. We might answer, that Origen was above all a Christian, and knew but very little of Plato till he was thirty years old; and that the Greek allegories {495} were invented by a more decorous generation for the purpose of veiling the grossness of the popular mythology; whereas the Christian allegory, as introduced by St Paul, or indeed by our Blessed Saviour, was a spiritual and mysterious application of real facts. Others, again, offer the excuse that Philo had allegorized very much, and Origen admired Philo. This is saying that allegory was very usual at Alexandria, as we have said ourselves when speaking of St. Clement. But it is not saying why allegory was kept up so warmly in the school of the Catechisms, or what was the radical cause that made its being
- 69. kept up there a necessity for the well-being of the Church. This we have endeavored to state in the foregoing remarks. When Origen, then, announces his grand principle of Scripture commentary, in the fourth book of the De Principiis, we may be excused if we see in it the statement of an important canon, whereby to understand much that he has written. He says, Wherefore, to those who are convinced that the sacred books are not the utterances of man, but were written and made over to us by the inspiration of the Holy Ghost, by the will of God the Father of all through Jesus Christ, we will endeavor to point out how they are to read them, keeping the rules of the divine and apostolic Church of Jesus Christ. This is the key-note of all his exposition, and derives its significance from the state of opinions among those for whom he wrote; and a dispassionate application of it to such passages as seem questionable or gratuitous in his writings, will explain many a difficulty, and show how clearly he apprehended the work he had to do. If the Old Testament be really the word of the Holy Ghost, as, he says, all true Christians believe, then nothing in it can be trivial, nothing useless, nothing false. This he insists upon over and over again. And, descending more to particulars, he states these three celebrated rules of interpretation, which may be called, with their development, his contribution to Scripture exposition. They are so plainly aimed at Ebionites and Gnostics, that we need merely to state them to show the connection. His first rule regards the old Law. The Law, he says, being abrogated by Jesus Christ, the precepts and ordinances that are purely legal are no longer to be taken and acted up to literally, but only in their mystical sense. This seems rudimentary and evident nowadays; but at that period it greatly needed to be clearly stated and enforced. His second rule is about the history and prophecy relating to Jew or Gentile that is found in the Old Testament. The Ebionite who kissed the Pentateuch, and the Gnostic who tore it up, were both foolish because both ignorant. These historic and prophetic details were
- 70. undoubtedly true in their letter; but their chief use to the Christian Church, and the main object the Holy Spirit had in giving them to us, was the mystical meaning that lies hidden under the letter. Thus the earthly Pharaoh, the earthly Jerusalem, Babylon, or Egypt, are chiefly of importance to the Church from the fact that they are the allegories of heavenly truths. Origen's third canon of scriptural exposition is this: Whatever in holy Scripture seems trivial, useless, or false, (the Gnostics could not or would not see that parabolic narratives are most unjustly called false,) is by no means to be rejected, but its presence in the divine record is to be explained by the fact that the divine Author had a deeper and more important meaning in it than appears from the letter. Such portions, therefore, must be taken and applied in a spiritual and mystical sense, in which sense chiefly they were dictated by Almighty God. These three rules look simple now; they were all-important and not so simple then. It was by means of them, {496} and in the spirit which they indicate, that the great catechist led his hearers by the hand through the flowery paths of God's word, and in his own easy, simple, earnest style, so different from that of the rhetoricians, showed them the true use of the Old Testament. We hope it is not a fanciful idea, but it has struck us that, the difference of circumstances considered, there are few writers so like each other in their handling of holy Scripture as Origen and St. John of the Cross. Both treat of deep truths, and in a phraseology that sounds uncommon--the one because his hearers were intellectual Greeks, the other because he is professedly treating of the very highest points of the spiritual life. Both use holy Scripture in a fashion that is absolutely startling to those who are accustomed to rationalistic Protestantism, or to what may be called the domestic wife-and- children interpretation of the Evangelicals. Both bring forward, in the most unhesitating manner, the mystic sense of the inspired words to prove or illustrate their point, and both mix up with their more abstruse disquisitions a large amount of practical matter in the very
- 71. plainest words. From communion with both of them we rise full of a new sense of the presence and nearness of the Spirit of God, and of reverence for the minutest details of his Word. Finally, both the Greek father and the Spanish mystic interpret the ceremonial prescriptions, the history, the allusions to physical nature, and the incidents of domestic life that occur in the Old Testament, as if all these, however important in their letter, had a far deeper and more interesting signification addressed to the spiritual sense of the spiritual Christian. To illustrate Origen's principles of Scripture interpretation by extracts from his works would exceed our present limits, however interesting and satisfactory the task might be. Neither have we space to notice his celebrated division of the meaning of the text into literal, mystical, and moral, a division he was the first to insist upon formally. To answer the objections of critics against both his principles and his alleged practice would also be a distinct task of great length. We must content ourselves with having briefly sketched and indicated his spirit. There are grave theological controversies too, as is well known, connected with his name; and on these we have had no thought of entering. The purpose of this and the preceding articles has not been dogmatical, but rather biographical. We have attempted to set forth on the one hand the personal character of this great man; on the other, the external circumstances by which that character was influenced, and through which it exercised influence on others. {497}
- 72. Translated from the Spanish. PERICO THE SAD; OR, THE FAMILY OF ALVAREDA. CHAPTER I. Following the curve formed by the ancient walls of Seville, encircling it as with a girdle of stone, leaving on the right the river and Las Delicias, we reach the gate of San Fernando. From this gate, in a direct line across the plain, as far as the ridge of Buena Vista, extends a road which passes the rill upon a bridge of stone, and ascends the steep side of the hill. To the right of the road are seen the ruins of a chapel. At a bird's-eye view this road looks like an arm which Seville extends toward the ruins as if to call attention to them; for though small, and without a vestige of artistic merit, they form a religious and historic souvenir. They are an inheritance from the great king, Fernando III., whose memory is so popular that he is admired as a hero, venerated as a saint, and beloved as a king: thus realizing, in one grand historic figure the ideal of the Spanish people. Having gained the summit, the road descends upon the opposite side into a a little valley, through which runs a narrow stream, which has washed its channel so clean that you will see in it only shining pebbles and golden sand. Fording this stream, the road touches on its right at a cheerful and hospitable little inn, and salutes on its left a Moorish castle seated so haughtily upon the height that it seems as though the ground had risen solely to form a pedestal for it. This castle was given by Don Pedro de Castilla to Doña Maria de Padilla, whose name it retains.
- 73. The estate and castle of Doña Maria passed in time, as a pious donation, to the Cathedral of Seville, the chapter of which has, in our days, sold it to a private gentleman. The associations passed for nothing, since a little while afterward, the withered, old, and furrowed Doña Maria appeared clothed in the whitest of lime, and adorned with brilliants of crystal. Let us follow the road which advances, opening its way through the palmettos and evergreens of some pasture-lands, until it enters the village of Dos-Hermanas, [Footnote 85] situated in the midst of a sandy plain, two leagues from Seville. [Footnote 85: Dos-Hermanas, two sisters. ] One sees here neither river, nor lake, nor umbrageous trees, nor rural houses with green blinds, nor arbors covered with twining plants, nor peacocks and Guinea fowls picking the green turf, nor grand avenues of trees in straight lines, like slaves holding parasols, to provide a constant shade for those who walk beneath. All these are wanting here. Sad it is to confess it! All is common, rude, and inelegant, but instead, one meets good and contented faces, which prove how little those things are needed to make happiness. One sees, beside, flowers in the yards of the houses, and at their doors gay and healthy children, even more numerous than the flowers, and finds that sweet peace of the country, made up of silence and solitude, an atmosphere of Eden and the sky of paradise. The village consists of houses of a single story, arranged in long, straight, though not parallel streets, which open upon the large, sandy market-place, spread out like a yellow carpet before a fine church, which lifts its lofty tower, surmounted by a cross, like a soldier elevating his standard. {498} Behind the church we shall find the oasis of this desert. Supported by the rear wall of the edifice is a gate, opening into a wide and vast
- 74. court, which leads to the chapel of Saint Anna, the patroness of the place. Built against the side of the chapel is the small and humble dwelling of the custodian, who is both singer and sacristan of the church. In this enclosure we shall see century-old cypresses, thick foliaged and sombre; the lilac, of stem so slight and rapid growth, lavishing leaves, flowers, and perfumes upon the wind, as if conscious that its life is short; the orange, that grand seigneur, that favorite son of the soil of Andalusia, to whom it yields a life so sweet and long. We shall see the vine, which, like a child, needs the help of man to thrive and rise, and which spreads its broad leaves as if to caress the trellis that supports it. For it is certain that even plants have their individual characters from which we receive different impressions. We can hardly see a cypress without sadness, a lilac without tenderness, an orange-tree without admiration. Does not the lavender suggest the thought of a neat and peaceful interior; and the rosemary, perfume of holy night, does it not awaken the wholesome and sacred thoughts of that season? To the right and left of the place extend those interminable olive plantations, which form the principal branch of the agriculture of Andalusia. The trees being planted well apart from each other give a cheerful air to these groves, but the ground underneath, kept so level and free from other vegetation by the plough, renders them wearisomely monotonous. At certain distances we encounter the groups of buildings which belong to the estates. These are constructed without taste or symmetry, and we may go all round them without finding the front. There is nothing imposing about these great masses, or structures, except the towers of their windmills, which rise above the olives as if to count them. The most of these estates belong to the aristocracy of Seville, but they are generally deserted because the ladies do not like to live in the country, and are therefore as desolate and as empty as barns, so that in these out-of-the-way places, the silence is only broken by the crowing of the cock, while he vigilantly guards his seraglio, or by the braying of some superannuated ass, that, turned out by the overseer to take his ease, tires of his solitude.
- 75. At the close of a beautiful day in January, in the year 1810, might have been heard the fresh voice of a youth of some twenty years, who, with his musket upon his shoulder, was walking with a firm but light step along one of the footpaths which are traced through the olive groves. His figure was straight, tall, and slight. His person, his air, his walk, had the ease, the grace, and the elegance which art endeavors to create, and which nature herself lavishes upon the Andalusians with generous hand. His head, covered with black curls, a model of the beautiful Spanish type, he carried erect and proudly. His large eyes were black and vivid; his look frank and full of intelligence. His well-formed upper lip, shortened with an expression of cheerful humor, showed his white and brilliant teeth. His whole person breathed a superabundance of life, health, and strength. A silver button fastened the snowy shirt at his brown throat. He wore a short jacket of gray cloth, short trowsers, tied at the knee with cords and tassels of silk, and a yellow silk girdle passed several times around his waist. Leather shoes and gaiters of the same, finely stitched, encased his well-formed feet and legs. A wide-brimmed Portuguese hat, adorned with a velvet band and silk tassels, and jauntily inclined toward the left side, completed the elegant Andalusian dress. This youth, noted for his active disposition, and for his impulsive and daring character, was employed by the superintendent of one of the estates to act as guard during the olive gathering. He sang as he went along: {499} The way is short, my step is light, I loiter not, nor do I weary; The path seems downward--easy trod, When up the hill I climb to Mary. But long the road, and oh! how steep! My lingering footsteps slow and weary;
- 76. The mountains seem before me piled When down the hill I come from Mary. Arriving at the paling which enclosed the plantation the guard sprang over it without stopping to look for the gate, and found himself in a road face to face with another youth a little older than himself, who was also going toward the village. He was dressed in the same manner, but he was neither so tall nor so erect as the former. His eyes were gray, and not so vivid, and his glance was more tranquil, his mouth was graver and his smile sweeter. Instead of a gun he carried a spade upon his shoulder. An ass preceded him without being driven, and he was followed by an enormous dog, with short thick hair of a whitish yellow color, of the fine race of shepherd-dogs of Estremadura. Halloo! Is this you, Perico? God bless you! exclaimed the elegant guard. And you, too, Ventura, are you coming to take a rest? No, answered Ventura, I come for supplies, and besides, it is eight days-- Since you saw my sister, Elvira, interrupted Perico with his sweet smile. Very good, my friend, you are killing two birds with one stone. You keep still, Perico, and I will. He whose house has a glass roof shouldn't throw stones at his neighbor's, answered the guard. You are happy, Ventura, proceeded Perico with a sigh, for you can marry when you like, without opposition from any one.
- 77. And what! exclaimed Ventura, who or what can oppose your getting married? The will of my mother, replied Perico. What are you saying? asked Ventura, and why? What fault can she find with Rita, who is young, good-looking, and comes of a good stock, since she is own cousin to you? That is precisely the reason my mother alleges for not being in favor of it. An old woman's scruples! Does she wish to change the custom of the church, which permits it? My mother's scruples, replied Perico, are not religious ones. She says that the union of such near relations is against nature, that the same blood in both repels itself, and distaste is the result; that sooner or later evils, misfortunes and weariness follow and overtake them, and she gives a hundred examples to prove it. Don't mind her, said Ventura; let her prophesy and sing evil like an owl. Mothers have always something against their sons' marrying. No, answered Perico gravely, no; without my mother's consent I will never marry. They walked along some instants in silence when Ventura said: The truth is, I am like the captain who embarked the passengers and remained on shore himself, or like the preacher who used to say, 'Do as I tell you and not as I do;' for, in fact, does not the will of my father hold me, tied down like a lion with a woollen rope? Do you think, Perico, that if it were not for my father, I would not now be in Utrera, where the regiment of volunteers is enlisting to go and fight the infamous traitors who steal across our frontier in the guise of
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