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GANDHI INSTITUTE FOR EDUCATION & TECHNOLOGY
FIFT SEMESTER EXAMINATION-2010
COMPUTER ARCHITECTURE & ORGANIZATION
FULL MARK: 70 TIME: - 3HOURS
Prepared by: Asst.Prof. Santosh Kumar Rath (CSE DEPARTMENT) Page 1
Answer Question No.1 which is compulsory and any five from the rest.
The figure in the right hand margin indicates marks.
1. Answer the following question: 2*10=20
(a) Write is the function of MAR?
Ans: MAR stands for Memory address register. MAR stores the address of the memory
location to be accessed by the processor.
(b) What are advantages of multi bus over single bus?
Ans: Multi bus architecture provides more paths for data transfer a s compared to
single bus architecture. By providing more paths for data transfer a significant
reduction in the number of clock cycle needed to execute an instruction in case of
multi bus architecture.
(c) Differentiate between direct access and sequential access?
Ans: in direct access we can fetch any elements from any position directly but in
sequential access we have to traverse whole data which we stored at first.
- the difference is that , direct access allows us to go directly to a specific pieces of
data using an index where as sequential access is used when data is sequentially
stored on a magnetic tape. we must traverse all the data before we reach, searching
for.
(d) What is the unit of data transfer between processor and cache memory?
Ans: Word or byte is the unit of data transfer between processor and cache memory.
(e) Mention one difference between SDRAM, DDR SDRAM?
Ans: SDRAM stands for synchronous dynamic random access memory where as DDR
SDRAM stands for double data rate synchronous dynamic random access memory.
Both SDRAM and DDR SDRAM can be differentiate by the factor speed i.e. DDR
SDRAM transfer data roughly twice the speed of SDRAM.
(f) Differentiate between DRAM and SRAM in term of speed, size, and cost?
Ans: Speed: DRAM (Dynamic Ram): Access time is greater i.e slower in speed.
SRAM (Static Ram): Less access time hence faster memories.
Size: DRAM: less
SRAM: More
GANDHI INSTITUTE FOR EDUCATION & TECHNOLOGY
FIFT SEMESTER EXAMINATION-2010
COMPUTER ARCHITECTURE & ORGANIZATION
FULL MARK: 70 TIME: - 3HOURS
Prepared by: Asst.Prof. Santosh Kumar Rath (CSE DEPARTMENT) Page 2
Cost: DRAM: Less SRAM: More
(g) Define seek time?
Ans: seek time is a measure of the amount of time required for the read/write head to
move between tracks over the surface of platter.
(h)What do you understand by exponent overflow?
Ans: Overflow is an exponent to IEEE standard when representation of floating point
number. Exponent overflow means exponent is having a value which is too larger i.e
size is more than the register size.
(i) IS ROM a RAM? Why?
Ans: ROM is not a RAM because ROM is non-volatile in nature where as RAM is
volatile in nature so A ROM cannot be a RAM.
(j) Differentiate between horizontal and vertical microprogramming?
Ans: A horizontal microprogramming requires a larger micro programmed memory but
a vertical microprogramming require more encoding and decoding of signal, hence
time to access leads to slower operation.
2) A) List the different cache mapping techniques? Explain any one of them?
Ans: Three types of mapping procedures are there?
(1) Associative Mapping-The fastest and most flexible cache organizations uses
associative mapping. The associative memory stores both the address and content of
memory word. This permits any location in cache to store word in main memory.
(2) Direct Mapping-Associative memories are expensive compared to RAM's because of
added logic associated with each cell.
(3) Set Associative Mapping-It is a more general method that includes pure associative
and direct mapping as special case. It is an improvement over the direct mapping
organization in that each word of cache can store two or more words of memory under
the same index address. Each data word is stored together with its tag and the
number of tag data items in one word of cache is said to form a set.
Direct Mapping:
• Each location in RAM has one specific place in cache where the data will be held.
• Consider the cache to be like an array. Part of the address is used as index into
the cache to identify where the data will be held.
GANDHI INSTITUTE FOR EDUCATION & TECHNOLOGY
FIFT SEMESTER EXAMINATION-2010
COMPUTER ARCHITECTURE & ORGANIZATION
FULL MARK: 70 TIME: - 3HOURS
Prepared by: Asst.Prof. Santosh Kumar Rath (CSE DEPARTMENT) Page 3
• Since a data block from RAM can only be in one specific line in the cache, it must
always replace the one block that was already there. There is no need for a
replacement algorithm.
B) a two way set associative cache memory uses block of four word. The caches can
accommodate a total of 2048 word from main memory. The main memory size is 128K
* 32. What is the size of cache memory?
Ans:
Given – Two ways set associative mapping
Number of blocks in a set =2
Main memory size = 128 K* 32
Cache Memory block size = 4 words
Total no of blocks= no of words/ cache memory block size= 2048/4=512
No of set= size of cache in block/no of block in a set=512/2=256
Size of cache memory= 2048/4=512 blocks.
3) A) Explain the different types of ROM? Explain the advantages and disadvantages?
Ans: ROM stands for Read Only Memory which is non-volatile in nature.
Read Only Memory is physical memory that is not-volatile, meaning, if there is not electricity,
the memory is not lost. ROMs are used to put programs which start hardware components. and
good example of this is the BIOS on your computer. these types of software are called firmware.
ROMs server their purpose, but have their limitations because once you burn the information
into a ROM chip, it cannot be charged, that is why they come up with new types of ROMs there
are three
PROM: Programmable read-only memory - on this type of memory, you can write into just
once, you cannot erase the data once you store it in a PROM
EPROM: Erasable Programmable read-only memory - on this type of memory you can erase the
whole data and rewrite with a new one. Meaning, you have to erase the everything and put new
data, but you cannot keep any of the old data once you override it with the new one - BIOS and
CMOS use EPROM
EEPROM: Electronically Erasable Programmable read-only memory - on this type of ROM you
can edit/modify the data and still keep your data. as you can see from the image above, all these
chips look alike, the difference in the internal circuitry. Some examples of these chips on
computers are the computer CMOS and BIOS. also the difference in these chips are the prices.
EEPROMs are more expensive then ROM chips
GANDHI INSTITUTE FOR EDUCATION & TECHNOLOGY
FIFT SEMESTER EXAMINATION-2010
COMPUTER ARCHITECTURE & ORGANIZATION
FULL MARK: 70 TIME: - 3HOURS
Prepared by: Asst.Prof. Santosh Kumar Rath (CSE DEPARTMENT) Page 4
B) Explain the mechanism of virtual memory:
Ans: if your computer lacks the random access memory (RAM) needed to run a
program or operation, Windows uses virtual memory to compensate.
Virtual memory combines your computer’s RAM with temporary space on your hard
disk. When RAM runs low, virtual memory moves data from RAM to a space called a
paging file. Moving data to and from the paging file frees up RAM to complete its work.
The purpose of virtual memory is to enlarge the address space, the set of addresses a
program can utilize. For example, virtual memory might contain twice as many
addresses as main memory. A program using all of virtual memory, therefore, would
not be able to fit in main memory all at once. Nevertheless, the computer could
execute such a program by copying into main memory those portions of the program
needed at any given point during execution.
Virtual Memory Advantages
---------------------------------
You can run more applications at once.
You can run larger applications with less real RAM.
Applications may launch faster because of File Mapping.
You don't have to buy more memory (RAM).
Virtual Memory Disadvantages
---------------------------------
Applications run slower.
It takes more time to switch between applications.
Less hard drive space for your use.
Reduced system stability
4) A) List the four alternative methods of rounding the result of floating point
operation.
Ans: Rounding Mode: this floating point format support four different modes.
1) Round to Zero: This result closest to zero is returned. Nothing is added to the
least significant bit. This is equivalent to truncation.
2) Round Up: The more positive result closest to the infinity precise result is
returned. If the result is +ve and either the strictly bit is 1, the result is
GANDHI INSTITUTE FOR EDUCATION & TECHNOLOGY
FIFT SEMESTER EXAMINATION-2010
COMPUTER ARCHITECTURE & ORGANIZATION
FULL MARK: 70 TIME: - 3HOURS
Prepared by: Asst.Prof. Santosh Kumar Rath (CSE DEPARTMENT) Page 5
rounded. if the result is –ve , the result is not rounded because the un rounded
result is the most + ve result closest to the precise result.
3) Round Down: in this case more –ve result is returned. If the result is –ve and
either the sickly bit is 1, 1 is added to the least significant bit. If the result is
+ve nothing is added to the least significant bit.
4) Round to Nearest: This result closest to the infinitely precise result is returned.
If the undelivered bit below the LSB, have a significance of more than half the
LSB. If the result is exactly half, 1 is added if the LSB is 1.
B) What are steps for floating point division.
Ans: A floating point division operation mostly follows 3 steps.
Step 1: Subtract exponent and add bias. The bias value is 127 in case of single
precision number and 1023 in case of double precision number.
Step 2: Divide the mantissa and determine the sign result.
Step 3: Normalize the data.
5) A) write an algorithm for signed operand multiplication using booth algorithm.
Ans:
Register used in Booths algorithm: A->Accumulator (initially Zero)
GANDHI INSTITUTE FOR EDUCATION & TECHNOLOGY
FIFT SEMESTER EXAMINATION-2010
COMPUTER ARCHITECTURE & ORGANIZATION
FULL MARK: 70 TIME: - 3HOURS
Prepared by: Asst.Prof. Santosh Kumar Rath (CSE DEPARTMENT) Page 6
M-> Multiplicand
Q-> Multiplier
SC -> Sequential Counter (No’s of bits present in Q Register)
This process is continuing till the sequential counter becomes Zero. The result is
stored in Register A and Q.
Example:
B) Represent 0.5 in IEEE 754 single precision format.
Ans: Step 1: Convert decimal number to binary format 0.5 * 2= 1.0 0.1
Step 2: Normalize the number 0.1 * 2-1
Single Precision – For the above given number S=0, E =-1, M=0
Bias for the single precision format is given by 127.
So E1 =E +127 =-1 +127 =(126)10= (01111110)2
Number in single precision format is given as
0 01111110 0
Sign bit Exponent Mantissa
GANDHI INSTITUTE FOR EDUCATION & TECHNOLOGY
FIFT SEMESTER EXAMINATION-2010
COMPUTER ARCHITECTURE & ORGANIZATION
FULL MARK: 70 TIME: - 3HOURS
Prepared by: Asst.Prof. Santosh Kumar Rath (CSE DEPARTMENT) Page 7
6 A) Explain the different type of Addressing Modes?
Ans: Addressing modes are an aspect of the instruction set architecture in most
central processing unit (CPU) designs. The various addressing modes that are defined
in a given instruction set architecture define how machine language instructions in
that architecture identify the operand (or operands) of each instruction. An addressing
mode specifies how to calculate the effective memory address of an operand by using
information held in registers and/or constants contained within a machine instruction
or elsewhere.
Types of Addressing Modes
Each instruction of a computer specifies an operation on certain data. The are various
ways of specifying address of the data to be operated on. These different ways of
specifying data are called the addressing modes. The most common addressing modes
are:
 Immediate addressing mode
 Direct addressing mode
 Indirect addressing mode
 Register addressing mode
 Register indirect addressing mode
 Displacement addressing mode
 Stack addressing mode
To specify the addressing mode of an instruction several methods are used. Most often
used are:
a) Different operands will use different addressing modes.
b) One or more bits in the instruction format can be used as mode field. The value of
the mode field determines which addressing mode is to be used.
The effective address will be either main memory address of a register.
Immediate Addressing: This is the simplest form of addressing. Here, the operand is
given in the instruction itself. This mode is used to define constant or set initial values
of variables. The advantage of this mode is that no memory reference other than
instruction fetch is required to obtain operand. The disadvantage is that the size of the
number is limited to the size of the address field, which most instruction sets is small
compared to word length.
INSTRUCTION OPERAND
Direct Addressing: In direct addressing mode, effective address of the operand is
given in the address field of the instruction. It requires one memory reference to read
the operand from the given location and provides only a limited address space. Length
of the address field is usually less than the word length.
Ex : Move P, Ro, Add Q, Ro P and Q are the address of operand.
Indirect Addressing: Indirect addressing mode, the address field of the instruction
refers to the address of a word in memory, which in turn contains the full length
GANDHI INSTITUTE FOR EDUCATION & TECHNOLOGY
FIFT SEMESTER EXAMINATION-2010
COMPUTER ARCHITECTURE & ORGANIZATION
FULL MARK: 70 TIME: - 3HOURS
Prepared by: Asst.Prof. Santosh Kumar Rath (CSE DEPARTMENT) Page 8
address of the operand. The advantage of this mode is that for the word length of N, an
address space of 2N can be addressed. He disadvantage is that instruction execution
requires two memory reference to fetch the operand Multilevel or cascaded indirect
addressing can also be used.
Register Addressing: Register addressing mode is similar to direct addressing. The
only difference is that the address field of the instruction refers to a register rather
than a memory location 3 or 4 bits are used as address field to reference 8 to 16
generate purpose registers. The advantages of register addressing are Small address
field is needed in the instruction.
Register Indirect Addressing: This mode is similar to indirect addressing. The
address field of the instruction refers to a register. The register contains the effective
address of the operand. This mode uses one memory reference to obtain the operand.
The address space is limited to the width of the registers available to store the effective
address.
Displacement Addressing:
In displacement addressing mode there are 3 types of addressing mode. They are:
1) Relative addressing
2) Base register addressing
3) Indexing addressing.
This is a combination of direct addressing and register indirect addressing. The value
contained in one address field. A is used directly and the other address refers to a
register whose contents are added to A to produce the effective address.
Stack Addressing: Stack is a linear array of locations referred to as last-in first out
queue. The stack is a reserved block of location, appended or deleted only at the top of
the stack. Stack pointer is a register which stores the address of top of stack location.
This mode of addressing is also known as implicit addressing.
B) Explain the Addressing Mechanism in Big-Endian and Little- Endian format with
example?
Ans: There are two scheme used to assign the memory location for storing multi byte
data.1) Big-Endian Scheme II) Little-Endian scheme.
Big- Endian is the order in which big end (MSB) is stored first (at lowest storage
address)
Little-Endian is an order in which the ‘little end (LSB) is stored first.
Word Address Byte Address
Big-Endian
0 1 2 3
4 5 6 7
2k-4 2k-3 2k-2 2k-1
GANDHI INSTITUTE FOR EDUCATION & TECHNOLOGY
FIFT SEMESTER EXAMINATION-2010
COMPUTER ARCHITECTURE & ORGANIZATION
FULL MARK: 70 TIME: - 3HOURS
Prepared by: Asst.Prof. Santosh Kumar Rath (CSE DEPARTMENT) Page 9
Word Address Byte Address
Little-Endian
7) A) Explain the instruction execution cycle step by step?
Ans: The time period during which one instruction is fetched from memory and
executed when a computer is given an instruction in machine language. There are
typically four stages of an instruction cycle that the CPU carries out:
1. Fetch the instruction from memory. This step brings the instruction into the
instruction register, a circuit that holds the instruction so that it can be
decoded and executed.
2. Decode the instruction.
3. Read the effective address from memory if the instruction has an indirect
address.
4. Execute the instruction.
Steps 1 and 2 are called the fetch cycle and are the same for each instruction. Steps 3
and 4 are called the execute cycle and will change with each instruction.
The term refers to both the series of four steps and also the amount of time that it
takes to carry out the four steps. An instruction cycle also is called machine cycle.
B) Convert the arithmetic expression:
A* b + A *(B*D+C*E) into reverse polish notation.
Ans: Symbol Scanned Stack Expression
A ( A
* ( * A
B ( * A B
+ ( + A B *
A ( + A B * A
* ( + A B * A
( ( + * ( A B * A
B ( + * ( A B * A B
* ( + * ( A B * A B
D ( + * ( A B * A B D
+ ( + * ( + A B * A B D
C ( + * ( + A B * A B D C
3 2 1 0
7 6 5 4
2k-1 2k-2 2k-3 2k-4
GANDHI INSTITUTE FOR EDUCATION & TECHNOLOGY
FIFT SEMESTER EXAMINATION-2010
COMPUTER ARCHITECTURE & ORGANIZATION
FULL MARK: 70 TIME: - 3HOURS
Prepared by: Asst.Prof. Santosh Kumar Rath (CSE DEPARTMENT) Page
10
* ( + * ( + A B * A B D * C
E ( + * ( + A B * A B D * C E
) ( + * ( + ) A B * A B D * C E + * +
8 A) write short notes on any two.
a) Virtual memory
b) Micro programmed Control
c) Segmentation
Ans: a) Virtual memory: Virtual memory is a feature of an operating system that
enables a process to use a memory (RAM) address space that is independent of other
processes running in the same system, and use a space that is larger than the actual
amount of RAM present, temporarily relegating some contents from RAM to a disk,
with little or no overhead. Virtual memory is a technique that allows processes that
may not be entirely in the memory to execute by means of automatic storage allocation
upon request. The term virtual memory refers to the abstraction of separating
LOGICAL memory--memory as seen by the process--from PHYSICAL memory--memory
as seen by the processor. Because of this separation, the programmer needs to be
aware of only the logical memory space while the operating system maintains two or
more levels of physical memory space. The virtual memory abstraction is implemented
by using secondary storage to augment the processor's main memory. Data is
transferred from secondary to main storage as and when necessary and the data
replaced is written back to the secondary storage according to a predetermined
replacement algorithm. If the data swapped is designated a fixed size, this swapping is
called paging; if variable sizes are permitted and the data is split along logical lines
such as subroutines or matrices, it is called segmentation.
b) Micro programmed Control: While executing a program, the microprocessor needs
to access memory frequently to read instruction codes and data stored in memory and
the interfacing circuit enables that access.
The primary function of memory interfacing is to allow the microprocessor to read
from and write into a given register of memory chip.
1. Be able to select the chip
2. Identify the register 3.Enable the appropriate buffer.
c) Segmentation: A segment can be defined as a logical grouping of instruction.
- Segmentation is a techniques used to handled different problem of different size and
different logical structure.
- In this case, a small program is divided into a number of logical parts, each
individual logical parts are known as a segment.

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Co question 2010

  • 1. GANDHI INSTITUTE FOR EDUCATION & TECHNOLOGY FIFT SEMESTER EXAMINATION-2010 COMPUTER ARCHITECTURE & ORGANIZATION FULL MARK: 70 TIME: - 3HOURS Prepared by: Asst.Prof. Santosh Kumar Rath (CSE DEPARTMENT) Page 1 Answer Question No.1 which is compulsory and any five from the rest. The figure in the right hand margin indicates marks. 1. Answer the following question: 2*10=20 (a) Write is the function of MAR? Ans: MAR stands for Memory address register. MAR stores the address of the memory location to be accessed by the processor. (b) What are advantages of multi bus over single bus? Ans: Multi bus architecture provides more paths for data transfer a s compared to single bus architecture. By providing more paths for data transfer a significant reduction in the number of clock cycle needed to execute an instruction in case of multi bus architecture. (c) Differentiate between direct access and sequential access? Ans: in direct access we can fetch any elements from any position directly but in sequential access we have to traverse whole data which we stored at first. - the difference is that , direct access allows us to go directly to a specific pieces of data using an index where as sequential access is used when data is sequentially stored on a magnetic tape. we must traverse all the data before we reach, searching for. (d) What is the unit of data transfer between processor and cache memory? Ans: Word or byte is the unit of data transfer between processor and cache memory. (e) Mention one difference between SDRAM, DDR SDRAM? Ans: SDRAM stands for synchronous dynamic random access memory where as DDR SDRAM stands for double data rate synchronous dynamic random access memory. Both SDRAM and DDR SDRAM can be differentiate by the factor speed i.e. DDR SDRAM transfer data roughly twice the speed of SDRAM. (f) Differentiate between DRAM and SRAM in term of speed, size, and cost? Ans: Speed: DRAM (Dynamic Ram): Access time is greater i.e slower in speed. SRAM (Static Ram): Less access time hence faster memories. Size: DRAM: less SRAM: More
  • 2. GANDHI INSTITUTE FOR EDUCATION & TECHNOLOGY FIFT SEMESTER EXAMINATION-2010 COMPUTER ARCHITECTURE & ORGANIZATION FULL MARK: 70 TIME: - 3HOURS Prepared by: Asst.Prof. Santosh Kumar Rath (CSE DEPARTMENT) Page 2 Cost: DRAM: Less SRAM: More (g) Define seek time? Ans: seek time is a measure of the amount of time required for the read/write head to move between tracks over the surface of platter. (h)What do you understand by exponent overflow? Ans: Overflow is an exponent to IEEE standard when representation of floating point number. Exponent overflow means exponent is having a value which is too larger i.e size is more than the register size. (i) IS ROM a RAM? Why? Ans: ROM is not a RAM because ROM is non-volatile in nature where as RAM is volatile in nature so A ROM cannot be a RAM. (j) Differentiate between horizontal and vertical microprogramming? Ans: A horizontal microprogramming requires a larger micro programmed memory but a vertical microprogramming require more encoding and decoding of signal, hence time to access leads to slower operation. 2) A) List the different cache mapping techniques? Explain any one of them? Ans: Three types of mapping procedures are there? (1) Associative Mapping-The fastest and most flexible cache organizations uses associative mapping. The associative memory stores both the address and content of memory word. This permits any location in cache to store word in main memory. (2) Direct Mapping-Associative memories are expensive compared to RAM's because of added logic associated with each cell. (3) Set Associative Mapping-It is a more general method that includes pure associative and direct mapping as special case. It is an improvement over the direct mapping organization in that each word of cache can store two or more words of memory under the same index address. Each data word is stored together with its tag and the number of tag data items in one word of cache is said to form a set. Direct Mapping: • Each location in RAM has one specific place in cache where the data will be held. • Consider the cache to be like an array. Part of the address is used as index into the cache to identify where the data will be held.
  • 3. GANDHI INSTITUTE FOR EDUCATION & TECHNOLOGY FIFT SEMESTER EXAMINATION-2010 COMPUTER ARCHITECTURE & ORGANIZATION FULL MARK: 70 TIME: - 3HOURS Prepared by: Asst.Prof. Santosh Kumar Rath (CSE DEPARTMENT) Page 3 • Since a data block from RAM can only be in one specific line in the cache, it must always replace the one block that was already there. There is no need for a replacement algorithm. B) a two way set associative cache memory uses block of four word. The caches can accommodate a total of 2048 word from main memory. The main memory size is 128K * 32. What is the size of cache memory? Ans: Given – Two ways set associative mapping Number of blocks in a set =2 Main memory size = 128 K* 32 Cache Memory block size = 4 words Total no of blocks= no of words/ cache memory block size= 2048/4=512 No of set= size of cache in block/no of block in a set=512/2=256 Size of cache memory= 2048/4=512 blocks. 3) A) Explain the different types of ROM? Explain the advantages and disadvantages? Ans: ROM stands for Read Only Memory which is non-volatile in nature. Read Only Memory is physical memory that is not-volatile, meaning, if there is not electricity, the memory is not lost. ROMs are used to put programs which start hardware components. and good example of this is the BIOS on your computer. these types of software are called firmware. ROMs server their purpose, but have their limitations because once you burn the information into a ROM chip, it cannot be charged, that is why they come up with new types of ROMs there are three PROM: Programmable read-only memory - on this type of memory, you can write into just once, you cannot erase the data once you store it in a PROM EPROM: Erasable Programmable read-only memory - on this type of memory you can erase the whole data and rewrite with a new one. Meaning, you have to erase the everything and put new data, but you cannot keep any of the old data once you override it with the new one - BIOS and CMOS use EPROM EEPROM: Electronically Erasable Programmable read-only memory - on this type of ROM you can edit/modify the data and still keep your data. as you can see from the image above, all these chips look alike, the difference in the internal circuitry. Some examples of these chips on computers are the computer CMOS and BIOS. also the difference in these chips are the prices. EEPROMs are more expensive then ROM chips
  • 4. GANDHI INSTITUTE FOR EDUCATION & TECHNOLOGY FIFT SEMESTER EXAMINATION-2010 COMPUTER ARCHITECTURE & ORGANIZATION FULL MARK: 70 TIME: - 3HOURS Prepared by: Asst.Prof. Santosh Kumar Rath (CSE DEPARTMENT) Page 4 B) Explain the mechanism of virtual memory: Ans: if your computer lacks the random access memory (RAM) needed to run a program or operation, Windows uses virtual memory to compensate. Virtual memory combines your computer’s RAM with temporary space on your hard disk. When RAM runs low, virtual memory moves data from RAM to a space called a paging file. Moving data to and from the paging file frees up RAM to complete its work. The purpose of virtual memory is to enlarge the address space, the set of addresses a program can utilize. For example, virtual memory might contain twice as many addresses as main memory. A program using all of virtual memory, therefore, would not be able to fit in main memory all at once. Nevertheless, the computer could execute such a program by copying into main memory those portions of the program needed at any given point during execution. Virtual Memory Advantages --------------------------------- You can run more applications at once. You can run larger applications with less real RAM. Applications may launch faster because of File Mapping. You don't have to buy more memory (RAM). Virtual Memory Disadvantages --------------------------------- Applications run slower. It takes more time to switch between applications. Less hard drive space for your use. Reduced system stability 4) A) List the four alternative methods of rounding the result of floating point operation. Ans: Rounding Mode: this floating point format support four different modes. 1) Round to Zero: This result closest to zero is returned. Nothing is added to the least significant bit. This is equivalent to truncation. 2) Round Up: The more positive result closest to the infinity precise result is returned. If the result is +ve and either the strictly bit is 1, the result is
  • 5. GANDHI INSTITUTE FOR EDUCATION & TECHNOLOGY FIFT SEMESTER EXAMINATION-2010 COMPUTER ARCHITECTURE & ORGANIZATION FULL MARK: 70 TIME: - 3HOURS Prepared by: Asst.Prof. Santosh Kumar Rath (CSE DEPARTMENT) Page 5 rounded. if the result is –ve , the result is not rounded because the un rounded result is the most + ve result closest to the precise result. 3) Round Down: in this case more –ve result is returned. If the result is –ve and either the sickly bit is 1, 1 is added to the least significant bit. If the result is +ve nothing is added to the least significant bit. 4) Round to Nearest: This result closest to the infinitely precise result is returned. If the undelivered bit below the LSB, have a significance of more than half the LSB. If the result is exactly half, 1 is added if the LSB is 1. B) What are steps for floating point division. Ans: A floating point division operation mostly follows 3 steps. Step 1: Subtract exponent and add bias. The bias value is 127 in case of single precision number and 1023 in case of double precision number. Step 2: Divide the mantissa and determine the sign result. Step 3: Normalize the data. 5) A) write an algorithm for signed operand multiplication using booth algorithm. Ans: Register used in Booths algorithm: A->Accumulator (initially Zero)
  • 6. GANDHI INSTITUTE FOR EDUCATION & TECHNOLOGY FIFT SEMESTER EXAMINATION-2010 COMPUTER ARCHITECTURE & ORGANIZATION FULL MARK: 70 TIME: - 3HOURS Prepared by: Asst.Prof. Santosh Kumar Rath (CSE DEPARTMENT) Page 6 M-> Multiplicand Q-> Multiplier SC -> Sequential Counter (No’s of bits present in Q Register) This process is continuing till the sequential counter becomes Zero. The result is stored in Register A and Q. Example: B) Represent 0.5 in IEEE 754 single precision format. Ans: Step 1: Convert decimal number to binary format 0.5 * 2= 1.0 0.1 Step 2: Normalize the number 0.1 * 2-1 Single Precision – For the above given number S=0, E =-1, M=0 Bias for the single precision format is given by 127. So E1 =E +127 =-1 +127 =(126)10= (01111110)2 Number in single precision format is given as 0 01111110 0 Sign bit Exponent Mantissa
  • 7. GANDHI INSTITUTE FOR EDUCATION & TECHNOLOGY FIFT SEMESTER EXAMINATION-2010 COMPUTER ARCHITECTURE & ORGANIZATION FULL MARK: 70 TIME: - 3HOURS Prepared by: Asst.Prof. Santosh Kumar Rath (CSE DEPARTMENT) Page 7 6 A) Explain the different type of Addressing Modes? Ans: Addressing modes are an aspect of the instruction set architecture in most central processing unit (CPU) designs. The various addressing modes that are defined in a given instruction set architecture define how machine language instructions in that architecture identify the operand (or operands) of each instruction. An addressing mode specifies how to calculate the effective memory address of an operand by using information held in registers and/or constants contained within a machine instruction or elsewhere. Types of Addressing Modes Each instruction of a computer specifies an operation on certain data. The are various ways of specifying address of the data to be operated on. These different ways of specifying data are called the addressing modes. The most common addressing modes are:  Immediate addressing mode  Direct addressing mode  Indirect addressing mode  Register addressing mode  Register indirect addressing mode  Displacement addressing mode  Stack addressing mode To specify the addressing mode of an instruction several methods are used. Most often used are: a) Different operands will use different addressing modes. b) One or more bits in the instruction format can be used as mode field. The value of the mode field determines which addressing mode is to be used. The effective address will be either main memory address of a register. Immediate Addressing: This is the simplest form of addressing. Here, the operand is given in the instruction itself. This mode is used to define constant or set initial values of variables. The advantage of this mode is that no memory reference other than instruction fetch is required to obtain operand. The disadvantage is that the size of the number is limited to the size of the address field, which most instruction sets is small compared to word length. INSTRUCTION OPERAND Direct Addressing: In direct addressing mode, effective address of the operand is given in the address field of the instruction. It requires one memory reference to read the operand from the given location and provides only a limited address space. Length of the address field is usually less than the word length. Ex : Move P, Ro, Add Q, Ro P and Q are the address of operand. Indirect Addressing: Indirect addressing mode, the address field of the instruction refers to the address of a word in memory, which in turn contains the full length
  • 8. GANDHI INSTITUTE FOR EDUCATION & TECHNOLOGY FIFT SEMESTER EXAMINATION-2010 COMPUTER ARCHITECTURE & ORGANIZATION FULL MARK: 70 TIME: - 3HOURS Prepared by: Asst.Prof. Santosh Kumar Rath (CSE DEPARTMENT) Page 8 address of the operand. The advantage of this mode is that for the word length of N, an address space of 2N can be addressed. He disadvantage is that instruction execution requires two memory reference to fetch the operand Multilevel or cascaded indirect addressing can also be used. Register Addressing: Register addressing mode is similar to direct addressing. The only difference is that the address field of the instruction refers to a register rather than a memory location 3 or 4 bits are used as address field to reference 8 to 16 generate purpose registers. The advantages of register addressing are Small address field is needed in the instruction. Register Indirect Addressing: This mode is similar to indirect addressing. The address field of the instruction refers to a register. The register contains the effective address of the operand. This mode uses one memory reference to obtain the operand. The address space is limited to the width of the registers available to store the effective address. Displacement Addressing: In displacement addressing mode there are 3 types of addressing mode. They are: 1) Relative addressing 2) Base register addressing 3) Indexing addressing. This is a combination of direct addressing and register indirect addressing. The value contained in one address field. A is used directly and the other address refers to a register whose contents are added to A to produce the effective address. Stack Addressing: Stack is a linear array of locations referred to as last-in first out queue. The stack is a reserved block of location, appended or deleted only at the top of the stack. Stack pointer is a register which stores the address of top of stack location. This mode of addressing is also known as implicit addressing. B) Explain the Addressing Mechanism in Big-Endian and Little- Endian format with example? Ans: There are two scheme used to assign the memory location for storing multi byte data.1) Big-Endian Scheme II) Little-Endian scheme. Big- Endian is the order in which big end (MSB) is stored first (at lowest storage address) Little-Endian is an order in which the ‘little end (LSB) is stored first. Word Address Byte Address Big-Endian 0 1 2 3 4 5 6 7 2k-4 2k-3 2k-2 2k-1
  • 9. GANDHI INSTITUTE FOR EDUCATION & TECHNOLOGY FIFT SEMESTER EXAMINATION-2010 COMPUTER ARCHITECTURE & ORGANIZATION FULL MARK: 70 TIME: - 3HOURS Prepared by: Asst.Prof. Santosh Kumar Rath (CSE DEPARTMENT) Page 9 Word Address Byte Address Little-Endian 7) A) Explain the instruction execution cycle step by step? Ans: The time period during which one instruction is fetched from memory and executed when a computer is given an instruction in machine language. There are typically four stages of an instruction cycle that the CPU carries out: 1. Fetch the instruction from memory. This step brings the instruction into the instruction register, a circuit that holds the instruction so that it can be decoded and executed. 2. Decode the instruction. 3. Read the effective address from memory if the instruction has an indirect address. 4. Execute the instruction. Steps 1 and 2 are called the fetch cycle and are the same for each instruction. Steps 3 and 4 are called the execute cycle and will change with each instruction. The term refers to both the series of four steps and also the amount of time that it takes to carry out the four steps. An instruction cycle also is called machine cycle. B) Convert the arithmetic expression: A* b + A *(B*D+C*E) into reverse polish notation. Ans: Symbol Scanned Stack Expression A ( A * ( * A B ( * A B + ( + A B * A ( + A B * A * ( + A B * A ( ( + * ( A B * A B ( + * ( A B * A B * ( + * ( A B * A B D ( + * ( A B * A B D + ( + * ( + A B * A B D C ( + * ( + A B * A B D C 3 2 1 0 7 6 5 4 2k-1 2k-2 2k-3 2k-4
  • 10. GANDHI INSTITUTE FOR EDUCATION & TECHNOLOGY FIFT SEMESTER EXAMINATION-2010 COMPUTER ARCHITECTURE & ORGANIZATION FULL MARK: 70 TIME: - 3HOURS Prepared by: Asst.Prof. Santosh Kumar Rath (CSE DEPARTMENT) Page 10 * ( + * ( + A B * A B D * C E ( + * ( + A B * A B D * C E ) ( + * ( + ) A B * A B D * C E + * + 8 A) write short notes on any two. a) Virtual memory b) Micro programmed Control c) Segmentation Ans: a) Virtual memory: Virtual memory is a feature of an operating system that enables a process to use a memory (RAM) address space that is independent of other processes running in the same system, and use a space that is larger than the actual amount of RAM present, temporarily relegating some contents from RAM to a disk, with little or no overhead. Virtual memory is a technique that allows processes that may not be entirely in the memory to execute by means of automatic storage allocation upon request. The term virtual memory refers to the abstraction of separating LOGICAL memory--memory as seen by the process--from PHYSICAL memory--memory as seen by the processor. Because of this separation, the programmer needs to be aware of only the logical memory space while the operating system maintains two or more levels of physical memory space. The virtual memory abstraction is implemented by using secondary storage to augment the processor's main memory. Data is transferred from secondary to main storage as and when necessary and the data replaced is written back to the secondary storage according to a predetermined replacement algorithm. If the data swapped is designated a fixed size, this swapping is called paging; if variable sizes are permitted and the data is split along logical lines such as subroutines or matrices, it is called segmentation. b) Micro programmed Control: While executing a program, the microprocessor needs to access memory frequently to read instruction codes and data stored in memory and the interfacing circuit enables that access. The primary function of memory interfacing is to allow the microprocessor to read from and write into a given register of memory chip. 1. Be able to select the chip 2. Identify the register 3.Enable the appropriate buffer. c) Segmentation: A segment can be defined as a logical grouping of instruction. - Segmentation is a techniques used to handled different problem of different size and different logical structure. - In this case, a small program is divided into a number of logical parts, each individual logical parts are known as a segment.