COMEDI: Combinatorial Election of Diagnostic Vectors From Detection Test Sets for Logic Circuits
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The document describes a novel technique called COMEDI that selects diagnostic test vectors from a pool of ATPG detection vectors to identify faults in chips during manufacturing testing. COMEDI constructs a combinatorial cover of the detection vector pool to determine a test set with high diagnostic coverage without using diagnostic test generation, circuit modification, or miter-based approaches. Experimental results on benchmark circuits show the method effectively reduces the size of the diagnostic test set while achieving high diagnostic coverage and requiring less CPU time compared to existing techniques. The proposed architecture is analyzed using Xilinx 14.2 in terms of logic size, area, and power consumption.
COMEDI: Combinatorial Election of Diagnostic Vectors From Detection Test Sets for Logic Circuits
- 1. COMEDI: Combinatorial Election of Diagnostic Vectors From Detection Test Sets for Logic Circuits ABSTRACT: Although the modern automatic test pattern generation (ATPG) tools can efficiently produce near-optimal test sets with high fault-coverage for a circuit- under-test, a diagnostic test set (DTS), which is needed for fault localization, is much more challenging to construct. The DTS is used to analyze the responses of failing chips during manufacturing test for the purpose of identifying the root cause of observed errors. In this paper, a novel technique for selecting a powerful DTS for stuck-at faults from a pool of ATPG detection vectors is proposed. Unlike existing methods, this technique does not use any diagnostic test generation, circuit modification, or miter-based approach. It constructs a combinatorial cover of the pool to determine a test set with high diagnostic coverage (DC). Two variants of the covering algorithm are proposed based on this technique. The experimental results on several combinational and scan-based benchmark circuits demonstrate the effectiveness of our method in terms of the size of the DTS, DC, and CPU time.The proposed architecture of this paper analysis the logic size, area and power consumption using Xilinx 14.2.
- 2. SOFTWARE IMPLEMENTATION: Modelsim Xilinx ISE