computer organisation unit 3 presentatio

COMPUTER ORGANIZATION
By
Ch.B.A.Raju
Associate Professor
Dept of Electrical and Electronics Engineering
School of Engineering
Aditya University
Surampalem.
ADITYA ENGINEERING COLLEGE(A)

Unit – III Central Processing Unit: General Register
Organization, STACK Organization. Instruction Formats,
Addressing Modes, Data Transfer and Manipulation, Program
Control, Reduced Instruction Set Computer.
Microprogrammed Control: Control Memory, Address
Sequencing, Micro Program example, Design of Control Unit.
Thursday, November 28, 2024
Aditya Engineering College (A)

Central Processing Unit
 The part of computer that do data processing operations is
called central processing unit (CPU) The CPU is made of 3
parts:
 1. Registers: stores intermediate data generated during
execution
 2. ALU: performs required micro operations
 3. Control Unit: controls transfer of data among registers
and instruct ALU to perform correct operation
Aditya Engineering College (A)
Thursday, November 28, 2024
COMPUTER ORGANIZATION Ch.B.A.Raju Associate Professor

 General Register Organization Intermediate data are needed to
be stored like pointers, counters, return address, temp results,
and partial products.
 Cannot save them in main memory because their access is
time consuming. It is more efficient and faster to be stored
inside processor. So the solution is designing multiple
registers inside processor and connects them through a
common bus.
 In Basic Computer, there is only one general purpose register,
the Accumulator (AC) but in modern CPUs, there are many
general purpose registers. It is advantageous to have many
registers Transfer between registers within the processor are
relatively fast. Going “off the processor” to access memory is
much slower.
Ch.B.A.Raju Associate Professor

 BUS SYSTEM
 A new bus organization will be introduced in order to clarify the idea of
register banking and how to control their actions.
 7 CPU registers that their outputs are connected to 2 MUX 8 X 1 to form
the 2 buses A and B.
 The A and B are inputted to ALU unit in which its operation is selected by
their select lines among different arithmetic and logic operations.
 The resulted ALU data can is directed to the input of all 7 registers which
one of them will be selected according to 3 X 8 decoder connected to LD
inputs of the registers

For example to perform operation R1 ←R2 + R3 MUXA select R2 , MUXB
select R3 , OPR in ALU operation for ADD , SELD to direct destination
register R1. These four control signals are generated in control unit in start
of each clock cycle ensuring operands are selected beside correct ALU
operation and result is chosen in one clock cycle only.

 CONTROL WORD
 There are 14 selection inputs in the unit and their combined value specifies
control word.
 bits to select A source, 3 bits to select B source, 5 bits to select operation
required on them, and finally 3 bits to select destination register. Encoding
of 3 bits for selection of the 2 sources plus the destination is defined in
next table. While the other table specifies ALU operations encoding.
 ALU ALU provides
 arithmetic operations (ADD, SUB, INCA, DECA)
 Logic operations (AND, OR, XOR, COMA)
 Shift operations (SHLA SHRA).
 And Transfer operation (TSFA)

• EXAMPLES

 Stack Organization
 Stack is a storage device that stores information in a way that the item is
stored last is the first to be retrieved (LIFO).
 Stack in computers is actually a memory unit with address register (stack
pointer SP) that can count only. SP value always points at top item in
stack.
 The two operations done on stack are PUSH (Push Down), operation of
insertion of items into stack POP (Pop Up), operation of deletion item from
stack Those operation are simulated by INC and DEC stack register (SP).

1. Register stack
A stand alone unit that consists of collection of finite number of registers. 64
location stack unit with SP that stores address of the word that is currently on the
top of stack.
3 items are placed in the stack A, B, and C. Item C is in top of stack so that SP
holds 3 which the address of item C. To remove top item from stack (popping
stack) we start by reading content of address 3 and decrementing the content of
SP. Item B is now in top of stack holding address 2. To insert new item (pushing
the stack) we start by incrementing SP then writing a new word where SP now
points to (top of stack).

 in 64 word stack we need to have SP of 6 bits only (from 000000 to
111111). If 111111 is reached then at next push SP will be 000000, that is
when the stack is FULL. Similarly when SP is 000001 then at next pop SP
will go to 000000 that is when the stack is EMTY. Initially, SP = 0,
EMPTY = 1, FULL =0 .
 Procedures for pushing stack
 SP ←SP + 1
 M[SP] ←DR
 IF (SP = 0) THEN (FULL = 1) EMTY ←0
 1. Always we use DR to pass word into stack
 2. M[SP] memory word specified by address currently in SP
 3. First item stored in stack is at address 1
 4. Last item stored in stack is at address 0. That is FULL = 1
 5. Any push to stack means EMTY = 0

 Procedures for popping stack
 DR ←M[SP]
 SP ←SP – 1
 IF (SP = 0) THEN (EMTY = 1)
 FULL ←0
 Note: 1. Top of stack is read into DR
 2. If SP reached 0 then stack is EMTY = 1. That when SP was 1 then pop
occurred. No more pops can happen from here.
 3. Any pop from stacks means FULL = 0

 Memory Stack :
 Stack can be implemented in RAM memory attached to CPU.
 Only by assigning special part of it for stack operations.
 Next figure shows of main memory divided into program, data, and stack.
 PC points to next instruction in instruction part
 AR points to array of data of operands
 SP points to top of stack
 All are connected to common address bus Stack grows (pushed) with
decreasing address and empties (pops) with increasing address.
 New item is inserted with push operation by decrementing SP then a write to
SP address is done.
 SP ←SP -1
 M [SP] ←DR
 Last item is removed from stack with pop operation by removing item by
reading from memory location addressed by SP then SP is incremented.
 DR ←M [SP]
 SP ←SP + 1

initial value of SP is 4001 and first item when pushed in stack stores at address
4000 and second one stores at address 3999. The last address pushed into will
be 3000. (See limitation danger?)
Most computers are not supported by hardware to sense stack overflow and
underflow. But can be implemented by saving the 2 limits in 2 registers.
After each push or pop the SP is compared with the limit to see if stack has
reached its limits. So must be taking care of using software.

Instruction Format
The Instruction coding fields in today’s computers follow the next format
1. Operation code field to specify operation
2. Address field that specifies operand address field or register
3. Mode field to specify effective address In general, most processors are
organized in one of 3 ways
Single register (Accumulator) organization
Basic Computer is a good example
Accumulator is the only general purpose register
General register organization
Used by most modern computer processors
Any of the registers can be used as the source or destination for computer
operations

Stack organization
All operations are done using the hardware stack
For example, an OR instruction will pop the two top elements from the
stack, do a logical OR on them, and push the result on the stack
The number of address fields in the instruction format depends on the
internal organization of CPU. The three most common CPU organizations:

computer organisation unit 3 presentatio

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computer organisation unit 3 presentatio