Computer Organization Unit 3 Computer Fundamentals

3.2. Operation and Operands of Computer Hardware Instruction
Arithmetic in MIPS: Every Computer Must Perform Arithmetic, and MIPS Assembly Follows A Structured Format.
General Format:
Add A, B, C
Adds The Values of B And C.
Stores The Result in A.
MIPS Syntax Example:
ADD $s1, $s2, $s3
Adds the values stored in registers $s2 and $s3.
The result is placed in register $s1
Registers and Variables:
$s1 = variable a
$s2 = variable b
$s3 = variable c
Microprocessor without Interlocked Pipeline Stages
(MIPS)

MIPS Operands
Every arithmetic operation in MIPS
has exactly 3 operands.
Keeps Hardware Simple: This
standard format simplifies the
design of the processor.
Efficiency: Simpler hardware allows
for faster and more reliable
execution.

Compiling Two C Assignment Statements into MIPS
This segment of a C program contains the five variables a, b, c, d, and e.
Since Java evolved from C, this example and the next few work for
either high-level programming language:
Answer
A MIPS instruction operates on two source operands and places the
result in one destination
operand.
Hence, the two simple statements above compile directly into these two
MIPS assembly language instructions:
Compiling a complex C Assignment into MIPS
A somewhat complex statement contains the five variables
f, g, h, i, and j:
Answer

MIPS Primarily Uses Three Types of Operands:
 Registers,
 Immediate Values
 Memory Addresses
Registers (Register Operands)
Registers are the fastest way to access data in MIPS because they are built into the CPU.
MIPS has 32 general-purpose registers (each 32-bits wide).
Register names typically start with a $ symbol, and there are several types of registers:
$t0 - $t9: Temporary registers
$s0 - $s7: Saved registers
$zero: Constant register that always holds the value 0.
$a0 - $a3: Argument registers (used for passing function arguments).
$v0 - $v1: Value registers (used for returning function results).
$sp: Stack pointer.
$ra: Return address register.
ADD $t0, $t1, $t2
Example
Adds the values in registers $t1 and $t2, and
stores the result in $t0

Immediate Operands
Immediate values are constants directly encoded in the instruction. These are often used in arithmetic or logic operations
where one operand is a constant number.
Immediate instructions are shorter because the operand is embedded within the instruction itself (usually 16 bits).
ADDI $t0, $t1, 5 Adds the value 5 (immediate) to the value in $t1, and stores the result in $t0
Memory Operands
MIPS follows a load/store architecture, meaning arithmetic operations cannot be directly performed on data in memory.
Instead, you must first load the data from memory into a register, perform operations, and then store the result back
to memory.
LW: Load word (loads data from memory to a register).
SW: Store word (stores data from a register to memory)
LW $t0, 0($t1) # Load the word at memory address $t1 + 0 into $t0
SW $t0, 4($t1) # Store the value in $t0 into memory at $t1 + 4

3.3.INSTRUCTION SET ARCHITECTURE (ISA)
 Operand Access: Addressing methods access memory locations and registers.
 Basic Concepts: Focus on general machine instructions and addressing methods used in processors.
 Assembly-Level Programming: Instructions and addressing methods are symbolically represented.
 Instruction Set Architecture (ISA): Complete instruction set + operand addressing methods = ISA.
 High-Level Languages: Most programs written in C, C++, Java.
 Compilation: High-level code is compiled into machine language to run on processors.
 Assembly Language: A human-readable form of machine language.

Memory Locations and Addressing
Memory Structure:
 Memory is made up of millions of storage cells.
 Each cell holds a bit (either 0 or 1).
Handling Data:
 Bits are usually grouped together because a single bit
holds very little information.
 Data is handled in groups called words.
Word Length:
 A word is a fixed group of n bits.
 The word length (n) is the number of bits in a word,
typically ranging from 16 to 64 bits in modern computers.
Example:
 If a word length is 32 bits, it can store:
 A 32-bit signed number. Or 4 ASCII characters, where
each character is 8 bits (1 byte).

Bytes and Words:
 A byte is a group of 8 bits.
 Words can contain multiple bytes (e.g., a 32-bit word
contains 4 bytes).
Memory Addressing:
 Each memory location (byte or word) has a unique
address.
 The total number of addresses is defined by the
formula 2^k, where k is the number of bits in the
address.
Example:
If a computer has a 24-bit address, it can access 2^24 =
16M (16 million) memory locations.
If a computer has a 32-bit address, it can access 2^32 =
4G (4 billion) locations.

Byte Addressability
 A byte is always 8 bits, while a word can range from 16 to 64 bits.
 Assigning individual addresses to bits is impractical, so modern computers use byte-addressable memory, where
each byte has a unique address (0, 1, 2, ...).
 For a 32-bit word (4 bytes), words are located at addresses like 0, 4, 8, ....
 Each word consists of 4 consecutive bytes, making memory access efficient.
 Big-endian is an order in which the "bigend" (most significant value in the sequence) is stored first (at the lowest
storage address).
 Little-endian is an order in which the “Little end" (least significant value in the sequence) is stored first (at the lowest
storage address).
Big-Endian and Little-Endian Assignments

Computer Organization Unit 3 Computer Fundamentals

Little Endian (e.g., in DEC, Intel)
» low order byte stored at lowest address
» byte0 byte1 byte2 byte3
Eg: 46,78,96,54 (32 bit data)
• H BYTEL BYTE
• 8000
• 8001
• 8002
• 8003
• 8004
54
96
78
46
|

Word Alignment
Word alignment occurs when a word's starting byte address is a multiple of the word's length
Word length is typically a power of 2 for ease of binary address manipulation.
For a 16-bit word (2 bytes), aligned addresses are 0, 2, 4, ...
Words can technically start at any byte address (unaligned), but aligned addresses are preferred for better memory access
efficiency

3.4 INSTRUCTION AND INSTRUCTION SEQUENCING
Instruction: is command to the microprocessor to perform a given task on specified data.
Instruction Set: The entire group of these instructions are called instruction set.
Instruction Sequencing : The order in which the instructions in a program are carried out.
A computer must have instructions capable of performing 4 types of operation
Data transfer between memory and processor register
Arithmetic and logic operation
 Program sequencing and control
I/O transfer

Register Transfer Notation (RTN)
The possible locations in which transfer of information occurs are:
1) Memory-location
2) Processor register
3) Registers in I/O device

Data Transfer Instructions
They are also called copy instructions.
Some instructions in 8086:
MOV -Copy from the source to the destination
LDA - Load the accumulator
STA - Store the accumulator
PUSH - Push the register pair onto the stack
POP - Pop off stack to the register pair

Data Manipulation Instructions
To perform the operations by the ALU
Three categories:
Arithmetic Instructions
Logical and bit manipulation instructions
Shift instructions
INC Increment the data by 1
🡺
DEC Decreases data by 1
🡺
ADD perform sum of data
🡺
ADC Add with carry bit.
🡺
MUL perform multiplication
🡺
AND bitwise AND operation
🡺
OR bitwise AND operation
🡺
NOT invert each bit of a byte or word
🡺
XOR Exclusive-OR operation over each bit
🡺
SHR shift bits towards the right and put zero(S) in MSBs
🡺
ROL rotate bits towards the left, i.e. MSB to LSB and to
🡺
Carry Flag [CF]
RCL rotate bits towards the left, i.e. MSB to CF and CF to
🡺
LSB.
Arithmetic Instructions Logical and bit manipulation instructions
Shift instructions

Evaluate (A+B) * (C+D)
Using Zero-Address instruction
1. PUSH A ; TOS ← A
2. PUSH B ; TOS ← B
3. ADD ; TOS ← (A + B)
4. PUSH C ; TOS ← C
5. PUSH D ; TOS ← D
6. ADD ; TOS ← (C + D)
7. MUL ; TOS ← (C+D)*(A+B)
8. POP X ; M[X] ← TOS
Using One-Address Instruction
1. LOAD A ; AC ← M[A]
2. ADD B ; AC ← AC + M[B]
3. STORE T ; M[T] ← AC
4. LOAD C ; AC ← M[C]
5. ADD D ; AC ← AC + M[D]
6. MUL T ; AC ← AC * M[T]
7. STORE X ; M[X] ← AC

Evaluate (A+B) * (C+D)
Using Two address Instruction:
1. MOV R1,A ; R1=M[A]
2. ADD R1,B ;R1=R1+M[B]
3. MOV R2,C ;R2=M[C]
4. ADD R2,D ;R2=R2+M[D]
5. MUL R1,R2 ; R1=R1*R2
6. MOV X,R1 ; M[X]=R1
Using Three address Instruction
1. ADD R1,A,B ;R1=M[A]+M[B]
2. ADD R2,C,D ;R2=M[C]+M[D]
3. MUL X,R1,R2 ;M[X]=R1*R2

3.5 ADDRESSING MODES
Different ways in which the location of the operand is specified in an instruction is referred as addressing modes.
The purpose of using addressing mode is:
 To give the programming versatility to the user.
 To reduce the number of bits in addressing field of instruction.
Types of Addressing Modes
1. Immediate Addressing
2. Direct Addressing
3. Indirect Addressing
4. Register Addressing
5. Register Indirect Addressing
6. Relative Addressing
7. Indexed Addressing
8. Auto Increment
9. Auto Decrement

Immediate Addressing
e.g. ADD 5
 Add 5 to contents of accumulator
 5 is operand
Direct Addressing
e.g. ADD A
Add contents of cell A to accumulator
Look in memory at address A for operand
Indirect Addressing
e.g. ADD (A)
Add contents of cell pointed to by contents of A to the
accumulator (Effective Address )

Register Direct Addressing
Eg: ADD R will increment the value stored in the
accumulator by the content of register R.
AC ← AC + [R]
Register Indirect Addressing
ADD R will increment the value stored in the
accumulator by the content of memory location
specified in register R.
AC ← AC + [[R]]

Indexed Addressing
Effective Address = Content of Index Register +
Address part of the instruction
Relative Addressing
Effective Address = Content of Program
Counter + Address part of the instruction

Auto Increment Mode Auto Decrement Mode
Effective Address of the Operand = Content of Register
Effective Address of the Operand
= Content of Register – Step Size

UNIT IV PROCESSOR
Instruction Execution
Building Data Path
Designing a Control Unit
 Hardwired Control
 Microprogrammed Control
Pipelining
Data Hazard
Control Hazards.

Instruction Execution
The process by which the CPU retrieves, decodes, and executes instructions stored in a
program to perform various tasks.
This process is fundamental in ensuring the CPU can execute programs written in
machine code or assembly language.
Key Components:
Control Unit (CU): Directs the operation of the processor, decodes instructions, and
controls the flow of data.
Arithmetic Logic Unit (ALU): Performs arithmetic operations (e.g., addition,
subtraction) and logical comparisons (e.g., AND, OR).
Registers: Small, fast storage areas that hold data temporarily.

Phases of Instruction Execution
Fetch Phase:
The CPU retrieves the next instruction from memory.
Component: Program Counter (PC) holds the memory address of the instruction. After fetching the instruction, the PC
increments to point to the next instruction.
Decode Phase:
The Control Unit (CU) decodes the fetched instruction to determine what actions need to be performed.
Components:
Opcode: The operation to be performed (e.g., ADD, SUB).
Operands: The data or memory addresses the operation will use.
Execute Phase:
The instruction is executed by the CPU, usually using the ALU.
Component: The result of the operation is either stored in a register or memory.
Store Phase (Optional to Mention):Process: After execution, the result of the instruction (if any) is stored in
memory or a register for future use.

The Instruction Cycle (with Example)
Fetch:
The instruction ADD R1, R2, R3 is fetched from memory, and the Program Counter (PC)
is incremented.
Decode:
The instruction is decoded by the CU.
Opcode: ADD (The operation is addition).
Operands: R2 and R3 are the source operands, R1 is the destination.
Execute:
The ALU performs the addition: R2 + R3.The result is stored in R1.Store:The result is
stored in the destination register, R1.
Cycle Continuity:
Once one instruction is completed, the PC points to the next instruction, and the cycle
repeats.

Building a Data Path
Datapath Element: Units used to hold and operate on data in a processor.
Examples: Instruction memory, data memory, register file, ALU, and adders.
Program Counter (PC):
Holds the address of the current instruction.
Adder:
Increments the PC by 4 to fetch the next instruction.
State Elements:
Instruction Memory: Provides instructions (read-only).
PC: A 32-bit register updated every clock cycle.

Building a MIPS Datapath
The MIPS processor datapath can be built incrementally by considering smaller subsets of instructions
first and then gradually adding more complex instructions.
This incremental approach simplifies the design and helps build a functional processor step by step.
Three types of MIPS instructions and see what the datapath look
Arithmetic and Logical Instructions:
These instructions, such as add and subtract, require the ALU and register file.
Data Transfer Instructions:
These instructions (like load and store) require access to memory for reading and writing data.
Branch Instructions:
These instructions (like beq) use the Program Counter (PC), adder for calculating the target address, and the
ALU to evaluate conditions.

R-format instructions perform arithmetic and logical operations.
Example: add $t1, $t2, $t3
The instruction adds the contents of registers $t2 and $t3 and writes the result to register $t1.
 Reading two operands from registers.
 Performing an ALU operation (like addition).
 Writing the result back into a register.
Register file
The register file is a collection of 32 general-purpose registers that hold the data used by instructions.
It provides two outputs and one input:
Outputs: Values from two registers that will be used as inputs to the ALU.
Input: A value that will be written to a register.

ALU (Arithmetic Logic Unit)
The ALU is a critical element of the datapath, responsible for performing arithmetic and logical operations.
 It accepts two 32-bit inputs from the register file.
 It produces a 32-bit output based on the operation (e.g., addition or subtraction).
 It also sets a 1-bit zero signal when the result is 0, which can be used for branch instructions (like beq).
Instruction Fetch
 The address from the PC goes to the instruction memory,
which returns the instruction.
 The PC goes to an adder which adds 4 to get the next value of
the PC; there is a separate adder dedicated to updating the PC.

We need a total of four inputs (three for register numbers and one for data) and two outputs (both for
data).
The register number inputs are 5 bits wide to specify one of 32 registers (32 = 25), whereas the data input
and two data output buses are each 32 bits wide
The ALU, which takes two 32 bit inputs and produces a 32 bit result, as well as a 1-bit signal if the result
‑ ‑
is 0. The 4-bit control signal of the ALU.
Executing R-type Instructions

Executing Load and Store Instructions
The sign extension unit is used to convert a 16-bit constant into a 32-bit constant.
Example:
In the instruction addi $R1, $R2, 20, the constant 20 is a 16-bit value.
The sign extension unit converts this 16-bit value into a 32-bit value so that it can be processed by the ALU.
ALU Input: The 32-bit extended constant is then passed to the ALU as one of the inputs for arithmetic
operations.

The shift left operation is often used in branch instructions to convert a word address (which is generally represented in
4-byte increments in MIPS architecture) into a byte address.
Example:
Instruction: BEQ $t0, $t1, 250
Here, 250 represents the offset in words for the branch target.
To calculate the actual byte address, you perform a left shift by 2:
250 << 2 = 1000
This means that the branch instruction will transfer control to the address calculated
PC = PC + 1000
BRANCH INSTRUCTIONS

The simple datapath for the MIPS architecture combines the elements required
by different instruction classes.
This datapath can execute the basic instructions
(load-store word, ALU operations, and branches) in a single clock cycle

Designing a Control Unit
These signals dictate the operation of other parts of the CPU, such as the ALU, registers, and memory.
Control signals can be categorized as:
 ALU Control Signals:
 Memory Control Signals:
 Register Control Signals:
 Instruction Set Architecture (ISA): The control unit must understand the instruction set of the CPU.
Each instruction will have specific control signals that must be generated.
 Clock Cycles: Control units work in synchronization with the clock, generating control signals based
on clock cycles to ensure proper timing for operations.
Types of Control Units
Hardwired Control :Uses fixed logic circuits (combinational logic) to produce control signals.
Faster but less flexible; modifications require redesign.
Microprogrammed Control Unit: Uses a set of stored instructions (microinstructions) to generate
control signals.
More flexible; easier to modify and implement complex instructions.

A hardwired control is a method of generating control signals with the help of Finite State Machines (FSM). It’s made in
the form of a sequential logic circuit by physically connecting components such as flip-flops, gates, and drums that
result in the finished circuit
Components
Instruction Register (IR):Stores the instruction fetched from main memory until execution is completed. Outputs opcode
bits to the instruction decoder.
Instruction Decoder: Interprets the opcode and addressing mode from the instruction register. Determines the necessary
actions to be taken based on the decoded instruction.
Step Counter: Tracks progress during instruction execution. Indicates which of the five steps is currently being carried out:
1. Instruction Fetch
2. Decode
3. Operand
4. ALU
5. Operand Store
Control Signal Generator:A combinational circuit that generates control signals based on its inputs.
Clock:Completes one clock cycle for each step of instruction execution.Synchronizes the operation of the control circuitry.
External Inputs:Acknowledge external signals such as interrupts to the control circuitry.
Conditional Signals:Assist the control unit in generating control signals for branching instructions.

Control Signal Generation Process
 The instruction to be executed is fetched from the main memory and placed in the instruction register.
 The instruction register generates the opcode, which is interpreted by the instruction decoder.
 The instruction decoder activates the corresponding INSi signal to the control circuitry based on the
decoded opcode bits.
 With each clock cycle, timing signals (T1 to T5) are activated, indicating the current step of instruction
execution.
 The control unit generates control signals based on:
1. Timing signals from the step counter.
2. Signals from the instruction decoder.
3. External signals and conditional signals.

Advantages of Hardwired Control Units
Speed: Generates control signals faster than microprogrammed control units.
Efficiency: Suitable for implementing RISC processors, which are known for their speed.
Simplicity: Works effectively with simple instructions.
Disadvantages of Hardwired Control Units
Modification Difficulty: Difficult to modify; changes in hardware require significant effort.
Complex Instructions: Not well-suited for complex instructions.
Cost: More expensive to implement or modify compared to other types.

Control signals are generated by a program that is similar to machine language programs.
Micro-programmed Control Unit
1. Control Word: A control word is a word whose individual bits represent various control signals.
2. Micro-routine: A sequence of control words corresponding to the control sequence of a machine instruction
constitutes the micro-routine for that instruction.
3. Micro-instruction: Individual control words in this micro-routine are referred to as microinstructions.
4. Micro-program: A sequence of micro-instructions is called a micro-program, which is stored in a ROM or RAM
called a Control Memory (CM).
5. Control Store: the micro-routines for all instructions in the instruction set of a computer are stored in a special
memory called the Control Store.

Instruction Fetch: The Microinstruction Address Generator fetches the instruction from the Instruction
Register (IR).
Decoding and Address Loading: It decodes the instruction from the IR to determine the starting address of
the microroutine needed to perform the operation. This starting address is loaded into the Microprogram
Counter.
Control Word Reading: The control word corresponding to the starting address of the Microprogram
Counter is read. As execution continues, the Microprogram Address Generator increments the
Microprogram Counter to read successive control words of the microroutine.
End of Microroutine: When the last microinstruction is reached, it has an "end bit" set to 1, indicating the
microroutine’s successful execution.
Repeat Cycle: After completing the microroutine, the Microprogram Address Generator returns to Step 1 to
fetch the next instruction, and the process repeats.

Pipelining
Pipeline in computer architecture is a technique that divides the processing of an instruction into
multiple stages, allowing different parts of an instruction to be processed simultaneously in different
pipeline stages.

1. Washing machine-Instruction Fetch
2. Dryer-Instruction Decode
3. Fold-Operand Fetch
4. Arrangement-Instruction Excuete
5. Stage 5-Write back/Store

Pipeline hazards are conditions that prevent the next instruction in the pipeline from
executing during its designated clock cycle.
Data Hazards
Occur when instructions that depend on the results of previous instructions use the data before it is
available.
Types:
Read After Write (RAW): Also called true dependency, it occurs when an instruction tries to read a source
operand before a previous instruction has written to it.
Write After Read (WAR): Also called anti-dependency, it occurs when an instruction writes to a destination
before a previous instruction has read it.
Write After Write (WAW): Also called output dependency, it occurs when an instruction writes to a
destination before a previous instruction has finished writing to the same destination.

Control Hazards
Occur when the pipeline makes the wrong decision on branch prediction and has to discard instructions that have
already been fetched.
Example: When a conditional branch is encountered, the pipeline cannot determine the next instruction until the
branch decision is made. If the branch is mispredicted, the pipeline must discard (flush) instructions that were fetched
based on the incorrect path.

Computer Organization Unit 3 Computer Fundamentals

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