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Coordinate Rotation-Based Low Complexity K-Means
Clustering Architecture
ABSTRACT:
In this brief, we propose a low-complexity architectural implementation of the K-
means-based clustering algorithm used widely in mobile health monitoring
applications for unsupervised and supervised learning. The iterative nature of the
algorithm computing the distance of each data point from a respective centroid for
a successful cluster formation until convergence presents a significant challenge to
map it onto a low-power architecture. This has been addressed by the use of a 2-D
Coordinate Rotation Digital Computer-based low-complexity engine for
computing the n-dimensional Euclidean distance involved during clustering. The
proposed clustering engine was synthesized using the TSMC 130-nm technology
library, and a place and route was performed following which the core area and
power were estimated as 0.36 mm2 and 9.21 mW at 100 MHz, respectively,
making the design applicable for low-power real-time operations within a sensor
node. The proposed architecture of this paper analysis the logic size, area and
power consumption using Xilinx 14.2.
SOFTWARE IMPLEMENTATION:
 Modelsim
 Xilinx ISE

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Coordinate Rotation-Based Low Complexity K-Means Clustering Architecture

  • 1. Coordinate Rotation-Based Low Complexity K-Means Clustering Architecture ABSTRACT: In this brief, we propose a low-complexity architectural implementation of the K- means-based clustering algorithm used widely in mobile health monitoring applications for unsupervised and supervised learning. The iterative nature of the algorithm computing the distance of each data point from a respective centroid for a successful cluster formation until convergence presents a significant challenge to map it onto a low-power architecture. This has been addressed by the use of a 2-D Coordinate Rotation Digital Computer-based low-complexity engine for computing the n-dimensional Euclidean distance involved during clustering. The proposed clustering engine was synthesized using the TSMC 130-nm technology library, and a place and route was performed following which the core area and power were estimated as 0.36 mm2 and 9.21 mW at 100 MHz, respectively, making the design applicable for low-power real-time operations within a sensor node. The proposed architecture of this paper analysis the logic size, area and power consumption using Xilinx 14.2.