![F020 NOP .
. . CPU
. ( )
.
. .
.
: AR AR
R'T0: AR PC
R'T2: AR IR(0-11)
D7'IT3: AR M[AR]
RT0: AR 0
D5T4: AR AR + 1
: ( ) CLR ( ) INR ( ) LD AR
LD (AR) = R'T0 + R'T2 + D7'IT3
CLR (AR) = RT0
INR (AR) = D5T4
5](https://image.slidesharecdn.com/cpureport-100614032441-phpapp02/85/Cpu-report-5-320.jpg)
Cpu report
- 1. CPU : : 1386
- 2. 3 ............................................................................................................................ 4 ..................................................................................................................... 4 ....................................................................................................................... 4 ............................................................................................................ 5 ................................................................................................................ 5 ............................................................................................................. 8 ..................................................................................................................... 12 ................................................................................................................ IDE 13 ......................................................................................................................... 14 ................................................................................................................. 15 ........................................................................................................... 19 .......................................................................................................... math.inc 26 ....................................................................................................... display.inc 28 .......................................................................................................keypad.inc 34 .......................................................................................................................... 2
- 3. . . CPU CPU . CPU mrtofigh.googlepages.com . mrtofigh.googlepages.com/CPUDesign . 1386 3
- 4. 1 . . . OUTR INPR CPU . DR 16 AR 12 AC 16 IR 16 PC 12 TR 16 INPR 16 OUTR 16 . 16 . 15 14 12 11 0 I 15 14 12 11 0 0 1 1 1 - 15 14 12 11 0 1 1 1 1 I/O 1 Basic Computer 4
- 5. F020 NOP . . . CPU . ( ) . . . . : AR AR R'T0: AR PC R'T2: AR IR(0-11) D7'IT3: AR M[AR] RT0: AR 0 D5T4: AR AR + 1 : ( ) CLR ( ) INR ( ) LD AR LD (AR) = R'T0 + R'T2 + D7'IT3 CLR (AR) = RT0 INR (AR) = D5T4 5
- 6. . OE . (Mux ) . 6
- 7. R'T1 + D7'IT3 + (D0 + D1 + D2 + D6)T4 RD RT1 + D6T6 + (D3 + D5)T4 WR R'T1 + D7'IT3 + (D0 + D1 + D2 + D6)T4 CS (D0 + D1 + D2)T5 + pB11 + (B9+B7+B6)r LD rB5 INR AC rB11 CLR D3T4 + pB10 OE D7'IT3 + (T2 + T0)R' LD D5T4 INR AR RT0 CLR D4T4 + D5T5 OE D4T4 + D5T5 LD R'T1 + RT2 + (DR=0)D6T6 + AC15'rB4 + AC15rB3 + (AC=0)rB2 + INR E'rB1 + (FGI)pB9 + (FGO)pB8 PC RT1 CLR T0 + D5T4 OE (D0 + D1 + D2 + D6)T4 LD D6T5 INR DR D2T5 + D6T6 OE R'T1 LD IR R'T2 OE RT0 LD TR RT1 OE pB10 LD OUTR pB11 OE INR RT2 + r + p + (D0+D1+D2+D5)T5 + (D3 + D4)T4 + D6T6 CLR SC R'T1 + D7'IT3 + (D0 + D1 + D2 + D6)T4 J R RT2 K rB8 + D1T5Cout + rB7AC0 + rB6AC15 J rB8 + D1T5Cout' + rB7AC0' + rB6AC15' K E rB10 CLR pB11 CLR FGI pB10 CLR FGO 7
- 8. : Proteus 5.2 IN2 AC2 U50 OUT2 DR2 U82 TR2 PC2 IR2 U11 AR2 U2 MEM1 In8 Bus8 Bus8 AC8 AC8 Bus8 Bus8 Out8 Bus8 DR8 DR8 Bus8 Bus8 Bus8 Bus8 Bus8 Bu s8 IR8 IR8 Bus8 Bu s8 Add r8 Ad dr8 Bus8 Ad dr0 Bus0 D0 Q0 D0 Q0 A0 B0 D0 Q0 D0 Q0 A0 B0 D0 Q0 D0 Q0 D0 Q0 A0 B0 D0 Q0 A0 B0 A0 D0 In9 Bus9 Bus9 AC9 AC9 Bus9 Bus9 Out9 Bus9 DR9 DR9 Bus9 Bus9 Bus9 Bus9 Bus9 Bu s9 IR9 IR9 Bus9 Bu s9 Add r9 Ad dr9 Bus9 Ad dr1 Bus1 D1 Q1 D1 Q1 A1 B1 D1 Q1 D1 Q1 A1 B1 D1 Q1 D1 Q1 D1 Q1 A1 B1 D1 Q1 A1 B1 A1 D1 In10 Bus10 Bus10 AC10 AC10 Bus10 Bus10 Out10 Bus10 DR10 DR10 Bus10 Bus10 Bus10 Bus10 Bus10 Bu s10 IR10 IR10 Bus10 Bu s10 Add r10 Ad dr10 Bus10 Ad dr2 Bus2 In11 D2 Q2 Bus11 Bus11 D2 Q2 AC11 AC11 A2 B2 Bus11 Bus11 D2 Q2 Out11 Bus11 D2 Q2 DR11 DR11 A2 B2 Bus11 Bus11 D2 Q2 Bus11 Bus11 D2 Q2 Bus11 Bu s11 D2 Q2 IR11 IR11 A2 B2 Bus11 Bu s11 D2 Q2 Add r11 Ad dr11 A2 B2 Bus11 Ad dr3 A2 D2 Bus3 In12 D3 Q3 Bus12 Bus12 D3 Q3 AC12 A3 B3 Bus12 D3 Q3 Out12 Bus12 D3 Q3 DR12 A3 B3 Bus12 D3 Q3 Bus12 Bus12 D3 Q3 Bu s12 D3 Q3 IR12 A3 B3 Bu s12 D3 Q3 A3 B3 Ad dr4 A3 D3 Bus4 D4 Q4 D4 Q4 D4 Q4 D4 Q4 D4 Q4 D4 Q4 D4 Q4 D4 Q4 A4 D4 In13 Bus13 Bus13 AC13 Bus13 Out13 Bus13 DR13 Bus13 Bus13 Bus13 Bu s13 IR13 Bu s13 Ad dr5 Bus5 D5 Q5 D5 Q5 ATOB D5 Q5 D5 Q5 ATOB D5 Q5 D5 Q5 D5 Q5 ATOB D5 Q5 ATOB A5 D5 In14 Bus14 Bus14 AC14 Bus14 Out14 Bus14 DR14 Bus14 Bus14 Bus14 Bu s14 IR14 Bu s14 Ad dr6 Bus6 In15 D6 Q6 Bus15 Bus15 D6 Q6 AC15 OE Bus15 D6 Q6 Out15 Bus15 D6 Q6 DR15 OE Bus15 D6 Q6 Bus15 Bus15 D6 Q6 Bu s15 D6 Q6 IR15 OE Bu s15 D6 Q6 OE Ad dr7 A6 D6 Bus7 D7 Q7 D7 Q7 D7 Q7 D7 Q7 D7 Q7 D7 Q7 D7 Q7 D7 Q7 A7 D7 BUFFER_4 BUFFER_4 BUFF ER_4 BUFF ER_4 Ad dr8 A8 Clock Clo ck Clock Clo ck Clock Clo ck Clock Clock Ad dr9 UCLK MIN UCLK MIN U51 UCLK MIN UCLK MIN U83 UCLK MIN UCLK MIN UCLK MIN U10 UCLK MIN U91 Ad dr10 A9 DCLK MAX DCLK MAX AC12 Bus12 DCLK MAX DCLK MAX DR12 Bus12 DCLK MAX DCLK MAX DCLK MAX IR12 Bus12 DCLK MAX Ad dr12 Bus12 Ad dr11 A10 CNTUP RCO CNT UP RCO A0 B0 CNTUP RCO CNT UP RCO A0 B0 CNTUP RCO CNTUP RCO CNTUP RCO A0 B0 CNTUP RCO A0 B0 A11 AC13 Bus13 DR13 Bus13 IR13 Bus13 Ad dr13 Bus13 A1 B1 A1 B1 A1 B1 A1 B1 AC14 Bus14 DR14 Bus14 IR14 Bus14 Ad dr14 Bus14 OE OE AC15 A2 B2 Bus15 OE OE DR15 A2 B2 Bus15 OE OE OE IR15 A2 B2 Bus15 OE Ad dr15 A2 B2 Bus15 CS CE CE A3 B3 CE CE A3 B3 CE CE CE A3 B3 CE A3 B3 WR LOAD LOAD LOAD LOAD LOAD LOAD LOAD LOAD RD RESET RESET ATOB RESET RESET ATOB RESET RESET RESET ATOB RESET ATOB MEMORY_12_8 COUNTER_8 U185 COUNTER_8 OE COUNT ER_8 U186 COUNTER_8 OE COUNTER_8 COUNTER_8 COUNTER_8 OE COUNTER_8 OE F ILE=main.1.bin,BINARY LOWER= 0 BUFFER_4 LOWER= 0 BUFFER_4 BUFF ER_4 BUFF ER_4 U52 U85 U9 U4 MEM2 AC0 Bus0 DR0 Bus0 IR0 Bus0 Ad dr0 Bus0 Ad dr0 Bus8 IN1 AC1 AND_2 AC1 A0 A1 B0 B1 Bus1 OUT1 DR1 AND_2 DR1 A0 A1 B0 B1 Bus1 TR1 PC1 IR1 IR1 A0 A1 B0 B1 Bus1 AR1 Ad dr1 A0 A1 B0 B1 Bus1 Ad dr1 A0 A1 D0 D1 Bus9 In0 Bus0 Bus0 AC0 AC2 Bus2 Bus0 Out0 Bus0 DR0 DR2 Bus2 Bus0 Bus0 Bus0 Bus0 Bu s0 IR0 IR2 Bus2 Bu s0 Ad dr0 Ad dr2 Bus2 Ad dr2 Bus10 In1 D0 Q0 Bus1 Bus1 D0 Q0 AC1 AC3 A2 B2 Bus3 Bus1 D0 Q0 Out1 Bus1 D0 Q0 DR1 DR3 A2 B2 Bus3 Bus1 D0 Q0 Bus1 Bus1 D0 Q0 Bus1 Bu s1 D0 Q0 IR1 IR3 A2 B2 Bus3 Bu s1 D0 Q0 Ad dr1 Ad dr3 A2 B2 Bus3 Ad dr3 A2 D2 Bus11 D1 Q1 D1 Q1 A3 B3 D1 Q1 D1 Q1 A3 B3 D1 Q1 D1 Q1 D1 Q1 A3 B3 D1 Q1 A3 B3 A3 D3 In2 Bus2 Bus2 AC2 Bus2 Out2 Bus2 DR2 Bus2 Bus2 Bus2 Bus2 Bu s2 IR2 Bu s2 Ad dr2 Ad dr4 Bus12 D2 Q2 D2 Q2 D2 Q2 D2 Q2 D2 Q2 D2 Q2 D2 Q2 D2 Q2 A4 D4 In3 Bus3 Bus3 AC3 Bus3 Out3 Bus3 DR3 Bus3 Bus3 Bus3 Bus3 Bu s3 IR3 Bu s3 Ad dr3 Ad dr5 Bus13 In4 D3 Q3 Bus4 Bus4 D3 Q3 AC4 ATOB Bus4 D3 Q3 Out4 Bus4 D3 Q3 DR4 ATOB Bus4 D3 Q3 Bus4 Bus4 D3 Q3 Bus4 Bu s4 D3 Q3 IR4 ATOB Bu s4 D3 Q3 Ad dr4 ATOB Ad dr6 A5 D5 Bus14 In6 In5 D4 Q4 Bus5 Bus5 D4 Q4 AC5 OE Bus5 D4 Q4 Out5 Bus5 D4 Q4 DR5 OE Bus5 D4 Q4 Bus5 Bus5 D4 Q4 Bus5 Bu s5 D4 Q4 IR5 OE Bu s5 D4 Q4 Ad dr5 OE Ad dr7 A6 D6 Bus15 D5 Q5 D5 Q5 D5 Q5 D5 Q5 D5 Q5 D5 Q5 D5 Q5 D5 Q5 A7 D7 In6 Bus6 Bus6 AC6 BUFFER_4 Bus6 Out6 Bus6 DR6 BUFFER_4 Bus6 Bus6 Bus6 Bus6 Bu s6 IR6 BUFF ER_4 Bu s6 Ad dr6 BUFF ER_4 Ad dr8 D6 Q6 D6 Q6 D6 Q6 D6 Q6 D6 Q6 D6 Q6 D6 Q6 D6 Q6 A8 In7 Bus7 Bus7 AC7 Bus7 Out7 Bus7 DR7 Bus7 Bus7 Bus7 Bus7 Bu s7 IR7 Bu s7 Ad dr7 Ad dr9 D7 Q7 D7 Q7 U53 D7 Q7 D7 Q7 U84 D7 Q7 D7 Q7 D7 Q7 U8 D7 Q7 U5 Ad dr10 A9 AC4 Bus4 DR4 Bus4 IR4 Bus4 Ad dr4 Bus4 Ad dr11 A10 UCLK MIN UCLK MIN A0 B0 UCLK MIN UCLK MIN A0 B0 UCLK MIN UCLK MIN UCLK MIN A0 B0 UCLK MIN A0 B0 A11 AC5 Bus5 DR5 Bus5 IR5 Bus5 Ad dr5 Bus5 DCLK MAX DCLK MAX A1 B1 DCLK MAX DCLK MAX A1 B1 DCLK MAX DCLK MAX DCLK MAX A1 B1 DCLK MAX A1 B1 AC6 Bus6 DR6 Bus6 IR6 Bus6 Ad dr6 Bus6 CNTUP RCO CNT UP RCO AC7 A2 B2 Bus7 CNTUP RCO CNT UP RCO DR7 A2 B2 Bus7 CNTUP RCO CNTUP RCO CNTUP RCO IR7 A2 B2 Bus7 CNTUP RCO Ad dr7 A2 B2 Bus7 CS A3 B3 A3 B3 A3 B3 A3 B3 WR OE CE OE CE ATOB 1 OE CE OE CE ATOB OE CE OE CE OE CE ATOB OE CE ATOB RD MEMORY_12_8 1 LOAD RESET LOAD RESET OE LOAD RESET LOAD RESET OE LOAD RESET LOAD RESET LOAD RESET OE LOAD RESET OE F ILE=main.2.bin,BINARY BUFFER_4 BUFFER_4 BUFF ER_4 BUFF ER_4 COUNTER_8 COUNTER_8 U92 COUNT ER_8 COUNTER_8 U145 COUNTER_8 COUNTER_8 COUNTER_8 COUNTER_8 UPPER=255 LOWER= 0 UPPER= 255 LOWER= 0 UPPER=255 UPPER=255 UPPER=255 UPPER=255 AND_2 AND_2 UPPER=25 5 UPPER=25 5 ACis0 DRis0 U93 U70 U74 U69 U71 U90 U80 U81 U87 U40 U38 U31 U184 U43 U34 U36 U25 U26 U24 U180 U188 U187 AND_2 AND_2 OR_3 AND_2 OR_2 AND_2 AND_2 AND_2 OR_2 AND_2 AND_2 OR_2 OR_2 OR_2 AND_2 AND_2 AND_2 OR_2 AND_2 OR_2 AND_2 OR_2 . Clock U55 U77 U76 U75 U73 U72 U86 U89 U88 OR_8 U48 U42 U45 U44 U30 U29 U182 U181 AND_2 AND_2 AND_2 AND_2 AND_2 OR_4 AND_2 AND_2 AND_2 AND_2 AND_2 AND_2 U35 U37 AND_3 AND_2 AND_2 AND_2 INVERTER INVERTER U19 U7 OR_3 OR_3 U65 OR_2 U79 U78 U33 U28 OR_3 OR_3 INVERTER OR_2 U32 INVERT ER U22 U21 U20 U15 U14 U13 8 AND_2 AND_2 AND_2 AND_2 AND_3 AND_2 U64 U63 U62 U61 U60 U59 U58 U57 U56 AND_3 AND_3 AND_3 AND_3 AND_3 AND_3 AND_3 AND_2 AND_2 U23 U17 U16 OR_2 INVERT ER OR_4 U66 U68 U67 INVERT ER U18 INVERTER INVERTER INVERTER ACis 0 DRis 0 Res et AC15 AC15 FG O IR1 1 IR1 1 IR1 1 IR1 0 IR1 0 IR1 5 IR1 5 FG I IR5 IR6 IR7 IR9 IR8 IR9 IR1 IR2 IR3 IR4 D2 D1 D0 D3 D6 D6 D2 D1 D0 D2 D6 D6 D5 D5 D4 D5 D7 D5 D4 D6 D5 D3 D7 D6 D2 D1 D0 pp pp pp pp pp pp T5 T4 T5 T4 T5 T6 T1 T0 T6 T2 T1 T4 T0 T1 T5 T4 T1 T2 T4 T3 T2 T0 T0 T5 T4 T1 T6 T4 T1 T3 T4 rr rr rr rr rr rr rr R R R R R R R R R R R E IR9 IR6 IR7 D1 D0 T5 T5 rr rr rr U150 U149 U148 U147 U146 U193 A 7 8 9 AND_2 AND_2 AND_2 AND_2 AND_2 Out0 A0 B0 Out1 Out2 Out3 A1 A2 B1 B2 B 4 5 6 A3 B3 ADD1 ADD3 U118 AND3 U116 CMP3 CIL3 CIR3 Out8 ATOB C 1 2 3 DR0 10 9 ADD0 DR8 10 9 ADD8 ADD8 Bus8 AND8 Bu s8 AC8 U117 Bus8 AC7 Bus8 AC9 Bus8 OE DR1 8 A1 S1 6 ADD1 DR9 8 A1 S1 6 ADD9 ADD9 A0 B0 Bus9 AND9 A0 B0 Bu s9 AC9 U122 A0 B0 A0 B0 A0 B0 A2 S2 A2 S2 A1 B1 U94 U102 A1 B1 U123 A1 B1 Bus9 AC8 A1 B1 Bus9 AC10 A1 B1 Bus9 BUFFER_4 DR2 DR3 3 1 A3 A4 S3 S4 2 15 ADD2 ADD3 DR10 DR11 3 1 A3 A4 S3 S4 2 15 ADD10 ADD11 ADD10 ADD11 A2 A3 B2 B3 Bus10 Bus11 DR0 AND0 DR8 AND8 AND10 AND11 A2 A3 B2 B3 Bu s10 Bu s11 AC10 AC11 INVERTER INVERT ER INVERTER A2 A3 B2 B3 Bus10 Bus11 AC9 AC10 A2 A3 B2 B3 Bus10 Bus11 AC11 AC12 A2 A3 B2 B3 Bus10 Bus11 D ON C 0 = + + 1 2 3 4 AC0 11 AC8 11 AC0 AC8 AC1 7 B1 AC9 7 B1 ATOB U95 U103 ATOB INVERTER ATOB ATOB ATOB Bus15 Bus0 AC2 B2 AC10 B2 OE DR1 DR9 OE OE OE OE 4 4 AND_2 AND_2 AC3 B3 AC11 B3 AND1 AND9 16 16 BUFFER_4 BUFF ER_4 BUFFER_4 BUFF ER_4 BUFFER_4 B4 B4 AC1 AC9 U124 U119 U96 U104 AND4 CMP4 CIL4 CIR4 Se gD3 Se gD2 Se gD1 Se gD0 Se gC3 Se gC2 Se gC1 Se gC0 Se gB3 Se gB2 Se gB1 Se gB0 Se gA3 Se gA2 Se gA1 Se gA0 13 14 13 14 U125 C0 C4 C0 C4 ADD12 Bus12 DR2 DR10 AND12 Bu s12 AC12 Bus12 AC11 Bus12 AC13 Bus12 AND_2 AND_2 U127 In0 In1 In2 In3 A0 B0 A0 B0 A0 B0 A0 B0 A0 B0 7483 7483 ADD13 Bus13 AND2 AND10 AND13 Bu s13 AC13 U126 Bus13 AC12 Bus13 AC14 Bus13 A1 B1 A1 B1 A1 B1 A1 B1 A1 B1 ADD14 Bus14 AC2 AC10 AND14 Bu s14 AC14 Bus14 AC13 Bus14 AC15 AC13 Bus14 ADD15 A2 B2 Bus15 U97 U105 AND15 A2 B2 Bu s15 AC15 INVERTER A2 B2 Bus15 AC14 A2 B2 Bus15 E A2 B2 Bus15 A3 B3 DR3 DR11 A3 B3 INVERT ER A3 B3 A3 B3 A3 B3 AND_2 AND_2 AND3 AND11 INVERTER ATOB AC3 AC11 ATOB INVERTER ATOB ATOB ATOB OE U98 U106 OE OE OE OE BUFFER_4 DR4 AND_2 DR12 AND_2 BUFF ER_4 BUFFER_4 BUFF ER_4 BUFFER_4 AND4 AND12 U128 ADD2 ADD4 U121 AC4 AC12 AND1 U129 CMP1 CIL1 CIR1 DR4 10 A1 S1 9 ADD4 DR12 10 A1 S1 9 ADD12 ADD0 A0 B0 Bus0 U99 U107 AND0 A0 B0 Bu s0 AC0 U131 A0 B0 Bus0 E A0 B0 Bus0 AC1 A0 B0 Bus0 DR5 8 A2 S2 6 ADD5 DR13 8 A2 S2 6 ADD13 ADD1 A1 B1 Bus1 DR5 AND_2 DR13 AND_2 AND1 A1 B1 Bu s1 AC1 U130 A1 B1 Bus1 AC0 A1 B1 Bus1 AC2 A1 B1 Bus1 FGI_ U143 DR6 3 2 ADD6 DR14 3 2 ADD14 ADD2 Bus2 AND5 AND13 AND2 Bu s2 AC2 Bus2 AC1 Bus2 AC3 Bus2 DR7 1 A3 A4 S3 S4 15 ADD7 DR15 1 A3 A4 S3 S4 15 ADD15 ADD3 A2 A3 B2 B3 Bus3 AC5 AC13 AND3 A2 B2 Bu s3 AC3 INVERTER A2 B2 Bus3 AC2 A2 B2 Bus3 AC4 A2 B2 Bus3 U175 0 J Q U174 0 J Q U100 U108 A3 B3 INVERT ER A3 B3 A3 B3 A3 B3 K SET !Q K SET !Q AC4 11 AC12 11 DR6 DR14 INVERTER AND_2 AND_2 AC5 B1 AC13 B1 ATOB AND6 AND14 ATOB INVERTER ATOB ATOB ATOB RESET RESET 7 7 AC6 B2 AC14 B2 OE AC6 AC14 OE OE OE OE CLK CLK 4 4 B3 B3 U101 U109 AC7 16 AC15 16 BUFFER_4 BUFF ER_4 BUFFER_4 BUFF ER_4 BUFFER_4 AND_2 JKFF AND_2 JKFF B4 B4 DR7 AND_2 DR15 AND_2 U132 13 14 13 14 Cout U120 AND7 AND15 AND2 U133 CMP2 CIL2 CIR2 C0 C4 C0 C4 ADD4 Bu s4 AC7 AC15 AND4 Bu s4 AC4 Bus4 AC3 Bus4 AC5 Bus4 U135 Cloc k Cloc k A0 B0 A0 B0 A0 B0 A0 B0 A0 B0 FG O ADD5 Bu s5 AND5 Bu s5 AC5 U134 Bus5 AC4 Bus5 AC6 Bus5 IR11 IR10 7483 7483 FG I A1 B1 A1 B1 A1 B1 A1 B1 A1 B1 pp pp ADD6 Bu s6 AND_2 AND_2 AND6 Bu s6 AC6 Bus6 AC5 Bus6 AC7 Bus6 ADD7 A2 B2 Bu s7 AND7 A2 B2 Bu s7 AC7 INVERTER A2 B2 Bus7 AC6 A2 B2 Bus7 AC8 A2 B2 Bus7 A3 B3 A3 B3 INVERT ER A3 B3 A3 B3 A3 B3 INVERTER ATOB ATOB INVERTER ATOB ATOB ATOB OE OE OE OE OE BUFF ER_4 BUFF ER_4 BUFFER_4 BUFF ER_4 BUFFER_4 U153 FGI U161 rr IRDECODE SEGA SEGC FGO U160 IR12 D0 Out0 SegA0 Out0 SegC0 IR8 IR13 D0 Q0 D1 Out1 D0 Q0 SegA1 Out1 D0 Q0 SegC1 pp IR14 D1 Q1 D2 Out2 D1 Q1 SegA2 Out2 D1 Q1 SegC2 OR_2 D2 Q2 D2 Q2 D2 Q2 U156 U162 AND_2 rr Q3 D3 D4 Out3 D3 Q3 SegA3 Out3 D3 Q3 SegC3 T0 U152 R_ D1 U163 OR_4 E_ U179 EN Q4 D5 Clock Clock U155 J Q R E D3 U201 U200 ALL Q5 D6 UCLK MIN UCLK MIN T5 U159 J Q T0 Q6 D7 DCLK MAX DCLK MAX T1 INVERT ER K !Q K !Q D4 U47 D0 Q0 D0 Q0 T1 Q7 CNTUP RCO CNT UP RCO SET U164 SET D1 Q1 D1 Q1 T2 U154 RESET AND_2 RESET D2 Q2 D2 Q2 DECODER_3_8 OE OE T2 INVERT ER AND_5 CLK U165 AND_2 CLK T4 OR_2 D3 Q3 D3 Q3 T3 T4 Out11 CE Out13 CE JKFF Cou t OR_4 JKFF U176 Clock UCLK MIN EN Q4 Q5 T5 LOAD RESET LOAD RESET D6 AND_2 T6 INVERT ER DCLK MAX ALL Q6 IEN Clo ck AND_2 Clo ck T7 COUNTER_4 COUNTER_4 U157 INVERT ER T6 U6 CNTUP RCO Q7 T8 R U177 Q8 T9 U166 R AND_2 OE Q9 T10 U41 T2 rr U167 CE Q10 T11 IR15 T2 LOAD Q11 T12 pp AND_2 IR7 U178 RESET Q12 Q13 T13 T5 AND_2 COUNTER_4 T14 SEGB SEGD AND_2 U168 Q14 T15 AND_2 Out0 SegB0 Out0 SegD0 Q15 Out1 D0 Q0 SegB1 Out1 D0 Q0 SegD1 U169 AND_2 D0 U46 OR_6 U39 Out2 D1 Q1 SegB2 Out2 D1 Q1 SegD2 DECODER_4_16 D2 Q2 D2 Q2 AC0 D1 AND_2 D7 Out3 SegB3 Out3 SegD3 D3 Q3 D3 Q3 U151 AND_2 D2 T3 Clock Clock D7 U110 INVERT ER D5 UCLK DCLK MIN MAX UCLK DCLK MIN MAX IR15 OR_4 AND_2 T3 U170 CNTUP RCO CNT UP RCO IEN_ rr U171 U49 AND_3 U136 IEN U54 OE OE IR7 J Q IR6 rr Out12 CE Out14 CE AND_2 U1 K SET !Q U12 IR15 LOAD LOAD IR6 AND_2 U172 U183 U27 RESET RESET U144 RESET U173 AND_2 rr J Q AND_2 COUNTER_4 COUNTER_4 R CLK K !Q Clock INVERTER AND_2 AC15 IR0 SET JKF F RESET T2 OR_2 CLK Clo ck AND_2 AND_2 AND_2 INVERT ER AND_2 JKF F 0 Reset U158 rr IR10 AND_2 .
- 9. IC (word) . 4 IC IC main.2.bin main.1.bin . . . inc ) 12 ( ) 16 16 . PC . 8 ( ) CE RCO . 4 .(inc 9
- 10. ( ) AR . DR AC : ( ) – InR OutR . 16 InR OutR .( ) AC / : 8 InR OutR 8 Out8 Out11-Out14 4 1 7-segment 10
- 11. (ALU) . ( ) ALU : AC . HLT . . 11
- 12. IDE . IDE . 4 IC . IC main.asm . Build Dual Memory . main.2.bin main.1.bin 12
- 13. . . . include . include 'file.inc' : Lib addr . addr . addr addr Ptr, dec 100 Ptr, addr Array … … org 100 Array, … Array, … . 4 . F020 NOP bin . hex 16 . ( ) . include . include . . . . end include . end 13
- 14. 4 7-segment 4 CPU . . : E . AC / / . . routineName_LabelName . ) . ( 14
- 15. /**************************************** / Calculator program for basic computer / Author: Mr.T (mrtofigh@gmail.com) / Last change: 1386.4.2 / All rights reserved. /**************************************** org 0 /------------------------------------------------ interrupt, bun start bun interrupt i /------------------------------------------------ include 'math.inc' include 'display.inc' include 'keypad.inc' /------------------------------------------------ start, reset, cla sta operand sta result sta operator sta eqWasEntered bsa writeHex loop, bsa readNum16 sta newOperand cla cil sta newOpEntered bsa readKey sta key add resetKey sza bun noReset bun reset noReset, checkOpEntered, lda newOpEntered sza bun checkSuccess checkEqKey, 15
- 16. lda key add equalityKey sza bun noOperand bun doOperand checkSuccess, lda newOperand sta operand lda eqWasEntered sza bun ignorePrevOperand bun doOperand ignorePrevOperand, cla sta operator doOperand, lda operator bsa lookup addr routines sta routine sze bun callRoutine lda operand bun afterCall callRoutine, lda result bsa routine i addr operand afterCall, sta result bsa writeNumber lda key add equalityKey sza bun noEqKey bun eqKey noOperand, noEqKey, lda key sta operator cla bun loopEnd eqKey, 16
- 17. cla cma loopEnd, sta eqWasEntered bsa waitNoKey bun loop key, hex 0 newOperand, hex 0 newOpEntered, hex 0 eqWasEntered, hex 0 operand, hex 0 result, hex 0 operator, hex 0 routine, hex 0 resetKey, dec -13 equalityKey, dec -15 routines, dec 4 addr divide dec 8 addr mul8 dec 12 addr sub16 dec 16 addr add16 dec 0 /---------------------------------------- divide, nop sta divide_Op1 lda divide i sta divide_Op2 lda divide_Op2 i sta divide_Op2 isz divide 17
- 18. lda divide_Op1 bsa div16 addr divide_Op2 addr divide_Rem bun divide i divide_Op1, hex 0 divide_Op2, hex 0 divide_Rem, hex 0 /---------------------------------------- end 18
- 19. math.inc /**************************************** / Math routines / Author: Mr.T (mrtofigh@gmail.com) / Last change: 1386.4.2 / All rights reserved. /**************************************** /---------------------------------------- / div16 routine / divides one word by another / input: / ac first operand >= 0 / pointer second operand <> 0 / output: / ac ac div second operand / pointer ac mod second operand /----------------------------------------- div16, nop sta div16_Divided lda div16 i sta div16_DividedBy lda div16_DividedBy i sta div16_DividedBy isz div16 lda div16 i sta div16_Param3 isz div16 cla sta div16_Remainder sta div16_Result lda div16_Divided bsa countBits addr div16_Divided cma inc sta div16_DBC div16_Loop, lda div16_DBC inc spa bun div16_Cont sza bun div16_End div16_Cont, 19
- 20. sta div16_DBC lda div16_Divided cil sta div16_Divided lda div16_Remainder cil sta div16_Remainder lda div16_DividedBy cma inc add div16_Remainder cle sna bun div16_DivideRem lda div16_Result cil sta div16_Result bun div16_Loop div16_DivideRem, sta div16_Remainder lda div16_Result cme cil sta div16_Result bun div16_Loop div16_End, lda div16_Remainder sta div16_Param3 i lda div16_Result bun div16 i div16_Result, hex 0 div16_Param3, hex 0 div16_Divided, hex 0 div16_DividedBy, hex 0 div16_Remainder, hex 0 div16_DBC, 20
- 21. hex 0 /---------------------------------------- /---------------------------------------- / countBits routine / Counts bits of a number / input: / ac number / output: / ac number of bits (position of leftmost bit + 1) / pointer right shifted ac (it's left-most bit is placed at msb) /----------------------------------------- countBits, nop sta countBits_Num lda countBits i sta countBits_Ptr2 isz countBits cla sta countBits_Count lda countBits_Num sza bun countBits_Loop bun countBits_End countBits_Loop, lda countBits_Num cle cil sze bun countBits_First1 sta countBits_Num isz countBits_Count bun countBits_Loop countBits_First1, lda countBits_Count cma inc add countBits_Const sta countBits_Count countBits_End, lda countBits_Num sta countBits_Ptr2 i lda countBits_Count bun countBits i 21
- 22. countBits_Num, hex 0 countBits_Ptr2, hex 0 countBits_Count, hex 0 countBits_Const, dec 16 /---------------------------------------- /---------------------------------------- / toBCD routine / Converts a word to BCD format / input: / ac number / output: / ac BCD number /----------------------------------------- toBCD, nop sta toBCD_Num cla sta toBCD_BCD lda toBCD_DigitCount sta toBCD_DC toBCD_Loop, lda toBCD_Num bsa div16 addr toBCD_Ten addr toBCD_Remainder sta toBCD_Num lda toBCD_BitCount sta toBCD_BC toBCD_NextBit, lda toBCD_Remainder cir sta toBCD_Remainder lda toBCD_BCD cir sta toBCD_BCD isz toBCD_BC bun toBCD_NextBit isz toBCD_DC bun toBCD_Loop 22
- 23. lda toBCD_BCD bun toBCD i toBCD_Num, hex 0 toBCD_BCD, hex 0 toBCD_Ten, dec 10 toBCD_Remainder, hex 0 toBCD_DigitCount, dec -4 toBCD_DC, hex 0 toBCD_BitCount, dec -4 toBCD_BC, hex 0 /----------------------------------------- /---------------------------------------- / sub16 routine / subtracts two words / input: / ac first operand / pointer second operand / output: / ac ac - second operand /----------------------------------------- sub16, nop sta sub16_Op1 lda sub16 i sta sub16_Ptr2 lda sub16_Ptr2 i isz sub16 cma inc add sub16_Op1 bun sub16 i sub16_Op1, hex 0 sub16_Ptr2, hex 0 /----------------------------------------- /---------------------------------------- / add16 routine / adds two words 23
- 24. / input: / ac first operand / pointer second operand / output: / ac ac + second operand /----------------------------------------- add16, nop sta add16_Op1 lda add16 i sta add16_Ptr2 lda add16_Ptr2 i isz add16 add add16_Op1 bun add16 i add16_Op1, hex 0 add16_ptr2, hex 0 /----------------------------------------- /---------------------------------------- / mul8 routine / multiplies two small words / input: / ac first operand / pointer second operand / output: / ac ac * second operand /----------------------------------------- mul8, nop sta mul8_Op1 lda mul8 i sta mul8_Op2 lda mul8_Op2 i sta mul8_Op2 isz mul8 cla sta mul8_Result mul8_Loop, lda mul8_Op1 sza bun mul8_NoZero bun mul8_End 24
- 25. mul8_NoZero, cle cir sta mul8_Op1 sze bun mul8_Add bun mul8_AfterAdd mul8_Add, lda mul8_Op2 add mul8_Result sta mul8_Result mul8_AfterAdd, lda mul8_Op2 cle cil sta mul8_Op2 bun mul8_Loop mul8_End, lda mul8_Result bun mul8 i mul8_Result, hex 0 mul8_Op1, hex 0 mul8_Op2, hex 0 /----------------------------------------- 25
- 26. display.inc /**************************************** / Display routines / Author: Mr.T (mrtofigh@gmail.com) / Last change: 1386.4.2 / All rights reserved. /**************************************** /---------------------------------------- / writeNumber routine / Displays a word in it's decimal format / input: / ac number to be displayed /----------------------------------------- writeNumber, nop bsa toBCD bsa writeHex bun writeNumber i /---------------------------------------- /---------------------------------------- / writeHex routine / Displays a hex number / input: / ac number to be displayed /----------------------------------------- writeHex, nop sta writeHex_Num lda writeHex_Count sta writeHex_C lda writeHex_SegA cma sta writeHex_Seg writeHex_Loop, lda writeHex_Num and writeHex_f4 cma and writeHex_Seg cma out lda writeHex_Seg cle cme cil 26
- 27. sta writeHex_Seg lda writeHex_Num cir cir cir cir sta writeHex_Num isz writeHex_C bun writeHex_Loop bun writeHex i writeHex_Num, hex 0 writeHex_segA, hex 800 writeHex_Seg, hex 0 writeHex_Count, hex -4 writeHex_C, hex 0 writeHex_f4, hex 0f /--------------------------------------- 27
- 28. keypad.inc /**************************************** / Keypad routines / Author: Mr.T (mrtofigh@gmail.com) / Last change: 1386.4.2 / All rights reserved. /**************************************** /---------------------------------------- / lookup routine / Searches a key in a table and returns it's associated data / input: / ac key / pointer table. a 0 value indicates end of table / output: / ac data stored in table after found key / e flag 1 = found, 0 = not found /----------------------------------------- lookup, nop sta lookup_Key lda lookup i sta lookup_Table isz lookup bun lookup_LoopStart lookup_Loop, isz lookup_Table lookup_LoopStart, lda lookup_Table i isz lookup_Table sza bun lookup_Cont bun lookup_NotFound lookup_Cont, cma inc add lookup_Key sza bun lookup_Loop lookup_Found, lda lookup_Table i cle cme 28
- 29. bun lookup_End lookup_NotFound, cle lookup_End, bun lookup i lookup_Table, hex 0 lookup_Key, hex 0 /---------------------------------------- /---------------------------------------- / waitKey routine / waits until a key being pressed /----------------------------------------- waitKey, nop waitKey_Loop, bsa readKey sza bun waitKey_End bun waitKey_Loop waitKey_End, bun waitKey i /---------------------------------------- /---------------------------------------- / waitNoKey routine / waits until no key being pressed /----------------------------------------- waitNoKey, nop waitNoKey_Loop, bsa readKey sza bun waitNoKey_Loop bun waitNoKey i /---------------------------------------- /---------------------------------------- / readNum16 routine / waits for entering a number, / displays number on 7-segments / returns when a non-digit key pressed / output / ac number / e flag 1 = a number returned in ac, 0 = no number /----------------------------------------- 29
- 30. readNum16, nop cla sta readNum16_NumEntered sta readNum16_Num readNum16_Loop, bsa readKey sza bun readNum16_Cont bun readNum16_Loop readNum16_Cont, sta readNum16_Key bsa keyToDigit sta readNum16_Digit sze bun readNum16_DigitKey bun readNum16_NonDigitKey readNum16_DigitKey, cla inc sta readNum16_NumEntered lda readNum16_Num bsa sub16 addr readNum16_4Digit sna bun readNum16_Loop lda readNum16_Num bsa Mul8 addr readNum16_Ten add readNum16_Digit sta readNum16_Num bsa writeNumber bsa waitNoKey bun readNum16_Loop readNum16_NonDigitKey, readNum16_End, lda readNum16_NumEntered cir lda readNum16_Num 30
- 31. bun readNum16 i readNum16_NumEntered, hex 0 readNum16_Digit, hex 0 readNum16_Num, hex 0 readNum16_Key, hex 0 readNum16_4Digit, dec 1000 readNum16_Ten, dec 10 /--------------------------------------- /---------------------------------------- / keyToDigit routine / returns digit from its key code / input: / ac Key code / output: / ac digit / e flag 1 = digit, 0 = non-digit /----------------------------------------- keyToDigit, nop bsa lookup addr keyToDigit_Digits bun keyToDigit i keyToDigit_Digits, dec 1 dec 7 dec 2 dec 8 dec 3 dec 9 dec 5 dec 4 dec 6 dec 5 dec 7 dec 6 dec 9 dec 1 31
- 32. dec 10 dec 2 dec 11 dec 3 dec 14 dec 0 dec 0 /--------------------------------------- /---------------------------------------- / readKey routine / returns code of pressed key / output: / ac 0 = no key pressed, non-0 = key code /----------------------------------------- readKey, nop cla sta readKey_Result sta readKey_Col lda readKey_RowCount sta readKey_RC lda readKey_Row sta readKey_R readKey_RowLoop, lda readKey_R and readKey_Keypad cma out inp sza bun readkey_Pressed lda readKey_R cle cme cil sta readKey_R lda readKey_Result add readKey_Four sta readKey_Result isz readKey_RC bun readKey_RowLoop /-- end of RowLoop -- 32
- 33. cla bun readKey_End readKey_Pressed, cle cir sze bun readKey_Pressed2 isz readKey_Col bun readKey_Pressed readKey_Pressed2, lda readKey_Result add readKey_Col inc readKey_End, bun readKey i readKey_Keypad, hex 0feff readKey_Result, hex 0 readKey_Four, hex 4 readKey_Row, hex 0fffe readKey_R, hex 0 readKey_RowCount, hex -4 readKey_RC, hex 0 readKey_Col, hex 0 /--------------------------------------- 33
- 34. .1385 .1 .1380 . .2 .(5.20.07 ) PROTEUS .3 34