![DDRx Memory Interfaces Overview
General Design Requirements
• Typical DDR2 and DDR3 Data Bus Structure:
BYTELANE0 DQ[7:0], DM0, DQS_P0, DQS_N0
BYTELANE1 DQ[15:8], DM1, DQS_P1, DQS_N1
BYTELANE2 DQ[23:16], DM2, DQS_P2, DQS_N2
BYTELANE3 DQ[31:24], DM3, DQS_P3, DQS_N3
BYTELANEn DQ[<8bits>], DMn, DQS_Pn, DQS_Nn
• Data Bytelane members should be routed on the same layer.
– In some DDR2 memory applications the Data Strobe line may single ended.
• Address / Command / Control / Differential Clocks should be routed on the
same layer but if space issues arise they could route on different layers.
– Adjacent layers or layers referencing the same plane layer is preferred.
• Address / Command / Control / Differential Clocks route topology differences
– DDR2 Interfaces: Routed using a Symmetrical Tree route topology.
– Routed to a central t-point with balanced routed legs to each of the Memory IC’s
– DDR3 Interfaces: Routed using a Daisy Chain (Fly-by) topology. Route from
controller starting with Chip 0 thru Chip n routing in order by Bytelane numbers
– Chip 0 is the lower data bit (Bytelane0) / Chip n is the upper data bit (Bytelane3).](https://image.slidesharecdn.com/a9268a60-55b4-4c41-b5e2-6b2cd742f61f-150623101935-lva1-app6892/85/DDR31-4-320.jpg)
DDR31
- 2. Agenda:- DDRx Memory Interfaces Overview Interconnect Topologies Placement and Pre-Route Techniques DDRx Design Rules XNET Generation Electrical Constraint Management Length Matching
- 3. •DDRx Memory Interfaces Overview Functional Group to Route Group Mapping
- 4. DDRx Memory Interfaces Overview General Design Requirements • Typical DDR2 and DDR3 Data Bus Structure: BYTELANE0 DQ[7:0], DM0, DQS_P0, DQS_N0 BYTELANE1 DQ[15:8], DM1, DQS_P1, DQS_N1 BYTELANE2 DQ[23:16], DM2, DQS_P2, DQS_N2 BYTELANE3 DQ[31:24], DM3, DQS_P3, DQS_N3 BYTELANEn DQ[<8bits>], DMn, DQS_Pn, DQS_Nn • Data Bytelane members should be routed on the same layer. – In some DDR2 memory applications the Data Strobe line may single ended. • Address / Command / Control / Differential Clocks should be routed on the same layer but if space issues arise they could route on different layers. – Adjacent layers or layers referencing the same plane layer is preferred. • Address / Command / Control / Differential Clocks route topology differences – DDR2 Interfaces: Routed using a Symmetrical Tree route topology. – Routed to a central t-point with balanced routed legs to each of the Memory IC’s – DDR3 Interfaces: Routed using a Daisy Chain (Fly-by) topology. Route from controller starting with Chip 0 thru Chip n routing in order by Bytelane numbers – Chip 0 is the lower data bit (Bytelane0) / Chip n is the upper data bit (Bytelane3).
- 5. •DDRx Memory Interfaces Overview DDR2 Bus Topologies – On Board SDRAM
- 6. •DDRx Memory Interfaces Overview DDR3 Bus Topologies – On Board SDRAM •Data Bus Termination – Series resistor termination could be used when the point to point connection is in the 2” to 2.5” range. – Resistors located at the center of the transmission line. – DRAM Termination with direct connect using On-Die termination (ODT) – Better signal quality and lower cost compared to using series resistor termination. • Clock Termination – 100ohm Differential terminator at last DDR3 device in the chain.
- 7. DDR2 Electrical Constraint Targets: • Relative Propagation Delay – Data Bytelane Ø 200mils between all members inside of Bytelane(For single ended) – Address / Command / Control 200 – 300mils between Controller(For single ended 25 – 50mils between memory ICs • Propagation Delay – Normally not constraint controlled as it is driven by placement of the memory ICs, which should be placed as close to the Controller as possible, normally between 750 – 1000mils between Memory ICs. Package type is also a driving factor, ICs vs. DIMM Connector. • Differential Phase Tolerance – 25mils for all Data Strobe and Clock Differential Pairs
- 8. Impedance / Design Stack-up:- • Impedance Requirements – Single Ended Target = 50 – 60 Ohms – Differential Pair Target = 100 – 120 Ohms • Design Stack-up considerations
- 9. Interconnect Topologies – Daisy Chain Routing:- DDR3 Address / Control / Command Routing Idle analysis.
- 10. Interconnect Topologies – Daisy Chain Routing:- DDR3 Address / Control / Command Routing Actual analysis
- 11. Placement Techniques:- Component Placement Careful planning of Memory chips or DIMM connectors placement to allow the best possible path for routing. Reserve space for pin escape (fanout), termination resistors as well as termination power supplies. For DDR3 interfaces: – Locate Memory chips to allow Address / Command / Control / Differential Clock Daisy Chain (Fly-by) routing starting at the Controller then connecting to the lowest data bit chip first (Bytelane0) progressing up the Bytelane numbers and ending at the highest data bit chip.
- 12. Placement Techniques:- Electrical Options – DRC Unrouted (Setup > Constraints > Modes) Enabling these options will provide DRC feedback when placing components that do not meet the delay requirements. Rules will be checked using Manhattan distances of Ratsnest connections.
- 13. Design Rules:- Electrical Options – Z Axis Delay (Setup > Constraints > Modes) As tolerances get tighter you can include Package and Z-Axis Delays in the DRC calculations to ensure rules are being met. These settings should be considered when planning out the electrical rules on any high speed interfaces
- 14. Design Rules:- Electrical Options – Z Axis Delay (Setup > Constraints > Modes) Design Stack-up must be defined with all the appropriate thicknesses based on a Fabricator approved stack-up for this additional Z-Axis check to be accurate. Depth (distance) the signal travels down the via or pin holes will be added to the delay calculations.
- 15. X-NET What is X-Net? eXtended Net through passive devices such as a resistor or capacitor which allows electrical design rules to be applied from IC Pin to IC Pin. How to generate X-Net:- AnalyzeSI/EMI SIMModel Assignment
- 16. How to generate X-Net:-
- 17. How to generate X-Net:- Select the component that you want to generate X-Net Click on Create Model
- 18. How to generate X-Net:-
- 19. How to generate X-Net:- If it is a Resistor/Capacitor Network……?
- 20. Length Matching:- How to Length Matching: Two methods for length matching: X-net Pin Pair
- 21. Length Matching:- How to Length Matching: Then you need to go create a Match group and make all the pinpairs to the match group.
- 22. Any Queries