Delay Analysis for Current Mode Threshold Logic Gate Designs
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This document analyzes delays in current mode threshold logic gate designs. It proposes a new implementation of current mode threshold functions that improves gate delay and switching energy. Simulation results using the Tanner tool show that gates implemented with the optimum sensor size using the proposed method outperform existing implementations in delay and switching energy.
Delay Analysis for Current Mode Threshold Logic Gate Designs
- 1. Delay Analysis for Current Mode Threshold Logic Gate Designs ABSTRACT: Current mode is a popular CMOS-based implementation of threshold logic functions, where the gate delay depends on the sensor size. This paper presents a new implementation of current mode threshold functions for improved gate delay and switching energy. An analytical method is also proposed in order to identify quickly the sensor size that minimizes the gate delay. Simulation results on different gates implemented using the optimum sensor size indicates that the proposed current mode implementation method outperforms consistently the existing implementations in delay as well as switching energy. The proposed architecture of this paper analysis the logic size, area and power consumption using Tanner tool. SOFTWARE IMPLEMENTATION: Tanner tool