Design of a 5 port router for noc using verilog
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The document presents the design of a 5-port router for Network on Chip (NoC) using Verilog, addressing the challenges of multiprocessor systems on chip due to wire and power design constraints. It discusses the fundamental components of NoC, including topology, routing techniques, and the router's efficiency in data communication. The proposed router is simulated and synthesized in Xilinx ISE 9.2i, aiming for high speed and low delay.
![IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308
__________________________________________________________________________________________
Volume: 03 Special Issue: 03 | May-2014 | NCRIET-2014, Available @ http://www.ijret.org 901
DESIGN OF A 5 PORT ROUTER FOR NOC USING VERILOG Somashekhar1, Rekha S2 1Department of E&CE, M.Tech in VLSI Design & Embedded System, Appa Institute of Engineering & Technology, Gulbarga, Karnataka, India 2Assistant Professor, Department of E&CE, M.Tech in VLSI Design & Embedded System, Appa Institute of Engineering & Technology, Gulbarga, Karnataka, India Abstract Multiprocessor system on chip is emerging as a new trend for System on chip design but the wire and power design constraints are forcing adoption of new design methodologies. Researchers pursued a scalable solution to this problem i.e. Network on Chip (NOC). Network on chip architecture better supports the integration of SOC consists of on chip packet switched network. The proposed design of router is simulated and synthesized in Xilinx ISE 9.2iand the source code is written in Verilog. Keywords: Network on Chip, 5 port router, Xilinx ISE 9.2i.
----------------------------------------------------------------------***-------------------------------------------------------------------- 1. INTRODUCTION As per Moore's law the density of chip doubles every 18 months, so the parameters of a single chip get affected due to increase of processing elements on a chip. NOC is a packet switched on-chip data transfer network that solves challenges faced by SOC of bus based communication. The basic ingredients of NOC are topology which defines the communication architecture, routing technique which decides how the data is routed from sender to receiver, routers and switching technique which determines when the data flow through the routers. NOC used only point to point wires for all network sizes and it increases the utilization of wires. The focus of paper is design of Network on chip five port routers. The effective on chip communication is achieved by router’s routing functionality and efficient arbitration [1]. The main goal of this paper is the design of power and area efficient on chip router. 2. ROUTER BASICS Advanced fabrication technologies and scaling have made it possible to integrate a large number of processor cores onto a single die, allowing us to obtain an entire Network-on-Chip (NoC). An example of a NoC with DRAM memory controllers and Dual Inline Memory Modules are shown in Fig 1, where a system consisting of 16 cores is shown. Arriving data is stored at the input buffers, which are divided into Virtual Channels (VC) to prevent deadlockand increase throughput. The VC allocator selects one VC for each input, and the switch allocator decides where each input will be routed to at the output port.
Fig 1: Network on chip-Router](https://image.slidesharecdn.com/designofa5portrouterfornocusingverilog-140822045252-phpapp02/85/Design-of-a-5-port-router-for-noc-using-verilog-1-320.jpg)
![IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308
__________________________________________________________________________________________
Volume: 03 Special Issue: 03 | May-2014 | NCRIET-2014, Available @ http://www.ijret.org 903
5. CONCLUSIONS
The proposed design of 5 port router is simulated and synthesized in Xilinx ISE 9.2i and the source code is written in Verilog. This proposed design has high speed and less delay. ACKNOWLEDGEMENTS I thankful to his Holiness Poojya Dr. Sharanabasaweshwar Appa, Mahadasoha Peethadhipati, Sharanabasaweshwar Samsthana, Gulbarga President, Sharanabasaweshwar Vidhya Vardhak Sangha, Gulbarga. And also thankful to Principal, Dean AIET Gulbarga REFERENCES [1]. P.B.Domkondwar and Dr. D.S.Chaudhari, “Implementation of Five Port Router Architecture Using VHDL” IJARCSEE Volume 1, Issue 3, May 2012. [2]. P. Kaveri, G.R.K.Prasad, FazalNoorbasha“Router design using cadence encounter” IJRTE, May 2013. [3]. BhavanP.Shrivastava, KavitaKhare“Design of improved routers for network on chip” IJCTT, sep 2013. [4]. B. Attia, W. Chouchene, A. Zitouni, N. Abid,and R. Tourki , “A Modular Router Architecture Desgin For Network on Chip” 8thInternational Multi-Conference on Systems, Signals & Devices 2011. [5]. M. Sood and V. Tiwari “Performance Evalution of Noc Router Architecture by Using VHDL” Vol-II No. 2 pages 154- 158, Oct-2010Jan-2011.](https://image.slidesharecdn.com/designofa5portrouterfornocusingverilog-140822045252-phpapp02/85/Design-of-a-5-port-router-for-noc-using-verilog-3-320.jpg)
Design of a 5 port router for noc using verilog
- 1. IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308 __________________________________________________________________________________________ Volume: 03 Special Issue: 03 | May-2014 | NCRIET-2014, Available @ http://www.ijret.org 901 DESIGN OF A 5 PORT ROUTER FOR NOC USING VERILOG Somashekhar1, Rekha S2 1Department of E&CE, M.Tech in VLSI Design & Embedded System, Appa Institute of Engineering & Technology, Gulbarga, Karnataka, India 2Assistant Professor, Department of E&CE, M.Tech in VLSI Design & Embedded System, Appa Institute of Engineering & Technology, Gulbarga, Karnataka, India Abstract Multiprocessor system on chip is emerging as a new trend for System on chip design but the wire and power design constraints are forcing adoption of new design methodologies. Researchers pursued a scalable solution to this problem i.e. Network on Chip (NOC). Network on chip architecture better supports the integration of SOC consists of on chip packet switched network. The proposed design of router is simulated and synthesized in Xilinx ISE 9.2iand the source code is written in Verilog. Keywords: Network on Chip, 5 port router, Xilinx ISE 9.2i. ----------------------------------------------------------------------***-------------------------------------------------------------------- 1. INTRODUCTION As per Moore's law the density of chip doubles every 18 months, so the parameters of a single chip get affected due to increase of processing elements on a chip. NOC is a packet switched on-chip data transfer network that solves challenges faced by SOC of bus based communication. The basic ingredients of NOC are topology which defines the communication architecture, routing technique which decides how the data is routed from sender to receiver, routers and switching technique which determines when the data flow through the routers. NOC used only point to point wires for all network sizes and it increases the utilization of wires. The focus of paper is design of Network on chip five port routers. The effective on chip communication is achieved by router’s routing functionality and efficient arbitration [1]. The main goal of this paper is the design of power and area efficient on chip router. 2. ROUTER BASICS Advanced fabrication technologies and scaling have made it possible to integrate a large number of processor cores onto a single die, allowing us to obtain an entire Network-on-Chip (NoC). An example of a NoC with DRAM memory controllers and Dual Inline Memory Modules are shown in Fig 1, where a system consisting of 16 cores is shown. Arriving data is stored at the input buffers, which are divided into Virtual Channels (VC) to prevent deadlockand increase throughput. The VC allocator selects one VC for each input, and the switch allocator decides where each input will be routed to at the output port. Fig 1: Network on chip-Router
- 2. IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308 __________________________________________________________________________________________ Volume: 03 Special Issue: 03 | May-2014 | NCRIET-2014, Available @ http://www.ijret.org 902 3. BLOCK DIAGRAM OF 5 PORT ROUTER Fig 2: Block diagram of 5 port router Source Code Written in Verilog Fig 3: Schematic of 5 port router 4. SIMULATION RESULTS
- 3. IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308 __________________________________________________________________________________________ Volume: 03 Special Issue: 03 | May-2014 | NCRIET-2014, Available @ http://www.ijret.org 903 5. CONCLUSIONS The proposed design of 5 port router is simulated and synthesized in Xilinx ISE 9.2i and the source code is written in Verilog. This proposed design has high speed and less delay. ACKNOWLEDGEMENTS I thankful to his Holiness Poojya Dr. Sharanabasaweshwar Appa, Mahadasoha Peethadhipati, Sharanabasaweshwar Samsthana, Gulbarga President, Sharanabasaweshwar Vidhya Vardhak Sangha, Gulbarga. And also thankful to Principal, Dean AIET Gulbarga REFERENCES [1]. P.B.Domkondwar and Dr. D.S.Chaudhari, “Implementation of Five Port Router Architecture Using VHDL” IJARCSEE Volume 1, Issue 3, May 2012. [2]. P. Kaveri, G.R.K.Prasad, FazalNoorbasha“Router design using cadence encounter” IJRTE, May 2013. [3]. BhavanP.Shrivastava, KavitaKhare“Design of improved routers for network on chip” IJCTT, sep 2013. [4]. B. Attia, W. Chouchene, A. Zitouni, N. Abid,and R. Tourki , “A Modular Router Architecture Desgin For Network on Chip” 8thInternational Multi-Conference on Systems, Signals & Devices 2011. [5]. M. Sood and V. Tiwari “Performance Evalution of Noc Router Architecture by Using VHDL” Vol-II No. 2 pages 154- 158, Oct-2010Jan-2011.