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SEMINAR REPORT
PRESENTATION
ON
DIGITAL COUNTER
Presented by:
BHASKAR KUMAR JHA
Roll no.- 11900315014
Digital Counter
Introduction
Types of Digital Counter
Asynchronous Counter
Synchronous Counter
Ring Counter
Johnson Counter
Application
A Digital counter is a sequential circuit consisting a set of flip-flops
connected in a suitable manner to count the sequence of the input pulses
presented to it in digital form.
Counters can be broadly classified as follows:
 Asynchronous and synchronous counters
 Single and multi-mode counters
 Modulus counters
 Introduction
 Asynchronous Counters
 Asynchronous Counter is one in which each flip flop is
triggered by the output of the previous flip flop, which
limits the speed of operation.
 Asynchronous counters are also called Ripple counter.
 These counters are easier to design and are constructed
using minimum hardware.
 Examples
Designing of a Mod-8(3 bit) Asynchronous counter
No. of flip flop depends on 2 𝑁 ≥ 𝐾
where N is number of flip flop & K is Mod no.
∴2n ≥ 8 n=3, i.e. 3 flip flop are required
𝐽0 𝑄0
𝑐𝑙𝑘0
𝐾0 𝑄0
𝐽1 𝑄1
𝑐𝑙𝑘1
𝐾1 𝑄1
𝐽2 𝑄2
𝑐𝑙𝑘2
𝐾2 𝑄2
1 1 1
𝑓𝑓0 𝑓𝑓2𝑓𝑓1
Clk
𝑐𝑙𝑘0
𝑄0
𝑄1
𝑄2
000010001 011 111101 110100000𝑄2 𝑄1 𝑄0
It is also called Asynchronous up counter because it counts from 000 to 111.
Timing Diagram
 Asynchronous Down Counters
𝐽0 𝑄0
𝑐𝑙𝑘0
𝐾0 𝑄0
𝐽1 𝑄1
𝑐𝑙𝑘1
𝐾1 𝑄1
𝐽2 𝑄2
𝑐𝑙𝑘2
𝐾2 𝑄2
𝑓𝑓0 𝑓𝑓2𝑓𝑓1
Asynchronous Down Counter is one in which each flip flop is
triggered by the inverse output of the previous flip flop.
A down counter using n flip-flops downward from a maximum
count of (2n-1) to zero.
1 1 1
Clk
𝑐𝑙𝑘0
𝑄0
𝑄1
𝑄2
000110111 101 001011 010100000𝑄2 𝑄1 𝑄0
It is called Asynchronous Down counter because it counts from HIGH to LOW.
Timing Diagram
 Universal Asynchronous Counter
𝐽0 𝑄0
𝑐𝑙𝑘0
𝐾0 𝑄0
𝐽1 𝑄1
𝑐𝑙𝑘1
𝐾1 𝑄1
𝐽2 𝑄2
𝑐𝑙𝑘2
𝐾2 𝑄2
𝑓𝑓0 𝑓𝑓2𝑓𝑓1
1 11
𝑀
M
 The Universal counter is a combination of the up-counter and the down counter.
These problems can be eliminated by applying clock pulses to all the
flip-flops simultaneously, which is done in a synchronous counter.
Asynchronous counter
Asynchronous counter is the simplest type of binary counters as it requires
less hardware.
But its speed of operation is low because the propagation delay time of all
flip-flop is cumulative and the total settling time is the product of the total
number of flip-flops and the propagation delay of a single flip-flop.
Another problem encountered with asynchronous counter is the glitches at
the decoding gate outputs.
 Synchronous Counters
 In synchronous counters, the clock inputs of all the flip-flops are
connected together and are triggered by the input pulses. Thus, all
the flip-flops change state simultaneously (in parallel).
 Speed of operation is higher then Asynchronous counter.
 Synchronous Counters
Design Mod-4 Synchronous counter
We know, 2n ≥ N
∴2n ≥ 4 n=2, i.e. 2 flip flop are required
Qn Qn+1
J K
0 0 0 ×
0 1 1 ×
1 0 × 1
1 1 × 0
Count Value
(Decimal)
Count Value
(Binary)
Q1 Q0
𝑱 𝟏 𝑲 𝟏 𝑱 𝟎 𝑲 𝟎
0 0 0 0 × 1 ×
1 0 1 1 × × 1
2 1 0 0 × 1 ×
3 1 1 × 1 × 1
0 0 0
Excitation table
Q0
Q1
0 1
0 0 1
1 0 X
K-map simplification
Q0
Q1
0 1
0 1 X
1 1 X
Q0
Q1
0 1
0 X 1
1 X 1
Q0
Q1
0 1
0 X X
1 X 1
For 𝐾1 For 𝐽0 For 𝐾0For 𝐽1
𝐽1 = 𝑄0 𝐾1=1 𝐽0=1 𝐾0=1
𝐽0 𝑄0
𝑐𝑙𝑘0
𝐾0 𝑄0
𝐽1 𝑄1
𝑐𝑙𝑘1
𝐾1 𝑄1
𝑓𝑓0 𝑓𝑓1
1
clock
Clock Q1 Q0
0 0
0 1
1 0
1 1
0 0
 Synchronous Universal Counters
To form a synchronous universal counter, the control inputs are used
to allow either the normal output or the inverted output of one flip-
flop to the J and K inputs of the following flip-flop.
𝐽0 𝑄0
𝑐𝑙𝑘0
𝐾0 𝑄0
𝐽1 𝑄1
𝑐𝑙𝑘1
𝐾1 𝑄1
𝐽2 𝑄2
𝑐𝑙𝑘2
𝐾2 𝑄2
𝑓𝑓0 𝑓𝑓2𝑓𝑓1
1
Count-Down
Clk
Count-Up
 Ring Counters
 The true output (Q) of the last flip-flop in a shift register is connected
back to the first flip-flop.
 One flip-flop is set at any particular time while all others are cleared.
 A single 1 in the register is made to circulate around the register as long
as clock pulses are applied, it is called a ring counter.
𝐷0 𝑄0
𝑐𝑙𝑘0
𝑄0
𝐷1 𝑄1
𝑐𝑙𝑘1
𝑄1
𝐷2 𝑄2
𝑐𝑙𝑘2
𝑄2
𝑓𝑓0 𝑓𝑓2
𝑓𝑓1
𝑐𝑟
𝑝𝑟
𝑐𝑟
Clk
𝑂𝑅𝐼
ORI Clk Q0 Q1 Q2
L
H
H
H
X 1 0 0
0 1 0
0 0 1
1 0 0
No. of states= No. of flip flop
 Ring Counters
 Johnson Counters
The Johnson Counter is constructed similar to a standard ring counter
except that the inverted output of the last flip-flop is connected to the
input of the first flip-flop.
𝐷0 𝑄0
𝑐𝑙𝑘0
𝑄0
𝐷1 𝑄1
𝑐𝑙𝑘1
𝑄1
𝐷2 𝑄2
𝑐𝑙𝑘2
𝑄2
𝑓𝑓0 𝑓𝑓2
𝑓𝑓1
𝑐𝑟𝑐𝑟 𝑐𝑟
Clk
ORI
No. of states= 2 × No. of flip flop
ORI Clk Q0 Q1 Q2
L
H
H
H
H
H
H
X 0 0 0
1 0 0
1 1 0
1 1 1
0 1 1
0 0 1
0 0 0
Application:
Some of their applications are :
Tally Counter Digital Meter Product Counter Calculator
Thank you

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Digital counter

  • 1. SEMINAR REPORT PRESENTATION ON DIGITAL COUNTER Presented by: BHASKAR KUMAR JHA Roll no.- 11900315014
  • 2. Digital Counter Introduction Types of Digital Counter Asynchronous Counter Synchronous Counter Ring Counter Johnson Counter Application
  • 3. A Digital counter is a sequential circuit consisting a set of flip-flops connected in a suitable manner to count the sequence of the input pulses presented to it in digital form. Counters can be broadly classified as follows:  Asynchronous and synchronous counters  Single and multi-mode counters  Modulus counters  Introduction
  • 4.  Asynchronous Counters  Asynchronous Counter is one in which each flip flop is triggered by the output of the previous flip flop, which limits the speed of operation.  Asynchronous counters are also called Ripple counter.  These counters are easier to design and are constructed using minimum hardware.
  • 5.  Examples Designing of a Mod-8(3 bit) Asynchronous counter No. of flip flop depends on 2 𝑁 ≥ 𝐾 where N is number of flip flop & K is Mod no. ∴2n ≥ 8 n=3, i.e. 3 flip flop are required 𝐽0 𝑄0 𝑐𝑙𝑘0 𝐾0 𝑄0 𝐽1 𝑄1 𝑐𝑙𝑘1 𝐾1 𝑄1 𝐽2 𝑄2 𝑐𝑙𝑘2 𝐾2 𝑄2 1 1 1 𝑓𝑓0 𝑓𝑓2𝑓𝑓1 Clk
  • 6. 𝑐𝑙𝑘0 𝑄0 𝑄1 𝑄2 000010001 011 111101 110100000𝑄2 𝑄1 𝑄0 It is also called Asynchronous up counter because it counts from 000 to 111. Timing Diagram
  • 7.  Asynchronous Down Counters 𝐽0 𝑄0 𝑐𝑙𝑘0 𝐾0 𝑄0 𝐽1 𝑄1 𝑐𝑙𝑘1 𝐾1 𝑄1 𝐽2 𝑄2 𝑐𝑙𝑘2 𝐾2 𝑄2 𝑓𝑓0 𝑓𝑓2𝑓𝑓1 Asynchronous Down Counter is one in which each flip flop is triggered by the inverse output of the previous flip flop. A down counter using n flip-flops downward from a maximum count of (2n-1) to zero. 1 1 1 Clk
  • 8. 𝑐𝑙𝑘0 𝑄0 𝑄1 𝑄2 000110111 101 001011 010100000𝑄2 𝑄1 𝑄0 It is called Asynchronous Down counter because it counts from HIGH to LOW. Timing Diagram
  • 9.  Universal Asynchronous Counter 𝐽0 𝑄0 𝑐𝑙𝑘0 𝐾0 𝑄0 𝐽1 𝑄1 𝑐𝑙𝑘1 𝐾1 𝑄1 𝐽2 𝑄2 𝑐𝑙𝑘2 𝐾2 𝑄2 𝑓𝑓0 𝑓𝑓2𝑓𝑓1 1 11 𝑀 M  The Universal counter is a combination of the up-counter and the down counter.
  • 10. These problems can be eliminated by applying clock pulses to all the flip-flops simultaneously, which is done in a synchronous counter. Asynchronous counter Asynchronous counter is the simplest type of binary counters as it requires less hardware. But its speed of operation is low because the propagation delay time of all flip-flop is cumulative and the total settling time is the product of the total number of flip-flops and the propagation delay of a single flip-flop. Another problem encountered with asynchronous counter is the glitches at the decoding gate outputs.
  • 11.  Synchronous Counters  In synchronous counters, the clock inputs of all the flip-flops are connected together and are triggered by the input pulses. Thus, all the flip-flops change state simultaneously (in parallel).  Speed of operation is higher then Asynchronous counter.
  • 12.  Synchronous Counters Design Mod-4 Synchronous counter We know, 2n ≥ N ∴2n ≥ 4 n=2, i.e. 2 flip flop are required Qn Qn+1 J K 0 0 0 × 0 1 1 × 1 0 × 1 1 1 × 0 Count Value (Decimal) Count Value (Binary) Q1 Q0 𝑱 𝟏 𝑲 𝟏 𝑱 𝟎 𝑲 𝟎 0 0 0 0 × 1 × 1 0 1 1 × × 1 2 1 0 0 × 1 × 3 1 1 × 1 × 1 0 0 0 Excitation table
  • 13. Q0 Q1 0 1 0 0 1 1 0 X K-map simplification Q0 Q1 0 1 0 1 X 1 1 X Q0 Q1 0 1 0 X 1 1 X 1 Q0 Q1 0 1 0 X X 1 X 1 For 𝐾1 For 𝐽0 For 𝐾0For 𝐽1 𝐽1 = 𝑄0 𝐾1=1 𝐽0=1 𝐾0=1 𝐽0 𝑄0 𝑐𝑙𝑘0 𝐾0 𝑄0 𝐽1 𝑄1 𝑐𝑙𝑘1 𝐾1 𝑄1 𝑓𝑓0 𝑓𝑓1 1 clock Clock Q1 Q0 0 0 0 1 1 0 1 1 0 0
  • 14.  Synchronous Universal Counters To form a synchronous universal counter, the control inputs are used to allow either the normal output or the inverted output of one flip- flop to the J and K inputs of the following flip-flop. 𝐽0 𝑄0 𝑐𝑙𝑘0 𝐾0 𝑄0 𝐽1 𝑄1 𝑐𝑙𝑘1 𝐾1 𝑄1 𝐽2 𝑄2 𝑐𝑙𝑘2 𝐾2 𝑄2 𝑓𝑓0 𝑓𝑓2𝑓𝑓1 1 Count-Down Clk Count-Up
  • 15.  Ring Counters  The true output (Q) of the last flip-flop in a shift register is connected back to the first flip-flop.  One flip-flop is set at any particular time while all others are cleared.  A single 1 in the register is made to circulate around the register as long as clock pulses are applied, it is called a ring counter.
  • 16. 𝐷0 𝑄0 𝑐𝑙𝑘0 𝑄0 𝐷1 𝑄1 𝑐𝑙𝑘1 𝑄1 𝐷2 𝑄2 𝑐𝑙𝑘2 𝑄2 𝑓𝑓0 𝑓𝑓2 𝑓𝑓1 𝑐𝑟 𝑝𝑟 𝑐𝑟 Clk 𝑂𝑅𝐼 ORI Clk Q0 Q1 Q2 L H H H X 1 0 0 0 1 0 0 0 1 1 0 0 No. of states= No. of flip flop  Ring Counters
  • 17.  Johnson Counters The Johnson Counter is constructed similar to a standard ring counter except that the inverted output of the last flip-flop is connected to the input of the first flip-flop. 𝐷0 𝑄0 𝑐𝑙𝑘0 𝑄0 𝐷1 𝑄1 𝑐𝑙𝑘1 𝑄1 𝐷2 𝑄2 𝑐𝑙𝑘2 𝑄2 𝑓𝑓0 𝑓𝑓2 𝑓𝑓1 𝑐𝑟𝑐𝑟 𝑐𝑟 Clk ORI No. of states= 2 × No. of flip flop ORI Clk Q0 Q1 Q2 L H H H H H H X 0 0 0 1 0 0 1 1 0 1 1 1 0 1 1 0 0 1 0 0 0
  • 18. Application: Some of their applications are : Tally Counter Digital Meter Product Counter Calculator