1. 1
Hardware description languages: introduction
• intellectual property (IP)
• introduction to VHDL and Verilog
• entities and architectural bodies
• behavioral, structural, and dataflow views
• examples
2. 2
hardware description languages (HDL's):
HDL is a language to describe hardware, just
like it says; typically a HDL tries to use
programming-language-type syntax and
constructs to describe hardware, allowing the
user to avoid the use of schematics
3. 3
Some things HDL's must deal with:
parallel activity (e.g., in a half adder, both the XOR
and AND gates receive inputs simultaneously)
vector inputs (e.g., in an 8-bit adder, the inputs are
each 8 bits and the output is 9 bits)
timing--both sequential and combinational logic
(e.g., in a register the interaction between the clock
input and the state changes must be described)
levels of abstraction
ideally will support both analysis and synthesis for
hardware components/systems
4. 4
intellectual property (IP): HDL's are an effective
way to describe components in which the internal
workings ("intellectual property") are proprietary but
the interface to other components must be public
"popular" HDL's: VHDL, Verilog
Both have “AMS” (Analog and Mixed Signal)
extensions
5. 5
Two main HDLs: VHDL / Verilog
VHDL--Very High Speed Integrated Circuit (VHSIC) Hardware
Description Language
Standards--IEEE 1076-1987;1076-1993; Ada-like language
Additions--VHDL-AMS--Analog & Mixed Signal
Verilog—1985; proprietary to Cadence until 1990 (“open
Verilog”)
C-like language
Additions—Verilog-AMS—Analog & Mixed Signal
NOTE: this course is NOT designed to make you a VHDL
or Verilog expert! The Altera tools (as well as other
synthesis tools) work best with simpler HDL constructs
(e.g., structural representations, modest levels of nesting)
6. 6
VHDL and Verilog:
Behavioral, Structural, and “Dataflow" views supported
Physical views generally not supported
--descriptions do not encompass the low-level physical
details of a design
--in particular descriptions can be "technology
independent"; this supports REUSABILITY
--for simulation, may add details of a particular
technology
[this quarter—HDL designs are tied to the specific
technology of the chosen Altera device]
Both languages allow for “testbenches” to aid
simulation
We will use Verilog this quarter; Verilog is “c-like”;;
Verilog is CASE SENSITIVE
7. 7
what can HDLs be used for?
design entry
simulation ("analysis"): simulators are examples
of "discrete event simulators"
E10 E11 E20 E12 E22 E13
synthesis: HDL description can be turned into a
circuit layout by powerful "silicon compilers"
time
a b
sum
carry
E10: a changes
E20: b changes
E11, E21
E12, E22
E13, E23
8. 8
Example; what combinational circuit does this represent?
module mystery (enable, x1, x2, x3, x4, y);
//what is the mystery function? This is a 1-line comment
input enable, x1, x2, x3, x4;
output y;
/* definitions of logic gates begin
at this point –this is a multiple line comment */
wire w1, w2, w3;
or (w1, x1, x2);
or (w2, x3, x4);
or (w3, x3, x4); // redundant
nand (y, w1, w2, w3, enable);
endmodule
Source of this and following slides on verilog:
cs.haifa.ac.il/courses/verilog/verilog_tutorial1.ppt
cs.haifa.ac.il/courses/verilog/verilog_tutorial2.ppt
cs.haifa.ac.il/courses/verilog/verilog_tutorial3.ppt
9. 9
Example 2;
what should we name this combinational circuit?
How should we fill in the blanks in the comments?
Can we rewrite it using the style of example 1?
module Name (A, B, Sum Carry);
input A, B;
output Sum, Carry;
assign Sum = A ^ B;
//^ denotes ______
assign Carry = A & B;
// & denotes ______
endmodule
10. 10
3 types of description:
--structural
--behavioral
--dataflow
Example: structural description
not n1(sel_n, sel);
and a1(sel_b, b, sel_n);
and a2(sel_a, a, sel);
or o1(out, sel_b, sel_a);
sel
b
a
out
sel_n
sel_b
sel_a
n1
a1
a2
o1
13. 13
not n1(sel_n, sel);
and a1(sel_b, b, sel_n);
and a2(sel_a, a, sel);
or o1(out, sel_b, sel_a);
assign out = (sel & a) | (~sel & b);
// multiple assignment statements
// will all execute concurrently
//order of the statements
doesn’t //matter
if (select == 0) begin
out = b;
end
else if (select == 1) begin
out = a;
end
//statements sequential; inter-
and intra-statement delays exist
In all 3
cases, the
design tools
will choose
the actual
PHYSICAL
layout.
14. 14
Behavioral (“algorithmic”) modeling: “programming” constructs
Example:
module mux_2x1(a, b, sel, out);
input a, b, sel;
output out;
always @(a or b or sel)
begin
if (sel == 1)
out = a;
else out = b;
end
endmodule
//if any of a, b, sel changes, output is recalculated
Sensitivity List
15. 15
Behavioral modeling:
always statement : Sequential Block
Sequential Block: All statements within the block are executed
sequentially
When is it executed?
Occurrence of an event in the sensitivity list
Event: Change in the logical value
Statements with a Sequential Block: Procedural Assignments
Delay in Procedural Assignments
Inter-Statement Delay
Intra-Statement Delay
16. 16
Inter-Assignment Delay
Example:
Sum = A ^ B;
#2 Carry = A & B;
Delayed execution
Intra-Assignment Delay
Example:
Sum = A ^ B;
Carry = #2 A & B;
Delayed assignment
Notation: #2 means delay 2 time units (unit = ns)
17. 17
Two Procedural Constructs
initial Statement
always Statement
initial Statement : Executes only once
always Statement : Executes in a loop
Example:
…
initial begin
Sum = 0;
Carry = 0;
end
…
…
always @(A or B) begin
Sum = A ^ B;
Carry = A & B;
end
…
18. 18
Sequential logic:
Can be edge-triggered (posedge or negedge) or level-triggered
Example:
Edge Triggered Event Control
@ (posedge CLK) //Positive Edge of CLK
Curr_State = Next_state;
Level Triggered Event Control
@ (A or B) //change in values of A or B
Out = A & B;
19. 19
Loops: while, for repeat
Examples:
repeat (Count)
sum = sum + 5;
while (Count < 10) begin
sum = sum + 5;
Count = Count +1;
end
for (Count = 0; Count < 10; Count = Count + 1) begin
sum = sum + 5;
end
In while and repeat loops, if value of count is x or z, it is treated
as 0
21. 21
Case Statements
Example 1:
case (X)
2’b00: Y = A + B;
2’b01: Y = A – B;
2’b10: Y = A / B;
endcase
Example 2: which statement is executed?
case (3’b101 << 2)
3’b100: A = B + C;
4’b0100: A = B – C;
5’b10100: A = B / C;
endcase
22. 22
Example: mux design
if .. else Statement
module mux_4bits (y, a, b, c, d, sel);
input [3:0] a, b, c, d;
input [1:0] sel
output [3:0] y;
reg [3:0] y;
always @ (a or b or c or d or sel)
if (sel == 0) y = a; else
if (sel == 1) y = b; else
if (sel == 2) y = c; else
if (sel == 3) y = d;
else y = 4'bx;
endmodule
CASE Statement
module mux_4bits (y, a, b, c, d,
sel);
input [3:0] a, b, c, d;
input [1:0] sel
output [3:0] y;
reg [3:0] y;
always @ (a or b or c or d or
sel)
case (sel)
0: y = a;
1: y = b;
2: y = c;
3: y = d;
default: y = 4'bx;
endcase
endmodule
sel[1:0]
a[3:0]
y[3:0]
b[3:0]
c[3:0]
d[3:0]
23. 23
Data types:
Net Types: Physical Connection between structural
elements
Register Type: Represents an abstract storage
element.
Default Values
Net Types : z
Register Type : x
Some Net Types: wire, supply0, supply1
Some Register Types : reg, integer, time, real, realtime
24. 24
Some example bit vectors:
Net Type: Wire
wire [ msb : lsb ] wire1, wire2, …
Example
wire Reset; // A 1-bit wire
wire [6:0] Clear; // A 7-bit wire
Register Type: Reg
reg [ msb : lsb ] reg1, reg2, …
Example
reg [ 3: 0 ] cla; // A 4-bit register
reg cla; // A 1-bit register
25. 25
Data Flow and Structural Modeling
Can use only wire data type
Cannot use reg data type
Behavioral Modeling
Can use only reg data type (within initial and
always constructs)
Cannot use wire data type
26. 26
An array of registers
reg [ msb : lsb ] memory1 [ upper : lower ];
Example
reg [ 0 : 3 ] mem [ 0 : 63 ];
// An array of 64 4-bit registers
reg mem [ 0 : 4 ];
// An array of 5 1-bit registers
Example: define a 2 megabyte memory called
MyMem
(recall: what is the meaning of
“megabyte”?)
27. 27
Example: an altera state machine design: what does the state
diagram look like?
statem.v
module statem(clk, in, reset, out);
input clk, in, reset;
output [3:0] out; reg [3:0] out;
reg [1:0] state;
parameter zero=0, one=1,
two=2, three=3;
always @(state) begin case (state)
zero: out = 4'b0000;
one: out = 4'b0001;
two: out = 4'b0010;
three: out = 4'b0100;
default: out = 4'b0000;
endcase
end
always
@(posedge clk or posedge reset)
begin
if (reset) state = zero;
else case (state)
zero: state = one;
one: if (in) state = zero;
else state = two;
two: state = three;
three: state = zero;
endcase
end
endmodule
![6
VHDL and Verilog:
Behavioral, Structural, and “Dataflow" views supported
Physical views generally not supported
--descriptions do not encompass the low-level physical
details of a design
--in particular descriptions can be "technology
independent"; this supports REUSABILITY
--for simulation, may add details of a particular
technology
[this quarter—HDL designs are tied to the specific
technology of the chosen Altera device]
Both languages allow for “testbenches” to aid
simulation
We will use Verilog this quarter; Verilog is “c-like”;;
Verilog is CASE SENSITIVE](https://image.slidesharecdn.com/embedfall12tworev-250816003842-62992045/85/Digital-system-design-using-vhdl-and-verilog-6-320.jpg)
![22
Example: mux design
if .. else Statement
module mux_4bits (y, a, b, c, d, sel);
input [3:0] a, b, c, d;
input [1:0] sel
output [3:0] y;
reg [3:0] y;
always @ (a or b or c or d or sel)
if (sel == 0) y = a; else
if (sel == 1) y = b; else
if (sel == 2) y = c; else
if (sel == 3) y = d;
else y = 4'bx;
endmodule
CASE Statement
module mux_4bits (y, a, b, c, d,
sel);
input [3:0] a, b, c, d;
input [1:0] sel
output [3:0] y;
reg [3:0] y;
always @ (a or b or c or d or
sel)
case (sel)
0: y = a;
1: y = b;
2: y = c;
3: y = d;
default: y = 4'bx;
endcase
endmodule
sel[1:0]
a[3:0]
y[3:0]
b[3:0]
c[3:0]
d[3:0]](https://image.slidesharecdn.com/embedfall12tworev-250816003842-62992045/85/Digital-system-design-using-vhdl-and-verilog-22-320.jpg)
![24
Some example bit vectors:
Net Type: Wire
wire [ msb : lsb ] wire1, wire2, …
Example
wire Reset; // A 1-bit wire
wire [6:0] Clear; // A 7-bit wire
Register Type: Reg
reg [ msb : lsb ] reg1, reg2, …
Example
reg [ 3: 0 ] cla; // A 4-bit register
reg cla; // A 1-bit register](https://image.slidesharecdn.com/embedfall12tworev-250816003842-62992045/85/Digital-system-design-using-vhdl-and-verilog-24-320.jpg)
![26
An array of registers
reg [ msb : lsb ] memory1 [ upper : lower ];
Example
reg [ 0 : 3 ] mem [ 0 : 63 ];
// An array of 64 4-bit registers
reg mem [ 0 : 4 ];
// An array of 5 1-bit registers
Example: define a 2 megabyte memory called
MyMem
(recall: what is the meaning of
“megabyte”?)](https://image.slidesharecdn.com/embedfall12tworev-250816003842-62992045/85/Digital-system-design-using-vhdl-and-verilog-26-320.jpg)
![27
Example: an altera state machine design: what does the state
diagram look like?
statem.v
module statem(clk, in, reset, out);
input clk, in, reset;
output [3:0] out; reg [3:0] out;
reg [1:0] state;
parameter zero=0, one=1,
two=2, three=3;
always @(state) begin case (state)
zero: out = 4'b0000;
one: out = 4'b0001;
two: out = 4'b0010;
three: out = 4'b0100;
default: out = 4'b0000;
endcase
end
always
@(posedge clk or posedge reset)
begin
if (reset) state = zero;
else case (state)
zero: state = one;
one: if (in) state = zero;
else state = two;
two: state = three;
three: state = zero;
endcase
end
endmodule](https://image.slidesharecdn.com/embedfall12tworev-250816003842-62992045/85/Digital-system-design-using-vhdl-and-verilog-27-320.jpg)
