digitaldesign-2020-lecture10a-lc3andmips-beforelecture.pdf

Digital Design & Computer Arch.
Lecture 10a: Instruction Set Architecture
Prof. Onur Mutlu
ETH Zürich
Spring 2020
20 March 2020

Assignment: Required Lecture Video
n Why study computer architecture?
n Why is it important?
n Future Computing Architectures
n Required Assignment
q Watch Prof. Mutlu’s inaugural lecture at ETH and understand it
q https://www.youtube.com/watch?v=kgiZlSOcGFM
n Optional Assignment – for 1% extra credit
q Write a 1-page summary of the lecture and email us
n What are your key takeaways?
n What did you learn?
n What did you like or dislike?
n Submit your summary to Moodle – Deadline: March 25
2

Extra Assignment: Moore’s Law (I)
n Paper review
n G.E. Moore. "Cramming more components onto integrated
circuits," Electronics magazine, 1965
n Optional Assignment – for 1% extra credit
q Write a 1-page review
q Upload PDF file to Moodle – Deadline: April 1
n I strongly recommend that you follow my guidelines for
(paper) review (see next slide)
3

Extra Assignment: Moore’s Law (II)
n Guidelines on how to review papers critically
q Guideline slides: pdf ppt
q Video: https://www.youtube.com/watch?v=tOL6FANAJ8c
q Example reviews on “Main Memory Scaling: Challenges and
Solution Directions” (link to the paper)
n Review 1
n Review 2
q Example review on “Staged memory scheduling: Achieving
high performance and scalability in heterogeneous
systems” (link to the paper)
n Review 1
4

Agenda for Today & Next Few Lectures
n LC-3 and MIPS Instruction Set Architectures
n LC-3 and MIPS assembly and programming
n Introduction to microarchitecture and single-cycle
microarchitecture
n Multi-cycle microarchitecture
5

Required Readings
n This week
q Von Neumann Model, LC-3, and MIPS
n P&P, Chapters 4, 5
n H&H, Chapter 6
n P&P, Appendices A and C (ISA and microarchitecture of LC-3)
n H&H, Appendix B (MIPS instructions)
q Programming
n P&P, Chapter 6
q Recommended: H&H Chapter 5, especially 5.1, 5.2, 5.4, 5.5
n Next week
q Introduction to microarchitecture and single-cycle microarchitecture
n H&H, Chapter 7.1-7.3
n P&P, Appendices A and C
q Multi-cycle microarchitecture
n H&H, Chapter 7.4
n P&P, Appendices A and C
6

Recall: The Instruction Cycle
q FETCH
q DECODE
q EVALUATE ADDRESS
q FETCH OPERANDS
q EXECUTE
q STORE RESULT
7

Instruction Set Architectures
8

Recall: The Instruction Set Architecture
n The ISA is the interface between what the software commands
and what the hardware carries out
n The ISA specifies
q The memory organization
n Address space (LC-3: 216, MIPS: 232)
n Addressability (LC-3: 16 bits, MIPS: 32 bits)
n Word- or Byte-addressable
q The register set
n R0 to R7 in LC-3
n 32 registers in MIPS
q The instruction set
n Opcodes
n Data types
n Addressing modes
9
Microarchitecture
ISA
Program
Algorithm
Problem
Circuits
Electrons

Recall: Opcodes in LC-3
10
5.1 The ISA: Overview 119
BaseR 000000
DR
DR SR 111111
000000000000
SR
BaseR offset6
0000 trapvect8
0 00 BaseR 000000
1 PCoffset11
PCoffset9
PCoffset9
PCoffset9
PCoffset9
STI
STR
TRAP
reserved
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
z
n p
DR SR1 1 imm5
0101
0000
000
DR SR1 0 00 SR2
0101
0001 DR SR1 1 imm5
0001 DR SR1 0 00 SR2
DR
DR
1100
1010
0110
1110
1001
1100
1000
0011
BaseR offset6
000 111 000000
SR
1011
0111
1111
1101
SR
0100
DR
0010
0100
PCoffset9
PCoffset9
BR
AND+
ADD+
ADD+
AND+
JMP
LD+
LDI+
LDR+
LEA+
NOT+
RET
RTI
ST
JSRR
JSR
Figure 5.3 Formats of the entire LC-3 instruction set. NOTE: + indicates instructions
that modify condition codes

Recall: Funct in MIPS R-Type Instructions (I)
12
101011 (43) sw rt, imm(rs) store word [Address] = [rt]
110001 (49) lwc1 ft, imm(rs) load word to FP coprocessor 1 [ft] = [Address]
111001 (56) swc1 ft, imm(rs) store word to FP coprocessor 1 [Address] = [ft]
Table B.2 R-type instructions, sorted by funct field
Funct Name Description Operation
000000 (0) sll rd, rt, shamt shift left logical [rd] = [rt] << shamt
000010 (2) srl rd, rt, shamt shift right logical [rd] = [rt] >> shamt
000011 (3) sra rd, rt, shamt shift right arithmetic [rd] = [rt] >>> shamt
000100 (4) sllv rd, rt, rs shift left logical variable [rd] = [rt] << [rs]4:0
000110 (6) srlv rd, rt, rs shift right logical variable [rd] = [rt] >> [rs]4:0
000111 (7) srav rd, rt, rs shift right arithmetic variable [rd] = [rt] >>> [rs]4:0
001000 (8) jr rs jump register PC = [rs]
001001 (9) jalr rs jump and link register $ra = PC + 4, PC = [rs]
001100 (12) syscall system call system call exception
001101 (13) break break break exception
010000 (16) mfhi rd move from hi [rd] = [hi]
010001 (17) mthi rs move to hi [hi] = [rs]
010010 (18) mflo rd move from lo [rd] = [lo]
010011 (19) mtlo rs move to lo [lo] = [rs]
011000 (24) mult rs, rt multiply {[hi], [lo]} = [rs] × [rt]
011001 (25) multu rs, rt multiply unsigned {[hi], [lo]} = [rs] × [rt]
011010 (26) div rs, rt divide [lo] = [rs]/[rt],
[hi] = [rs]%[rt]
011011 (27) divu rs, rt divide unsigned [lo] = [rs]/[rt],
[hi] = [rs]%[rt]
(continued)
Harris and Harris, Appendix B: MIPS Instructions
Opcode is 0
in MIPS R-
Type
instructions.
Funct defines
the operation

Recall: Funct in MIPS R-Type Instructions (II)
13
Harris and Harris, Appendix B: MIPS Instructions
Table B.2 R-type instructions, sorted by funct field—Cont’d
100000 (32) add rd, rs, rt add [rd] = [rs] + [rt]
100001 (33) addu rd, rs, rt add unsigned [rd] = [rs] + [rt]
100010 (34) sub rd, rs, rt subtract [rd] = [rs] – [rt]
100011 (35) subu rd, rs, rt subtract unsigned [rd] = [rs] – [rt]
100100 (36) and rd, rs, rt and [rd] = [rs] & [rt]
100101 (37) or rd, rs, rt or [rd] = [rs] | [rt]
100110 (38) xor rd, rs, rt xor [rd] = [rs] ^ [rt]
100111 (39) nor rd, rs, rt nor [rd] = ~([rs] | [rt])
101010 (42) slt rd, rs, rt set less than [rs] < [rt] ? [rd] = 1 : [rd] = 0
101011 (43) sltu rd, rs, rt set less than unsigned [rs] < [rt] ? [rd] = 1 : [rd] = 0
Table B.3 F-type instructions (fop = 16/17)
000000 (0) add.s fd, fs, ft /
add.d fd, fs, ft
FP add [fd] = [fs] + [ft]
000001 (1) sub.s fd, fs, ft /
sub.d fd, fs, ft
FP subtract [fd] = [fs] – [ft]
000010 (2) mul.s fd, fs, ft / FP multiply [fd] = [fs] × [ft]
622 APPENDIX B MIPS Instructions
n Find the complete list of instructions in the appendix

Data Types
n An ISA supports one or several data types
n LC-3 only supports 2’s complement integers
q Negative of a 2’s complement binary value X = NOT(X) + 1
n MIPS supports
q 2’s complement integers
q Unsigned integers
q Floating point
n Again, tradeoffs are involved
q What data types should be supported and what should not be?
14

Data Type Tradeoffs
n What is the benefit of having more or high-level data types
in the ISA?
n What is the disadvantage?
n Think compiler/programmer vs. microarchitect
n Concept of semantic gap
q Data types coupled tightly to the semantic level, or complexity
of instructions
n Example: Early RISC architectures vs. Intel 432
q Early RISC machines: Only integer data type
q Intel 432: Object data type, capability based machine
q VAX: Complex types, e.g., doubly-linked list
15

Addressing Modes
n An addressing mode is a mechanism for specifying where
an operand is located
n There five addressing modes in LC-3
q Immediate or literal (constant)
n The operand is in some bits of the instruction
q Register
n The operand is in one of R0 to R7 registers
q Three of them are memory addressing modes
n PC-relative
n Indirect
n Base+offset
n In addition, MIPS has pseudo-direct addressing (for j and
jal), but does not have indirect addressing
16

Operate Instructions
n In LC-3, there are three operate instructions
q NOT is a unary operation (one source operand)
n It executes bitwise NOT
q ADD and AND are binary operations (two source operands)
n ADD is 2’s complement addition
n AND is bitwise SR1 & SR2
n In MIPS, there are many more
q Most of R-type instructions (they are binary operations)
n E.g., add, and, nor, xor…
q I-type versions (i.e., with one immediate operand) of the R-
type operate instructions
q F-type operations, i.e., floating-point operations
18

n NOT assembly and machine code
NOT in LC-3
19
NOT R3, R5
LC-3 assembly
Field Values
Machine Code
9 3 5 1 1 1 1 1 1
OP DR SR
1 0 0 1 0 1 1 0 0 1 1 1 1 1 1 1
OP DR SR
15 12 11 9 8 6 0
5
5.2 Operate Instructions
16
16
R0
R1
R2
R3
R4
R5
R6
R7
A
ALU
NOT
B
0101000011110000
1010111100001111
Figure 5.4 Data path relevant to the execution of NOT R3, R5
Figure 5.4 shows the key parts of the data path that are used to perform the
NOT instruction shown here. Since NOT is a unary operation, only the A input
of the ALU is relevant. It is sourced from R5. The control signal to the ALU
directs the ALU to perform the bit-wise complement operation. The output of the
ALU (the result of the operation) is stored into R3.
Register file
SR
DR
From
FSM
There is no NOT in MIPS. How is it implemented?

Operate Instructions
n We are already familiar with LC-3’s ADD and AND with
register mode (R-type in MIPS)
n Now let us see the versions with one literal (i.e., immediate)
operand
n Subtraction is another necessary operation
q How is it implemented in LC-3 and MIPS?
20

Operate Instr. with one Literal in LC-3
n ADD and AND
q OP = operation
n E.g., ADD = 0001 (same OP as the register-mode ADD)
q DR ← SR1 + sign-extend(imm5)
n E.g., AND = 0101 (same OP as the register-mode AND)
q DR ← SR1 AND sign-extend(imm5)
q SR1 = source register
q DR = destination register
q imm5 = Literal or immediate (sign-extend to 16 bits)
21
OP DR SR1 1 imm5
4 bits 3 bits 3 bits 5 bits

n ADD assembly and machine code
ADD with one Literal in LC-3
22
ADD R1, R4, #-2
LC-3 assembly
Field Values
Machine Code
1 1 4 1 -2
OP DR SR imm5
0 0 0 1 0 0 1 1 0 0 1 1 1 1 1 0
OP DR SR imm5
15 12 11 9 8 6 0
5 4
If bit [5] is 1, the second source operand is contained within the instruction.
In fact, the second source operand is obtained by sign-extending bits [4:0] to 16
bits before performing the ADD or AND. Figure 5.5 shows the key parts of the
data path that are used to perform the instruction ADD R1, R4, #−2.
Since the immediate operand in an ADD or AND instruction must fit in
bits [4:0] of the instruction, not all 2’s complement integers can be imme-
diate operands. Which integers are OK (i.e., which integers can be used as
immediate operands)?
16
1 0
0001 001 100 1 11110
ADD R1 R4 –2
16
5
0000000000000100
A
B
ALU
Bit[5]
ADD
IR
1111111111111110
SEXT
R0
R1
R2
R3
R4
R5
R6
R7
0000000000000110
Figure 5.5 Data path relevant to the execution of ADD R1, R4, #-2
Register file
SR
DR
From
FSM
Instruction register
Sign-
extend

Instructions with one Literal in MIPS
n I-type
q 2 register operands and immediate
n Some operate and data movement instructions
q opcode = operation
q rs = source register
q rt =
n destination register in some instructions (e.g., addi, lw)
n source register in others (e.g., sw)
q imm = Literal or immediate
23
opcode rs rt imm

n Add immediate
Add with one Literal in MIPS
24
0 17 16 5
op rs rt imm
addi $s0, $s1, 5
MIPS assembly
Field Values
001000 10001 10010 0000 0000 0000 0101
op rs rt imm
Machine Code
0x22300005
rt ← rs + sign-extend(imm)

Subtract in LC-3
n MIPS assembly
n LC-3 assembly
n Tradeoff in LC-3
q More instructions
q But, simpler control logic
25
a = b + c - d; add $t0, $s0, $s1
sub $s3, $t0, $s2
High-level code MIPS assembly
a = b + c - d; ADD R2, R0, R1
NOT R4, R3
ADD R5, R4, #1
ADD R6, R2, R5
High-level code LC-3 assembly
2’s
complement
of R3

Subtract Immediate
n MIPS assembly
n LC-3
26
a = b - 3; subi $s1, $s0, 3
Is subi necessary in MIPS?
addi $s1, $s0, -3
MIPS assembly
a = b - 3; ADD R1, R0, #-3
High-level code LC-3 assembly

Data Movement Instructions
and Addressing Modes
27

Data Movement Instructions
n In LC-3, there are seven data movement instructions
q LD, LDR, LDI, LEA, ST, STR, STI
n Format of load and store instructions
q Opcode (bits [15:12])
q DR or SR (bits [11:9])
q Address generation bits (bits [8:0])
q Four ways to interpret bits, called addressing modes
n PC-Relative Mode
n Indirect Mode
n Base+offset Mode
n Immediate Mode
n In MIPS, there are only Base+offset and immediate modes
for load and store instructions
28

PC-Relative Addressing Mode
n LD (Load) and ST (Store)
q OP = opcode
n E.g., LD = 0010
n E.g., ST = 0011
q DR = destination register in LD
q SR = source register in ST
q LD: DR ← Memory[PC✝ + sign-extend(PCoffset9)]
q ST: Memory[PC✝ + sign-extend(PCoffset9)] ← SR
29
OP DR/SR PCoffset9
4 bits 3 bits 9 bits
15 14 13 12 11 10 9 8 7 6 2 1 0
5 4 3
✝This is the incremented PC

n LD assembly and machine code
LD in LC-3
30
LD R2, 0x1AF
LC-3 assembly
Field Values
Machine Code
2 2 0x1AF
OP DR PCoffset9
0 0 1 0 0 1 0 1 1 0 1 0 1 1 1 1
OP DR PCoffset9
15 12 11 9 8 0
5.3 Data Movement Instructions
16
16
16
16
1
R0
R1
R2
R3
R4
R5
R6
R7
0010 010 110101111
15 0
IR[8:0]
PC
IR
0100 0000 0001 1001 SEXT
MAR MDR
MEMORY
0000000000000101
ADD
LD R2 x1AF
1111111110101111
3
2
Figure 5.6 Data path relevant to execution of LD R2, x1AF
incremented PC (x4019) is added to the sign-extended value contained in IR[8:0]
(xFFAF), and the result (x3FC8) is loaded into the MAR. In step 2, memory is
read and the contents of x3FC8 are loaded into the MDR. Suppose the value stored
in x3FC8 is 5. In step 3, the value 5 is loaded into R2, completing the instruction
cycle.
Note that the address of the memory operand is limited to a small range of the
Register file
DR
Sign-
extend
Incremented PC
1. Address
calculation
2. Memory
read
3. DR is
loaded
The memory address is only +255 to -256
locations away of the LD or ST instruction
Limitation: The PC-relative addressing mode
cannot address far away from the
instruction

Indirect Addressing Mode
n LDI (Load Indirect) and STI (Store Indirect)
q OP = opcode
n E.g., LDI = 1010
n E.g., STI = 1011
q DR = destination register in LDI
q SR = source register in STI
q LDI: DR ← Memory[Memory[PC✝ + sign-extend(PCoffset9)]]
q STI: Memory[Memory[PC✝ + sign-extend(PCoffset9)]] ← SR
31
OP DR/SR PCoffset9
15 14 13 12 11 10 9 8 7 6 2 1 0
5 4 3

n LDI assembly and machine code
LDI in LC-3
32
LDI R3, 0x1CC
LC-3 assembly
Field Values
Machine Code
A 3 0x1CC
OP DR PCoffset9
1 0 1 0 0 1 1 1 1 1 0 0 1 1 0 0
OP DR PCoffset9
15 12 11 9 8 0
Now the address of the operand can be anywhere in the memory
is read and the contents of x49E8 (x2110) is loaded into the MDR. In step 3, since
x2110 is not the operand, but the address of the operand, it is loaded into the MAR.
In step 4, memory is again read, and the MDR again loaded. This time the MDR
is loaded with the contents of x2110. Suppose the value −1 is stored in memory
location x2110. In step 5, the contents of the MDR (i.e., −1) are loaded into R3,
completing the instruction cycle.
16
16
16
16
1
2
3 x2110
R0
R1
R2
R3
R4
R5
R6
R7
15 0
IR[8:0]
PC
IR
SEXT
MAR MDR
MEMORY
ADD
1111111111111111
1010 011 111001100
x1CC
R3
xFFCC
0100 1010 0001 1100
LDI
4
5
Figure 5.7 Data path relevant to the execution of LDI R3, x1CC
Register file
DR
Sign-
extend
Incremented PC
1. Address
calculation
2. Memory
read
5. DR is
loaded
4. Memory
read
3. Loaded
address
from MDR
to MAR

Base+Offset Addressing Mode
n LDR (Load Register) and STR (Store Register)
q OP = opcode
n E.g., LDR = 0110
n E.g., STR = 0111
q DR = destination register in LDR
q SR = source register in STR
q LDR: DR ← Memory[BaseR + sign-extend(offset6)]
q STR: Memory[BaseR + sign-extend(offset6)] ← SR
33
OP DR/SR offset6
15 14 13 12 11 10 9 8 7 6 2 1 0
5 4 3
BaseR
3 bits

n LDR assembly and machine code
LDR in LC-3
34
LDR R1, R2, 0x1D
LC-3 assembly
Again, the address of the operand can be anywhere in the memory
1. Address
calculation
2. Memory
read
3. DR is
loaded
Field Values
6 1 0x1D
OP DR offset6
2
BaseR
Machine Code
0 1 1 0 0 0 1 0 1 1 1 0 1
OP DR offset6
15 12 11 9 8 0
0 1 0
BaseR
6 5
loads R1 with the contents of x2362.
Figure 5.8 shows the relevant parts of the data path required to execute this
instruction. First the contents of R2 (x2345) are added to the sign-extended value
contained in IR[5:0] (x001D), and the result (x2362) is loaded into the MAR.
Second, memory is read, and the contents of x2362 are loaded into the MDR.
Suppose the value stored in memory location x2362 is x0F0F. Third, and finally,
the contents of the MDR (in this case, x0F0F) are loaded into R1.
16
16
1
16
2
R0
R1
R2
R3
R4
R5
R6
R7
MAR MDR
MEMORY
ADD
0000111100001111
0010001101000101
15 0
IR 1010 011 011
x1D
011101
SEXT
x001D
IR[5:0]
3
LDR R1 R2
Figure 5.8 Data path relevant to the execution of LDR R1, R2, x1D
Register file
DR
Sign-
extend
BaseR
001 010
0110

Base+Offset Addressing Mode in MIPS
n In MIPS, lw and sw use base+offset mode (or base
addressing mode)
n imm is the 16-bit offset, which is sign-extended to 32 bits
35
A[2] = a; sw $s3, 8($s0)
Memory[$s0 + 8] ← $s3
43 16 19 8
op rs rt imm
Field Values

An Example Program in MIPS and LC-3
36
a = A[0];
c = a + b - 5;
B[0] = c;
A = $s0
b = $s2
B = $s1
High-level code MIPS registers
LDR R5, R0, #0
ADD R6, R5, R2
ADD R7, R6, #-5
STR R7, R1, #0
LC-3 assembly
lw $t0, 0($s0)
add $t1, $t0, $s2
addi $t2, $t1, -5
sw $t2, 0($s1)
MIPS assembly
A = R0
b = R2
B = R1
LC-3 registers

Immediate Addressing Mode
n LEA (Load Effective Address)
q OP = 1110
q DR = destination register
q LEA: DR ← PC✝ + sign-extend(PCoffset9)
37
OP DR PCoffset9
15 14 13 12 11 10 9 8 7 6 2 1 0
5 4 3
What is the difference from PC-Relative addressing mode?
Answer: Instructions with PC-Relative mode access memory,
but LEA does not à Hence the name Load Effective Address

n LEA assembly and machine code
LEA in LC-3
38
LEA R5, #-3
LC-3 assembly
Field Values
Machine Code
E 5 0x1FD
OP DR PCoffset9
1 1 1 0 1 0 1 1 1 1 1 1 1 1 0 1
OP DR PCoffset9
15 12 11 9 8 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 0 1 0 1 1 1 1 1 1 1 1 0 1
LEA R5 −3
R5 will contain x4016 after the instruction at x4018 is executed.
Figure 5.9 shows the relevant parts of the data path required to execute the
LEA instruction. Note that no access to memory is required to obtain the value
to be loaded.
16
16
16
R0
R1
R2
R3
R4
R5
R6
R7
15 0
IR[8:0]
PC
IR
0100 0000 0001 1001 SEXT
ADD
1111111111111101
0100000000010110
LEA R5 x1FD
111111101
101
1110
Figure 5.9 Data path relevant to the execution of LEA R5, #−3
Register file
DR
Sign-
extend
Incremented PC

Immediate Addressing Mode in MIPS
n In MIPS, lui (load upper immediate) loads a 16-bit
immediate into the upper half of a register and sets the
lower half to 0
n It is used to assign 32-bit constants to a register
39
a = 0x6d5e4f3c; # $s0 = a
lui $s0, 0x6d5e
ori $s0, 0x4f3c

Addressing Example in LC-3
n What is the final value of R3?
40
The third instruction to be executed is stored in x30F8. The opcode 0011
specifies the ST instruction, which stores the contents of the register specified by
bits [11:9] of the instruction into the memory location whose address is computed
using the PC-relative addressing mode. That is, the address is computed by adding
the incremented PC to the 16-bit value obtained by sign-extending bits [8:0] of
the instruction. The 16-bit value obtained by sign-extending bits [8:0] of the
instruction is xFFFB. The incremented PC is x30F9. Therefore, at the end of
Address 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
x30F6 1 1 1 0 0 0 1 1 1 1 1 1 1 1 0 1 R1<- PC-3
x30F7 0 0 0 1 0 1 0 0 0 1 1 0 1 1 1 0 R2<- R1+14
x30F8 0 0 1 1 0 1 0 1 1 1 1 1 1 0 1 1 M[x30F4]<- R2
x30F9 0 1 0 1 0 1 0 0 1 0 1 0 0 0 0 0 R2<- 0
x30FA 0 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 R2<- R2+5
x30FB 0 1 1 1 0 1 0 0 0 1 0 0 1 1 1 0 M[R1+14]<- R2
x30FC 1 0 1 0 0 1 1 1 1 1 1 1 0 1 1 1 R3<- M[M[x3F04]]
Figure 5.10 Addressing mode example
x30F4
P&P, Chapter 5.3.5

n What is the final value of R3?
n The final value of R3 is 5
The third instruction to be executed is stored in x30F8. The opcode 0011
specifies the ST instruction, which stores the contents of the register specified by
bits [11:9] of the instruction into the memory location whose address is computed
using the PC-relative addressing mode. That is, the address is computed by adding
the incremented PC to the 16-bit value obtained by sign-extending bits [8:0] of
the instruction. The 16-bit value obtained by sign-extending bits [8:0] of the
instruction is xFFFB. The incremented PC is x30F9. Therefore, at the end of
Address 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
x30F6 1 1 1 0 0 0 1 1 1 1 1 1 1 1 0 1 R1<- PC-3
x30F7 0 0 0 1 0 1 0 0 0 1 1 0 1 1 1 0 R2<- R1+14
x30F8 0 0 1 1 0 1 0 1 1 1 1 1 1 0 1 1 M[x30F4]<- R2
x30F9 0 1 0 1 0 1 0 0 1 0 1 0 0 0 0 0 R2<- 0
x30FA 0 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 R2<- R2+5
x30FB 0 1 1 1 0 1 0 0 0 1 0 0 1 1 1 0 M[R1+14]<- R2
x30FC 1 0 1 0 0 1 1 1 1 1 1 1 0 1 1 1 R3<- M[M[x3F04]]
Figure 5.10 Addressing mode example
x30F4
Addressing Example in LC-3
41
LEA
ADD
ST
AND
ADD
STR
LDI
-3
14
-5
5
14
-9
0
R3 = M[M[PC – 9]] = M[M[0x30FD – 9]] =
R1 = PC – 3 = 0x30F7 – 3 = 0x30F4
R2 = R1 + 14 = 0x30F4 + 14 = 0x3102
M[PC - 5] = M[0x030F4] = 0x3102
R2 = 0
R2 = R2 + 5 = 5
M[R1 + 14] = M[0x30F4 + 14] = M[0x3102] = 5
M[M[0x30F4]] = M[0x3102] = 5
P&P, Chapter 5.3.5

Control Flow Instructions
n Allow a program to execute out of sequence
n Conditional branches and jumps
q Conditional branches are used to make decisions
n E.g., if-else statement
q In LC-3, three condition codes are used
q Jumps are used to implement
n Loops
n Function calls
q JMP in LC-3 and j in MIPS
43

Condition Codes in LC-3
n Each time one GPR (R0-R7) is written, three single-bit registers
are updated
n Each of these condition codes are either set (set to 1) or cleared
(set to 0)
q If the written value is negative
n N is set, Z and P are cleared
q If the written value is zero
n Z is set, N and P are cleared
q If the written value is positive
n P is set, N and Z are cleared
n x86 and SPARC are examples of ISAs that use condition codes
44

Conditional Branches in LC-3
n BRz (Branch if Zero)
q n, z, p = which condition code is tested (N, Z, and/or P)
n n, z, p: instruction bits to identify the condition codes to be tested
n N, Z, P: values of the corresponding condition codes
q PCoffset9 = immediate or constant value
q if ((n AND N) OR (p AND P) OR (z AND Z))
n then PC ← PC✝ + sign-extend(PCoffset9)
q Variations: BRn, BRz, BRp, BRzp, BRnp, BRnz, BRnzp
45
BRz PCoffset9
0000 n PCoffset9
4 bits 9 bits
z p

Conditional Branches in LC-3
n BRz
46
BRz 0x0D9
What if n = z = p = 1?*
(i.e., BRnzp)
And what if n = z = p = 0?
132 chapter 5 The LC-3
16
SEXT
16 16
PCMUX
ADD
0000000011011001
IR 0
1
0
N Z P PCoffset9
BR
0000 011011001
9
Yes!
P
Z
N
0 1 0
PC 0100 0000 0010 1000
0100 0001 0000 0001
Figure 5.11 Data path relevant to the execution of BRz x0D9
Instruction
register
Program
Counter
Condition
registers
n z p
*n, z, p are the instruction bits to identify the condition codes to be tested

Conditional Branches in MIPS
n beq (Branch if Equal)
q 4 = opcode
q rs, rt = source registers
q offset = immediate or constant value
q if rs == rt
n then PC ← PC✝ + sign-extend(offset) * 4
q Variations: beq, bne, blez, bgtz
47
4 rs rt offset
beq $s0, $s1, offset

n This is an example of tradeoff in the instruction set
q The same functionality requires more instructions in LC-3
q But, the control logic requires more complexity in MIPS
beq $s0, $s1, offset
Branch If Equal in MIPS and LC-3
48
LC-3 assembly
MIPS assembly
NOT R2, R1
ADD R3, R2, #1
ADD R4, R3, R0
BRz offset
Subtract
(R0 - R1)

Lecture Summary
n Instruction Set Architectures: LC-3 and MIPS
q Operate instructions
q Data movement instructions
q Control instructions
n Instruction formats
n Addressing modes
49

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