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Introduction of
Direct Memory Access (DMA)
Why is DMA?
• It is wasteful to feed data into a controller
register 1 bytes at a time. (PIO)
• The DMA unit is word.
• In the high loading environment, a system
with DMA has better improvement.
DMA transfer
5. DMA controllertransfersbytes
tobufferX, increasingmemory
addressanddecreasingC until C=0
6. whenC=0, DMA interrupts CPU
tosignal transfercompletion
PCI bus
CPU m
em
ory bus Mem
ory buffer
DMA/bus/
interrupt
controller
cache
CPU
1. devicedriver toldtotransferdisk
datatobufferataddressX
2. devicedriver tellsdisk controllerto
transferC bytesfromdisk tobufferat
addressX
3. disk controllerinitiates
DMA transfer
4. disk controllersendseach
bytetoDMA controller
IDE disk
controller
disk
disk
disk
disk
X
DMA Progress
• To initiate a DMA transfer, the host writes a
DMA command into memory:
– A pointer to the source of a transfer
– A count of the number of bytes to be transferred
– ……..
• The CPU writes the address of the DMA
command block to the DMA controller.
DMA Progress (cont.)
• The DMA controller proceeds to operate the
memory bus directly without CPU help.
• Handshaking exists between DMA
controller and device controller.
• When the entire transfer is finished, the
DMA controller will interrupts the CPU.
Handshaking
• DMA-request and DMA_acknowledge
– When a word of data is available, the device
controller places a signal on the DMA-request
wire.
– The signal causes the DMA controller to seize
the memory bus,
• To place the desired address on the memory-address
wire
• To place a signal on the DMA-acknowledge wire
Handshaking (cont.)
• When the device controller receives the
DMA-acknowledge signal,
– it transfer the word of data to memory
– and remove the DMA_request signal.

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Direct Memory Access (DMA) E_systems.ppt

  • 2. Why is DMA? • It is wasteful to feed data into a controller register 1 bytes at a time. (PIO) • The DMA unit is word. • In the high loading environment, a system with DMA has better improvement.
  • 3. DMA transfer 5. DMA controllertransfersbytes tobufferX, increasingmemory addressanddecreasingC until C=0 6. whenC=0, DMA interrupts CPU tosignal transfercompletion PCI bus CPU m em ory bus Mem ory buffer DMA/bus/ interrupt controller cache CPU 1. devicedriver toldtotransferdisk datatobufferataddressX 2. devicedriver tellsdisk controllerto transferC bytesfromdisk tobufferat addressX 3. disk controllerinitiates DMA transfer 4. disk controllersendseach bytetoDMA controller IDE disk controller disk disk disk disk X
  • 4. DMA Progress • To initiate a DMA transfer, the host writes a DMA command into memory: – A pointer to the source of a transfer – A count of the number of bytes to be transferred – …….. • The CPU writes the address of the DMA command block to the DMA controller.
  • 5. DMA Progress (cont.) • The DMA controller proceeds to operate the memory bus directly without CPU help. • Handshaking exists between DMA controller and device controller. • When the entire transfer is finished, the DMA controller will interrupts the CPU.
  • 6. Handshaking • DMA-request and DMA_acknowledge – When a word of data is available, the device controller places a signal on the DMA-request wire. – The signal causes the DMA controller to seize the memory bus, • To place the desired address on the memory-address wire • To place a signal on the DMA-acknowledge wire
  • 7. Handshaking (cont.) • When the device controller receives the DMA-acknowledge signal, – it transfer the word of data to memory – and remove the DMA_request signal.