SlideShare a Scribd company logo
2
Most read
6
Most read
14
Most read
Lecture 22 : Decoder Circuit, Types, Larger
Decoders
Digital Logic Design
1
Decoder
What is the function of a decoder?
It selects or de-select one of the devices
2
Decoder
A decoder is a combinational circuit that converts binary
information from n input lines to a maximum of 2n unique output
output lines. Only one output can be active (high) at any time
If the n-bit coded information has unused combinations, the
decoder has fewer than 2n outputs
3
3-to-8-Line Decoder
A 3-to-8-Line Decoder is a decoder in which three inputs are
decoded into eight outputs, each representing one of the
minterms of the three input variables
Each one of the eight AND gates generates one of the minterms
A particular application of this decoder is binary-to-octal
conversion, however 3-to-8-line decoder can be used for
decoding any 3-bit code to provide eight outputs, one for each
element of the code
4
Inputs Outputs
X Y Z D0 D1 D2 D3 D4 D5 D6 D7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
3-to-8-Line Decoder Truth Table
5
3-to-8-Line Decoder Implementation
6
Overview of Last Lecture
What is the function of a decoder?
It selects or de-select one of the devices
7
Today’s Lecture
Decoder internal circuit
Decoders with NAND gates
Four Type of Decoders
Constructing large Decoders
8
3-to-8-Line Decoder
A 3-to-8-Line Decoder is a decoder in which three inputs are
decoded into eight outputs, each representing one of the
minterms of the three input variables
Each one of the eight AND gates generates one of the minterms
A particular application of this decoder is binary-to-octal
conversion, however 3-to-8-line decoder can be used for
decoding any 3-bit code to provide eight outputs, one for each
element of the code
9
Inputs Outputs
X Y Z D0 D1 D2 D3 D4 D5 D6 D7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
3-to-8-Line Decoder Truth Table
10
3-to-8-Line Decoder Implementation
11
Decoders with NAND gates
Some decoders are constructed with NAND gates. Since a NAND gate produces the
AND operation with inverted output, it becomes more economical to generate the
decoder minterms in their complemented form. Decoder include one or more enable
inputs to control the circuit operation
A 2-to4-line decoder with an enable input is shown next. (see fig).
The circuit operates with complement outputs and a complement enable input.
The decoder is enabled when E is equal to 0 and disabled when E = 1
The output whose value is equal to 0 represents the minterm selected
by inputs A and B.
Only one output can be zero at any given time, all other outputs are 1
Some decoders have two or more enable inputs that must satisfy a given logic
condition
12
Decoders with NAND gates
13
Four Type of Decoders
Active High Enable, Active High Output
Active Low Enable, Active High Output
Active High Enable, Active Low Output
Active Low Enable, Active Low Output
14
End of Lecture
15

More Related Content

PPT
Number System
PDF
Ite essentials apostila part 01
PPTX
Optimization Deep Dive: Unreal Engine 4 on Intel
PPTX
ATT SMK.pptx
PPT
STLD-Combinational logic design
PPTX
decorder and encoder and its applications
PDF
Lecture 8 Decoders & Encoders (combinational circuits)
PDF
Combinational circuits
Number System
Ite essentials apostila part 01
Optimization Deep Dive: Unreal Engine 4 on Intel
ATT SMK.pptx
STLD-Combinational logic design
decorder and encoder and its applications
Lecture 8 Decoders & Encoders (combinational circuits)
Combinational circuits

Similar to DLD Lecture No 22 Decoder Circuit and Types of Decoder.pptx (20)

PPT
Week_7_and_8_-_Lecture_2_of_3-_Decoders_and_Encoders1.ppt
PDF
UNIT3.3.pdf
PDF
Combinational Circuits - II (Encoders, Decoders, Multiplexers & PIDs).pdf
PPTX
Digital Logic Design Lectures on Flip-flops and latches and counters
PPT
Chapter 4 combinational circuit
PPT
11.ppt
PPTX
ENG 202 – Digital Electronics 1 - Chapter 4 (1).pptx
PPTX
decoders121-170714184489769876987698749.pptx
PDF
Digital logic-formula-notes-final-1
DOCX
Types of encoders and decoders with truth tables
PPTX
multiplexer and d-multiplexer
PDF
Decoders
PPTX
Encoder-and-decoder.pptx
PPT
Combinational circuit
PPTX
Decoders-Digital Electronics
PPT
217456070-Chapter-3_eletrical engineering
PPTX
Computer System and Architecture
PPTX
Decoders decoderand design with their.pptx
PPT
Lcdf4 chap 03_p2
PPTX
Combinational_Logic_Circuit for Digital Logic
Week_7_and_8_-_Lecture_2_of_3-_Decoders_and_Encoders1.ppt
UNIT3.3.pdf
Combinational Circuits - II (Encoders, Decoders, Multiplexers & PIDs).pdf
Digital Logic Design Lectures on Flip-flops and latches and counters
Chapter 4 combinational circuit
11.ppt
ENG 202 – Digital Electronics 1 - Chapter 4 (1).pptx
decoders121-170714184489769876987698749.pptx
Digital logic-formula-notes-final-1
Types of encoders and decoders with truth tables
multiplexer and d-multiplexer
Decoders
Encoder-and-decoder.pptx
Combinational circuit
Decoders-Digital Electronics
217456070-Chapter-3_eletrical engineering
Computer System and Architecture
Decoders decoderand design with their.pptx
Lcdf4 chap 03_p2
Combinational_Logic_Circuit for Digital Logic
Ad

More from SaveraAyub2 (7)

PPTX
DLD Lecture No 21 BCD Multiplier and Magnitude Comparator.pptx
PPTX
DLD Lecture No 20 Look Ahead Carry Generator, Binary Subtractors and BCD Add...
PPTX
DLD Lecture No 19 Binary adders.pptx
PPTX
DLD Lecture No 18 Analysis and Design of Combinational Circuit.pptx
PPTX
DLD Lecture No 16 Don't `Care Conditions, Nand gate Implementation.pptx
PPTX
DLD Lecture No 15 Prime and Essential Implicants, Five Variable Map.pptx
PPTX
presentation
DLD Lecture No 21 BCD Multiplier and Magnitude Comparator.pptx
DLD Lecture No 20 Look Ahead Carry Generator, Binary Subtractors and BCD Add...
DLD Lecture No 19 Binary adders.pptx
DLD Lecture No 18 Analysis and Design of Combinational Circuit.pptx
DLD Lecture No 16 Don't `Care Conditions, Nand gate Implementation.pptx
DLD Lecture No 15 Prime and Essential Implicants, Five Variable Map.pptx
presentation
Ad

Recently uploaded (19)

PDF
TIM Group - Results Presentation H1 '25.pdf
PPTX
TTL1_LMS-Presenfdufgdfgdgduhfudftation.pptx
PDF
202507_Sansan presentation materials FY2024
PDF
Cyberagent_For New Investors_EN_250808.pdf
PDF
Investor Presentation - Q2 FY 25 - 6 November 2024.pdf
PDF
Collective Mining | Corporate Presentation - August 2025
PDF
Corporate Finance, 12th Edition, Stephen Ross, Randolph Westerfield, Jeffrey ...
PDF
Methanex Investor Presentation - July 2025
PPTX
North Arrow Corporate Update for August 5, 2025
PDF
How to Analyze Market Trends in Precious Metal.pdf
PPTX
HealthIllnessSociety.pptxjjjjjjjjjjjjjjjjj
PDF
Update on North Arrow Minerals and the Kraaipan Gold Project, Botswanaf
PDF
OR Royalties Inc. - Q2 2025 Results, August 6, 2025
PPTX
Chemistry.pptxjhghjgghgyughgyghhhvhbhghjbjb
PPTX
investment-opportunities-in-rajasthan.pptx
DOC
École毕业证学历认证,劳伦森大学毕业证毕业证文凭
PDF
Probe Gold Corporate Presentation Aug 2025 Final.pdf
PDF
North Arrow Minerals Corporate and Kraaipan Project Update
PDF
OR Royalties Inc. - Corporate Presentation, August 2025
TIM Group - Results Presentation H1 '25.pdf
TTL1_LMS-Presenfdufgdfgdgduhfudftation.pptx
202507_Sansan presentation materials FY2024
Cyberagent_For New Investors_EN_250808.pdf
Investor Presentation - Q2 FY 25 - 6 November 2024.pdf
Collective Mining | Corporate Presentation - August 2025
Corporate Finance, 12th Edition, Stephen Ross, Randolph Westerfield, Jeffrey ...
Methanex Investor Presentation - July 2025
North Arrow Corporate Update for August 5, 2025
How to Analyze Market Trends in Precious Metal.pdf
HealthIllnessSociety.pptxjjjjjjjjjjjjjjjjj
Update on North Arrow Minerals and the Kraaipan Gold Project, Botswanaf
OR Royalties Inc. - Q2 2025 Results, August 6, 2025
Chemistry.pptxjhghjgghgyughgyghhhvhbhghjbjb
investment-opportunities-in-rajasthan.pptx
École毕业证学历认证,劳伦森大学毕业证毕业证文凭
Probe Gold Corporate Presentation Aug 2025 Final.pdf
North Arrow Minerals Corporate and Kraaipan Project Update
OR Royalties Inc. - Corporate Presentation, August 2025

DLD Lecture No 22 Decoder Circuit and Types of Decoder.pptx

  • 1. Lecture 22 : Decoder Circuit, Types, Larger Decoders Digital Logic Design 1
  • 2. Decoder What is the function of a decoder? It selects or de-select one of the devices 2
  • 3. Decoder A decoder is a combinational circuit that converts binary information from n input lines to a maximum of 2n unique output output lines. Only one output can be active (high) at any time If the n-bit coded information has unused combinations, the decoder has fewer than 2n outputs 3
  • 4. 3-to-8-Line Decoder A 3-to-8-Line Decoder is a decoder in which three inputs are decoded into eight outputs, each representing one of the minterms of the three input variables Each one of the eight AND gates generates one of the minterms A particular application of this decoder is binary-to-octal conversion, however 3-to-8-line decoder can be used for decoding any 3-bit code to provide eight outputs, one for each element of the code 4
  • 5. Inputs Outputs X Y Z D0 D1 D2 D3 D4 D5 D6 D7 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 1 3-to-8-Line Decoder Truth Table 5
  • 7. Overview of Last Lecture What is the function of a decoder? It selects or de-select one of the devices 7
  • 8. Today’s Lecture Decoder internal circuit Decoders with NAND gates Four Type of Decoders Constructing large Decoders 8
  • 9. 3-to-8-Line Decoder A 3-to-8-Line Decoder is a decoder in which three inputs are decoded into eight outputs, each representing one of the minterms of the three input variables Each one of the eight AND gates generates one of the minterms A particular application of this decoder is binary-to-octal conversion, however 3-to-8-line decoder can be used for decoding any 3-bit code to provide eight outputs, one for each element of the code 9
  • 10. Inputs Outputs X Y Z D0 D1 D2 D3 D4 D5 D6 D7 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 1 3-to-8-Line Decoder Truth Table 10
  • 12. Decoders with NAND gates Some decoders are constructed with NAND gates. Since a NAND gate produces the AND operation with inverted output, it becomes more economical to generate the decoder minterms in their complemented form. Decoder include one or more enable inputs to control the circuit operation A 2-to4-line decoder with an enable input is shown next. (see fig). The circuit operates with complement outputs and a complement enable input. The decoder is enabled when E is equal to 0 and disabled when E = 1 The output whose value is equal to 0 represents the minterm selected by inputs A and B. Only one output can be zero at any given time, all other outputs are 1 Some decoders have two or more enable inputs that must satisfy a given logic condition 12
  • 13. Decoders with NAND gates 13
  • 14. Four Type of Decoders Active High Enable, Active High Output Active Low Enable, Active High Output Active High Enable, Active Low Output Active Low Enable, Active Low Output 14

Editor's Notes

  • #3: Give examples of switching on one of the devices, TV, Fridge, Microwave, AC Example of Memory address lines to select memory location Example of Automatic Masala selection