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- 2. Contents Introduction What is Verilog What is system Verilog What is verification How to verify Why system Verilog for verification Difference between Verilog and system Verilog Verification methodology assertion method when we run the Verilog program, if there is any error in Verilog code, the code doesn’t run and difficult to identify the errors and also don’t know where the errors happened. Assertion is an instruction verification tools to check errors in Verilog code. Two type : immediate (assert) and concurrent (assert property).. Immediate assertion: similar to the if statement. The difference is that an if statement does not assert that an expression should be true, it simply checks that it is true, e.g.: if (A == B) ... // Simply checks if A equals B assert (A == B); // Asserts that A equals B; if not, an error is generated If the conditional expression of the immediate assert evaluates to X, Z or 0, then the assertion fails and the simulator writes an error message. An immediate assertion may include a pass statement and/or a fail statement. In our example the pass statement is omitted, so no action is taken when the assert expression is true. If the pass statement exists: assert (A == B) $display ("OK. A equals B");
- 3. introduction What is Verilog? Verilog is a Hardware Description Language(HDL) which is a textual format for describing electronic circuits and systems. Applied to electronic design and Verilog is intended to be used for verification through simulation, timing analysis, test analysis and logic synthesis. What is system Verilog? System Verilog is Hardware Description and Verification Language (HDVL). it combines the features of HDL such as Verilog and VHDL with features from specialized Hardware Verification Languages, together with features from C and C++. System Verilog first became an official IEEE standard (IEEE 1800™) in 2005, was updated with IEEE 1800™ 2009. What is verification? Verification is the process of ensuring that a given hardware design works as expected. Chip design is a very extensive and time consuming process and costs millions to fabricate. Functional defects in the design if caught at an earlier stage in the design process will help save costs.
- 4. Why system Verilog for verification Verilog was initially used for writing testbench But, writing complex testbenches is much more of a programming task than describing hardware. No need to synthesize testbench. Universal Verification Methodology(UVM) is replacing SV based verification in industry. UVM = Structured SV
- 5. SV features Assertion verification Functional coverage driven verification OOP support(classes, structures) New data types(logic) Constrained randomization
- 6. Assertion Immediate assertion Immediate assertions are executed based on simulation event semantics and are required to be specified in a procedural block. It is treated the same way as the expression in a if statement during simulation. The immediate assertion will pass if the expression holds true at the time when the statement is executed, and will fail if the expression evaluates to be false (X, Z or 0). Concurrent Assertions the behavior of a design may be specified using statements similar to these "The Read and Write signals should never be asserted together." "A Request should be followed by an Acknowledge occurring no more than two clocks after the Request is asserted.“ Concurrent assertions are used to check behavior such as this. These are statements that assert that specified properties must be true.