Efficient Testing of Chiplet-Based SiPs - 20250121_PreConH_Pendurkar_Tarde.pdf
- 1. Efficient Testing of Chiplet-Based SiPs Open Chiplet Economy OCP Sponsored Tutorial Chiplet Summit January 21st 2025 1:00 pm to 5:00 pm Santa Clara California, USA Rajesh Pendurkar, Aparna Tarde
- 2. Contributors Rajesh Pendurkar, UCSC Silicon Valley Extension Aparna Tarde, Synopsys Mike Bartley, Tessolve, Boon Chong Ang, Intel Anand Muthaiah, Tessolve, Madhumita Sanya, Synopsys Source: System in Package Testing OCP Contribution
- 3. From Ideas to Impact Outline Chiplet Test Problem DFT Strategies System Level and Functional Test Known Good Die (KGD) Testing Test Cost Test Standards
- 4. From Ideas to Impact Problem statement • Multi-die designs are growing • One bad die can cause the whole package to fail • Challenges in chiplet testing : ⎻ DFT Standard (Chiplets come from different vendors) • Structural Defect Coverage of the individual chiplets • Standards Interoperability • Known Good Die (KGD) Known Good Stack (KGS) ⎻ Architecture • Hierarchical Test Architecture including Repair • Individual Chiplets Test data to be available for the final product company ⎻ Functional Test • Reuse of chiplet level tests at System Level (SLT) • Use Case Scenarios; Varying Load conditions
- 5. From Ideas to Impact Chiplet Based SiPs
- 6. From Ideas to Impact Status of Chiplet Test • Existing example solution for chiplet test • IEEE P1838+1149.1 • Scan traffic over Native PCIe/USB protocol • Muxed with PCIe/USB/other HSIO phy • Direct IOs through active interposer with isolation mode
- 7. From Ideas to Impact Design for Test (DFT) Strategies • Design for Test (DFT) : These are Structured Techniques ⎻ Scan & ATPG (Automatic Test Pattern Generation) Controllability /Observability ⎻ Memory/Logic BIST (Built In Self-Test) ⎻ Hierarchical Test ⎻ IEEE 1149.X Boundary Scan Standard ⎻ IEEE P1500 Standard for Embedded Cores ⎻ IEEE 1687 for Embedded Instruments ⎻ IEEE 1838 3D test architecture • Design for Test (DFT) Techniques ⎻ Upfront Investment not an Overhead ⎻ Test Standards help reduce cost by mandating compatibility, inter- operability ⎻ Helps bridge the Silicon Process Technology and ATE Technology
- 8. From Ideas to Impact 2.5D DFT Methodology Leveraging SSN Source: D2D Chiplet Interface Testing
- 9. From Ideas to Impact 3D DFT Methodology Leveraging SSN
- 10. From Ideas to Impact System Level Test (SLT) and Functional Test • SLT in SoC focuses on function to complement traditional structural test • Can have an even bigger impact on chiplet testing
- 11. From Ideas to Impact Known Good Die (KGD) Testing and Assembly Yield Recovery Source: Synopsys Test & Repair Solution • Die assembly with interposer can impact overall final Multi-die SoC yield ⎻ Risk is higher for micro-bumps with small pitch traces and 1000’s of micro-bumps • In Advanced packages, UCIe PHY implements test & repair ⎻ Action triggered at PHY initialization or on-demand ⎻ Faulty links re-routed through built-in repair pins ⎻ Interface “signature” stored for later usage • For standard packages, UCIe-S PHY supports degraded operation mode ⎻ Half of PHY can be shut down if faulty pin identified ⎻ Yield of die assembly with substrates is high
- 12. From Ideas to Impact Accelerating Test for Cost Reduction • Target test cost is not to exceed 20% of the die cost as a rule of thumb. • Factors that influence testing cost: • # of scan patterns, scan chain length, and scan shift frequency.. • test compression and increasing shift frequency. • known good die (KGD) after packaging impacts gross margin. • Parallel chiplet testing can reduce final test cost Reference: OCP, Business Analysis of Chiplet-Based Systems and Technology
- 13. From Ideas to Impact Device Scrap Cost • Monolithic devices • Chiplet Device Scrap Cost
- 14. From Ideas to Impact Comparisons of Test Costs
- 15. From Ideas to Impact Test Standards for Interoperability • IEEE 1149.1 (JTAG) - Standard for Test Access Port and Boundary-Scan Architecture • IEEE 1687 - Standard for Access and Control of Instrumentation Embedded within a Semiconductor Device • IEEE 1838 - Standard for test access architecture for 3D stacked IC • IEEE 3405 - Standard for Chiplet Interconnect Test and Repair
- 16. From Ideas to Impact Conclusion The paper underscored the importance of adapting the existing DFT technologies and test cost models to scale to new challenges facing chiplet technology. This paper contribution in summarizing the current industry trend and challenges in D2D chiplet interface testing. Specifically • The DFT strategies that will be making significant impact in the chiplet based systems. • How test acceleration can reduce overall cost • The importance of KGD in the process of building highest quality SiP product for better yield • Assembly Yield Recovery • Understanding of overall test cost structure • The key test standards
- 17. From Ideas to Impact Thank You • SiP Test work stream under Open Chiplet Economy subgroup of OCP is actively continuing development. We welcome you to contribute and share ideas • Contact: Rajesh Pendurkar (rpendurk@ucsc.edu or rpendurk@gmail.com) / Mike Bartley (mike.bartley@tessolve.com) to join the workstream