emerging memory technologies Document

EMERGING MEMORIES

CHAPTER 1
EMERGING MEMORY TECHNOLOGIES
1.1. INTRODUCTION:

In the history of technology, emerging technologies are contemporary advances and
innovation in various fields of technology. Various converging technologies have emerged in
the technological convergence of different systems evolving towards similar goals. Convergence
can refer to previously separate technologies such as voice (and telephony features), data (and
productivity applications) and video that now share resources and interact with each other,
creating new efficiencies.

Emerging technologies are those technical innovations which represent progressive
developments within a field for competitive advantage converging technologies represent
previously distinct fields which are in some way moving towards stronger inter-connection and
similar goals. However, the opinion on the degree of impact, status and economic viability of
several emerging and converging technologies vary.

1.2. History of Emerging Technologies:

Emerging technologies in general denote significant technology developments that
broach new territory in some significant way in their field. Examples of currently emerging
technologies

include information

technology, nanotechnology, biotechnology, cognitive

science, robotics, and artificial intelligence.

Over centuries, innovative methods and new technologies are developed and opened up.
Some of these technologies are due to theoretical research, and others from commercial research
and development.

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Technological growth includes incremental developments and disruptive technologies.
An example of the former was the gradual roll-out of DVD as a development intended to follow
on from the previous optical technology Compact Disc. By contrast, disruptive technologies are
those where a new method replaces the previous technology and make it redundant, for example,
the replacement of horse-drawn carriages by automobiles. This change continues into
the contemporary day.

Technology scaling of SRAM and DRAM, the common memory technologies used in the
traditional memory hierarchy, are increasingly constrained by fundamental technology limits. In
particular, the increasing leakage power for SRAM and DRAM and the increasing refresh
dynamic power for DRAM have posed challenges to circuit and architecture designers of future
memory hierarchy designs. Emerging memory technologies such as spin transfer torque RAM
(STT-RAM), phase-change RAM (PCRAM), and resistive RAM (RRAM) are being explored as
potential alternatives to existing memories in future computing systems. Such emerging
nonvolatile memory (NVM) technologies combine the speed of SRAM, the density of DRAM,
and the non volatility of flash memory, and so become very attractive as alternatives for the
future memory hierarchies. As emerging memory technologies mature, computer architects need
to understand the benefits and limitations of such technologies so that they can better use them to
improve the performance, power, and reliability of future computer architectures.

Many promising candidates, such as PCRAM, STTRAM, RRAM, and memristor, have
gained substantial attention of late and are being actively investigated by industry. Two of the
most promising memory technologies are STT-RAM and PCRAM. STT-RAM is a new type of
magnetic RAM that features non volatility, fast writing and reading speeds (< 10 ns), high
programming endurance (> 1,015cycles), and zero standby power. The storage capability or
programmability of MRAM arises from a magnetic tunneling junction (MTJ), in which a thin
tunneling dielectric for example, magnesium oxide (MgO) is sandwiched between two
ferromagnetic layers, as Figure shows. One ferromagnetic layer (the pinned layer) is designed to
have its magnetization pinned, whereas the magnetization of the other layer (the free layer) can
be flipped by a write event. An MTJ has a low resistance if the magnetizations of both the free
and the pinned layers have the same polarity; it has a high resistance if the magnetizations have

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opposite polarity. Prototype STT-RAM chips have been demonstrated at recent industry
conferences, and commercial MRAM products have been launched by companies such as
Everspin and NEC. PCRAM technology is based on a chalcogenide alloy, typically Ge2Sb2Te5
(GST) material. PCRAM’s data storage capability is achieved from the resistance differences
between an amorphous (high resistance) and crystalline (low resistance) phase of the
chalcogenide-based material. In set operations, the phase-change material is crystallized by
applying an electrical pulse that heats a significant portion of the cell above its crystallization
temperature. In reset operations, a larger electrical current is applied and then abruptly cut off to
melt and then quench the material, leaving it in an amorphous state. Compared to STT-RAM,
PCRAM is even denser, with an approximate cell area of 6 to 12F2, where F is the feature size.
In addition, phase-change material has a key advantage with its excellent scalability within
current CMOS fabrication methodologies, featuring continuous density improvement. Many
PCRAM prototypes

have

been demonstrated by,

for

example,

Hitachi,

Samsung,

STMicroelectronics, and Numonyx.

1.3. Non-Volatile Memory:
Nonvolatile memory, NVM or non-volatile storage is computer memory that can get back
stored information even when not powered. Examples of non-volatile memory include read-only
memory, flash memory, ferroelectric RAM (F-RAM), most types of magnetic computer
storage devices (e.g. hard disks, floppy disks, and magnetic tape), optical discs, and early
computer storage methods such as paper tape and punched cards.

Non-volatile memory is typically used for the task of secondary storage, or long-term
persistent storage. The most widely used form of primary storage today is a volatile form
of random access memory (RAM), meaning that when the computer is shut down, anything
contained in RAM is lost. Unfortunately, most forms of non-volatile memory have limitations
that make them unsuitable for use as primary storage. Typically, non-volatile memory either
costs more or has a poorer performance than volatile random access memory.

Several companies are working on developing non-volatile memory systems comparable
in speed and capacity to volatile RAM. IBM is currently developing MRAM (Magneto resistive

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RAM). Not only would such technology save energy, but it would allow for computers that
could be turned on and off almost instantly, bypassing the slow start-up and shutdown sequence.
In addition, Ramtron International has developed, produced, and licensed ferroelectric RAM (FRAM), a technology that offers distinct properties from other nonvolatile memory options,
including extremely high endurance (exceeding 1016 for 3.3 V devices), ultra low power
consumption (since F-RAM does not require a charge pump like other non-volatile memories),
single-cycle write speeds, and gamma radiation tolerance. Other companies that have licensed
and produced F-RAM technology include Texas Instruments, Rohm, and Fujitsu.

Non-volatile data storage can be categorized in electrically addressed systems (read-only
memory) and mechanically addressed systems (hard disks, optical disc, magnetic tape,
holographic memory, and such). Electrically addressed systems are expensive, but fast, whereas
mechanically addressed systems have a low price per bit, but are slow. Non-volatile memory
may one day eliminate the need for comparatively slow forms of secondary storage systems,
which include hard disks.

Fig. 1.1 : The emerging memory technologies

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1.4. Modeling:
To assist in the architecture-level and system-level design space exploration of SRAM- or
DRAM-based cache and memory, various modeling tools have been developed during the past
decade. For example, CACTI (cache access and cycle time) and DRAM sim (DRAM memory
simulator) have become widely used in the computer architecture community to estimate the
speed, power, and area parameters of SRAM and DRAM caches and main memory. Similarly,
new models have been developed so that computer architects can explore new design
opportunities at the architecture and system levels. An STT-RAM-based cache model,2,3 and a
PCRAM based cache-memory model,4 have been recently developed at the architecture level.
Such models extract all important parameters, including access latency, dynamic access power,
leakage power, die area, and I/O bandwidth, to facilitate architecture level analysis. The models
also bridge the gap between the abundant research activities at the process and device levels and
the lack of a high-level cache and memory model for emerging NVMs.

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1.5. MEMORIES PRINCIPLES:

Fig. 1.2 : Memories principles

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CHAPTER 2
FERROELECTRIC RAM (FRAM or FeRAM)
2.1. INTRODUCTION:
FRAM, an acronym for ferro-electric random access memory, combines the fast read and
write access of dynamic RAM (DRAM) with being non-volatile (the ability to retain data when
power is turned off) and ultra-low power consumption (compared to EEPROM and Flash). In
spite of the name, FRAM is not affected by magnetic fields because there is no ferrous material
(iron) in the chip. FRAM is being used today in several applications including electronic
metering, automotive (e.g. smart air bags), printers, instrumentation, medical equipment,
industrial microcontrollers and radio frequency identification. A FRAM memory cell consists of
a capacitor connected to a plate and bit line. The orientation of the dipole within the capacitor
determines whether a “1” or “0” is stored. The dipole orientation can be set and reversed by
applying voltage across either line.

2.2. Key Advantages:
• Speed—FRAM has fast access times – similar to DRAM. The actual write time is less than

50ns/word.This is ~1000× faster than EEPROM or Flash memory making universal memory
reality.

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• Low Power—Accesses to the FRAM occur at lower voltages (1.5 V) requiring very little

power. EEPROM writes accesses need 10 to 14 V requiring much more power. Lower power
memory enables more functionality at faster transactions speeds.
• Data Reliability—All the necessary power for FRAM is front-loaded at the beginning of data
access eliminating “data tearing.” FRAM experiences 100 trillion read/write cycles or greater

2.3. FRAM Reliability:
Texas Instruments’ (TI) FRAM new generation of non-volatile memory is designed,
manufactured and tested to meet the stringent requirements of today and tomorrow. The
following tests, per JEDEC industry standard test specifications for non-volatile memory,
guarantee 10 years of operation and data retention at 85°C. These test results are a small portion
of the testing done continuously at TI.

2.4. FRAM Data Read / Rewrite:

A data read access from FRAM includes a rewrite of the data back to the same memory
location. This is done within the memory block automatically. This read/ restore operation is
similar to DRAM, commonly used in personal electronics. Since FRAM has an inexhaustible
write endurance (>100 trillion write/read cycles), this is not a practical concern.

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2.5. FRAM Security:
Studies by a leading security lab have concluded that FRAM’s functional features could
change the smart card security landscape compared to existing EEPROM technologies. FRAM is
more resistant to data corruption via electric fields, radiation, etc. Also, the extremely fast write
times and the small 130 nanometer (nm) process node make it more resistant to physical attacks.
Furthermore, FRAM’s much lower power consumption arguably makes it more difficult to
attack with differential power analysis techniques.

2.6. FRAM Manufacturing:

While the benefits of FRAM have been known for many years, productization at
acceptable manufacturing yields has posed challenges to many companies. TI has been
successfully producing FRAM memory at an advanced process node (130 nm) for over two
years. TI’s FRAM technology is the result of over 10 years of manufacturing development with
well over 200 issued patents.

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CHAPTER 3
MAGNETO RESISTIVE RAM (MRAM)
3.1. INTRODUCTION:
MRAM uses electron spin to store data and is also called as Universal memory - offering
the density of DRAM with the speed of SRAM and non-volatility of FLASH memory/ disk
drives. MRAM consumes less power, resists high radiation and operate in extreme temperatures
making it suitable for mil and aerospace applications..There are several 'newer' types of MRAMs
- STT-RAM, NV-RAM, etc….

Fig. 3.1 : MRAM cell

Magneto resistive random-access memory (MRAM) is a non-volatile random-access
memory technology under development since the 1990s. Continued increases in density of
existing memory technologies – notably flash RAM and DRAM – kept it in a niche role in the
market, but its proponents believe that the advantages are so overwhelming that magneto
resistive RAM will eventually become dominant for all types of memory, becoming a universal
memory.

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3.2. Description:
Unlike conventional RAM chip technologies, data in MRAM is not stored as electric
charge or current flows, but by magnetic storage elements. The elements are formed from
two ferromagnetic plates, each of which can hold a magnetic field, separated by a thin insulating
layer. One of the two plates is a permanent magnet set to a particular polarity; the other plate's
field can be changed to match that of an external field to store memory. This configuration is
known as a spin valve and is the simplest structure for an MRAM bit. A memory device is built
from a grid form such “cells”.

The simplest method of reading is accomplished by measuring the electrical resistance of
the cell. A particular cell is (typically) selected by powering an associated transistor that
switches current from a supply line through the cell to ground. Due to the magnetic tunnel effect,
the electrical resistance of the cell changes due to the orientation of the fields in the two plates.
By measuring the resulting current, the resistance inside any particular cell can be determined,
and from this the polarity of the writable plate. Typically if the two plates have the same polarity
this is considered to mean "1", while if the two plates are of opposite polarity the resistance will
be higher and this means "0".

Data is written to the cells using a variety of means. In the simplest, each cell lies
between a pair of write lines arranged at right angles to each other, above and below the cell.
When current is passed through them, an induced magnetic field is created at the junction, which
the writable plate picks up. This pattern of operation is similar to core memory, a system
commonly used in the 1960s. This approach requires a fairly substantial current to generate the
field, however, which makes it less interesting for low-power uses, one of MRAM's primary
disadvantages. Additionally, as the device is scaled down in size, there comes a time when the
induced field overlaps adjacent cells over a small area, leading to potential false writes. This
problem, the half-select (or write disturb) problem, appears to set a fairly large size for this type
of cell. One experimental solution to this problem was to use circular domains written and read
using the giant magneto resistive effect, but it appears this line of research is no longer active.

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A newer technique, spin transfer torque (STT) or spin transfer switching, uses spinaligned ("polarized") electrons to directly torque the domains. Specifically, if the electrons
flowing into a layer have to change their spin, this will develop a torque that will be transferred
to the nearby layer. This lowers the amount of current needed to write the cells, making it about
the same as the read process. There are concerns that the "classic" type of MRAM cell will have
difficulty at high densities due to the amount of current needed during writes, a problem that
STT avoids. For this reason, the STT proponents expect the technique to be used for devices of
65 nm and smaller. The downside is the need to maintain the spin coherence. Overall, the STT
requires much less write current than conventional or toggle MRAM. Research in this field
indicates that STT current can be reduced up to 50 times by using a new composite
structure. However, higher speed operation still requires higher current.

Other potential arrangements include "Thermal Assisted Switching" (TASMRAM), which briefly heats up (reminiscent of phase-change memory) the magnetic tunnel
junctions during the write process and keeps the MTJs stable at a colder temperature the rest of
the time; and "vertical transport MRAM" (VMRAM), which uses current through a vertical
column to change magnetic orientation, a geometric arrangement that reduces the write disturb
problem and so can be used at higher density.

A review paper provides the details of materials and challenges associated with MRAM
in the perpendicular geometry. The authors describe a new term called "Pentalemma" - which
represents a conflict in five different requirements such as write current, stability of the bits,
readability, read/write speed and the process integration with CMOS. The selection of materials
and the design of MRAM to fulfill those requirements are discussed.

3.3.Comparison with other systems:

3.3.1. Density:
The main determinant of a memory system's cost is the density of the components used to
make it up. Smaller components, and fewer of them, mean that more "cells" can be packed onto a

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single chip, which in turn means more can be produced at once from a single silicon wafer. This
improves yield, which is directly related to cost.
DRAM uses a small capacitor as a memory element, wires to carry current to and from it,
and a transistor to control it – referred to as a "1T1C" cell. This makes DRAM the highestdensity RAM currently available, and thus the least expensive, which is why it is used for the
majority of RAM found in a computer.
MRAM is physically similar to DRAM in makeup, although often does not require a
transistor for the write operation. However, as mentioned above, the most basic MRAM cell
suffers from the half-select problem, which limits cell sizes to around 180 nm or more.

3.3.2. Power consumption:
Since the capacitors used in DRAM lose their charge over time, memory assemblies that
use DRAM must refresh all the cells in their chips approximately 20 times a second, reading
each one and re-writing its contents. As DRAM cells decrease in size it is necessary to refresh
the cells more often, resulting in greater power consumption.

In contrast, MRAM never requires a refresh. This means that not only does it retain its
memory with the power turned off but also there is no constant power-draw. While the read
process in theory requires more power than the same process in a DRAM, in practice the
difference appears to be very close to zero. However, the write process requires more power to
overcome the existing field stored in the junction, varying from three to eight times the power
required during reading. Although the exact amount of power savings depends on the nature of
the work – more frequent writing will require more power – in general MRAM proponents
expect much lower power consumption (up to 99% less) compared to DRAM. STT-based
MRAMs eliminate the difference between reading and writing, further reducing power
requirements.

It is also worth comparing MRAM with another common memory system, flash RAM.
Like MRAM, flash does not lose its memory when power is removed, which makes it very
common as a "hard disk replacement" in small devices such as digital audio players ordigital

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cameras. When used for reading, flash and MRAM are very similar in power requirements.
However, flash is re-written using a large pulse of voltage (about 10 V) that is stored up over
time in a charge pump, which is both power-hungry and time-consuming. In addition, the current
pulse physically degrades the flash cells, which means flash can only be written to some finite
number of times before it must be replaced.

In contrast, MRAM requires only slightly more power to write than read, and no change
in the voltage, eliminating the need for a charge pump. This leads to much faster operation,
lower power consumption, and an indefinitely long "lifetime".

3.3.3. Performance:
DRAM performance is limited by the rate at which the charge stored in the cells can be
drained (for reading) or stored (for writing). MRAM operation is based on measuring voltages
rather than charges or currents, so there is less "settling time" needed. IBM researchers have
demonstrated MRAM devices with access times on the order of 2 ns, somewhat better than even
the most advanced DRAMs built on much newer processes .A team at the German PhysikalischTechnische Bundesanstalt have demonstrated MRAM devices with 1 ns settling times, better
than the currently accepted theoretical limits for DRAM, although the demonstration was a
single cell. The differences compared to flash are far more significant, with write times as much
as thousands of times faster.

The only current memory technology that easily competes with MRAM in terms of
performance is static RAM, or SRAM. SRAM consists of a series of transistors arranged in
a flip-flop, which will hold one of two states as long as power is applied. Since the transistors
have a very low power requirement, their switching time is very low. However, since an SRAM
cell consists of several transistors, typically four or six, its density is much lower than DRAM.
This makes it expensive, which is why it is used only for small amounts of high-performance
memory, notably the CPU cache in almost all modern CPU designs.

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Although MRAM is not quite as fast as SRAM, it is close enough to be interesting even
in this role. Given its much higher density, a CPU designer may be inclined to use MRAM to
offer a much larger but somewhat slower cache, rather than a smaller but faster one. It remains to
be seen how this trade-off will play out in the future.

MRAM has similar performance to SRAM, similar density to DRAM but much lower
power consumption than DRAM, and is much faster and suffers no degradation over time in
comparison to flash memory. It is this combination of features that some suggest makes it the
“universal memory”, able to replace SRAM, DRAM, EEPROM, and flash. This also explains the
huge amount of research being carried out into developing it.

However, to date, MRAM has not been as widely adopted in the market as other nonvolatile RAMs. It may be that vendors are not prepared to take the risk of allocating a
modern fab to MRAM production when such fabs cost upwards of a few billion dollars to build
and can instead generate revenue by serving developed markets producing flash and DRAM
memories.

The very latest fabs seem to be used for flash, for example producing 16 Gbit parts
produced by Samsung on a 50 nm process. Slightly older fabs are being used to produce most
DDR2 DRAM, most of which is produced on a one-generation-old 90 nm process rather than
using up scarce leading-edge capacity.

In comparison, MRAM is still largely "in development", and being produced on older
non-critical fabs. The only commercial product widely available at this point is Everspin's 4 Mbit
part, produced on a several-generations-old 180 nm process. As demand for flash continues to
outstrip supply, it appears that it will be some time before a company can afford to "give up" one
of their latest fabs for MRAM production. Even then, MRAM designs currently do not come
close to flash in terms of cell size, even using the same fab.

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3.4. Alternatives to MRAM:
Flash and EEPROM's limited write-cycles are a serious problem for any real RAM-like
role, however. In addition, the high power needed to write the cells is a problem in low-power
roles, where non-volatile RAM is often used. The power also needs time to be "built up" in a
device known as a charge pump, which makes writing dramatically slower than reading, often as
much as 1,000 times. While MRAM was certainly designed to address some of these issues, a
number of other new memory devices are in production or have been proposed to address these
shortcomings.

To date, the only such system to enter widespread production is ferroelectric RAM, or FRAM (sometimes referred to as FeRAM). F-RAM is a random-access memory similar in
construction to DRAM but (instead of a dielectric layer like in DRAM) contains a thin
ferroelectric film of lead zirconate titanate [Pb(Zr,Ti)O 3], commonly referred to as PZT. The
Zr/Ti atoms in the PZT change polarity in an electric field, thereby producing a binary switch.
Unlike RAM devices, F-RAM retains its data memory when power is shut off or interrupted, due
to the PZT crystal maintaining polarity. Due to this crystal structure and how it is influenced, FRAM offers distinct properties from other nonvolatile memory options, including extremely high
endurance (exceeding 1016 for 3.3 V devices), ultra low power consumption (since F-RAM does
not require a charge pump like other non-volatile memories), single-cycle write speeds, and
gamma

radiation

tolerance. Ramtron

International has

developed,

produced,

and

licensed ferroelectric RAM (F-RAM).

Another solid-state technology to see more than purely experimental development
is Phase-change RAM , or PRAM. PRAM is based on the same storage mechanism as
writable CDs and DVDs, but reads them based on their changes in electrical resistance rather
than changes in their optical properties. Considered a "dark horse" for some time, in
2006 Samsung announced the availability of a 512 Mb part, considerably higher capacity than
either MRAM or FeRAM. The areal density of these parts appears to be even higher than
modern flash devices, the lower overall storage being due to the lack of multi-bit encoding. This
announcement was followed by one from Intel and STMicroelectronics, who demonstrated their

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own PRAM devices at the 2006 Intel Developer Forum in October. One of the most attended
sessions in the IEDM December 2006 was the presentation by IBM of their PRAM technology.

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CHAPTER 4
PHASE-CHANGE MEMORY
4.1. INTRODUCTION:

Phase-change memory (also known as PCM, PCME, PRAM, PCRAM, Ovonic Unified
Memory, Chalcogenide RAM and C-RAM) is a type of non-volatile random-access memory.
PRAMs exploit the unique behavior of chalcogenide glass. In the older generation of PCM heat
produced by the passage of an electric current through a heating element generally made of TiN
would be used to either quickly heat and quench the glass, making it amorphous, or to hold it in
its crystallization temperature range for some time, thereby switching it to a crystalline state.
PCM also has the ability to achieve a number of distinct intermediary states, thereby having the
ability to hold multiple bits in a single cell, but the difficulties in programming cells in this way
has prevented these capabilities from being implemented in other technologies (most
notably flash memory) with the same capability. Newer PCM technology has been trending in a
couple different directions. Some groups have been directing a lot of research towards attempting
to find viable material alternatives to Ge2Sb2Te5 (GST), with mixed success, while others have
developed the idea of using a GeTe - Sb2Te3 superlattice in order to achieve non thermal phase
changes by simply changing the coordination state of the Germanium atoms with a laser pulse,
and this new Interfacial phase change memory (IPCM) has had many successes and continues to
be the site of much active research.

Leon Chua has argued that all 2-terminal non-volatile memory devices including phase
change memory should be considered memristors. Stan Williams of HP Labs has also argued
that phase change memory should be considered to be a memristor.

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4.2. PRAM vs. Flash
It is the switching time and inherent scalability that makes PRAM most appealing.
PRAM's temperature sensitivity is perhaps its most notable drawback, one that may require
changes in the production process of manufacturers incorporating the technology.

Fig. 4.1 : A cross-section of two PRAM memory cells. One cell is in low resistance crystalline state, the other
in high resistance amorphous state.

Flash memory works by modulating charge (electrons) stored within the gate of a MOS
transistor. The gate is constructed with a special "stack" designed to trap charges (either on a
floating gate or in insulator "traps"). The presence of charge within the gate shifts the
transistor's threshold voltage,

higher or lower, corresponding to a 1 to 0, for instance.

Changing the bit's state requires removing the accumulated charge, which demands a relatively
large voltage to "suck" the electrons off the floating gate. This burst of voltage is provided by
a charge pump, which takes some time to build up power. General write times for common Flash
devices are on the order of 0.1ms (for a block of data), about 10,000 times the typical 10 ns read
time, for SRAM for example (for a byte).

PRAM can offer much higher performance in applications where writing quickly is
important, both because the memory element can be switched more quickly, and also because
single bits may be changed to either 1 or 0 without needing to first erase an entire block of cells.

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PRAM's high performance, thousands of times faster than conventional hard drives, makes it
particularly interesting in nonvolatile memory roles that are currently performance-limited by
memory access timing.

In addition, with Flash, each burst of voltage across the cell causes degradation. As the
size of the cells decreases, damage from programming grows worse because the voltage
necessary to program the device does not scale with the lithography. Most flash devices are rated
for, currently, only 5,000 writes per sector, and many flash controllers perform wear leveling to
spread writes across many physical sectors.

PRAM devices also degrade with use, for different reasons than Flash, but degrade much
more slowly. A PRAM device may endure around 100 million write cycles. [12] PRAM lifetime is
limited by mechanisms such as degradation due to GST thermal expansion during programming,
metal (and other material) migration, and other mechanisms still unknown.

Flash parts can be programmed before being soldered on to a board, or even purchased
pre-programmed. The contents of a PRAM, however, are lost because of the high temperatures
needed to solder the device to a board (see reflow soldering or wave soldering). This is made
worse by the recent drive to lead-free manufacturing requiring higher soldering temperatures.
The manufacturer using PRAM parts must provide a mechanism to program the PRAM "insystem" after it has been soldered in place.

The special gates used in Flash memory "leak" charge (electrons) over time, causing
corruption and loss of data. The resistivity of the memory element in PRAM is more stable; at
the normal working temperature of 85°C, it is projected to retain data for 300 years. [13]
By carefully modulating the amount of charge stored on the gate, Flash devices can store
multiple (usually two) bits in each physical cell. In effect, this doubles the memory density,
reducing cost. PRAM devices originally stored only a single bit in each cell, but Intel's recent
advances have removed this problem.

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Because Flash devices trap electrons to store information, they are susceptible to data
corruption from radiation, making them unsuitable for many space and military applications.
PRAM exhibits higher resistance to radiation.

PRAM cell selectors can use various devices: diodes, BJTs and MOSFETs. Using a diode
or a BJT provides the greatest amount of current for a given cell size. However, the concern with
using a diode stems from parasitic currents to neighboring cells, as well as a higher voltage
requirement, resulting in higher power consumption. The chalcogenide resistance being a
necessarily larger resistance than the diode entails that the operating voltage must exceed 1 V by
a wide margin to guarantee adequate forward bias current from the diode. Perhaps the most
severe consequence of using a diode-selected array, in particular for large arrays, is the total
reverse bias leakage current from the unselected bit lines. In transistor-selected arrays, only the
selected bit lines contribute reverse bias leakage current. The difference in leakage current is
several orders of magnitude. A further concern with scaling below 40 nm is the effect of discrete
dopants as the p-n junction width scales down.

4.3. Challenges:
The greatest challenge for phase-change memory has been the requirement of high
programming current density (>107 A/cm², compared to 105-106 A/cm² for a typical transistor or
diode) in the active volume highly unlikely. This has led to active areas that are much smaller
than the driving transistor area. The discrepancy has forced phase-change memory structures to
package the heater and sometimes the phase-change material itself in sub-lithographic
dimensions. This is a process cost disadvantage compared to Flash.

The contact between the hot phase-change region and the adjacent dielectric is another
fundamental concern. The dielectric may begin to leak current at higher temperature, or may lose
adhesion when expanding at a different rate from the phase-change material.

Phase-change memory is susceptible to a fundamental tradeoff of unintended vs. intended
phase-change. This stems primarily from the fact that phase-change is a thermally driven process
rather than an electronic process. Thermal conditions that allow for fast crystallization should not

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be too similar to standby conditions, e.g. room temperature. Otherwise data retention cannot be
sustained. With the proper activation energy for crystallization it is possible to have fast
crystallization at programming conditions while having very slow crystallization at normal
conditions.

Probably the biggest challenge for phase change memory is its long-term resistance and
threshold voltage drift. The resistance of the amorphous state slowly increases according to a
power law (~t0.1). This severely limits the ability for multilevel operation (a lower intermediate
state would be confused with a higher intermediate state at a later time) and could also jeopardize
standard two-state operation if the threshold voltage increases beyond the design value.

In April 2010, Numonyx released its Omneo line of parallel and serial interface 128 Mb
NOR-Flash replacement PRAM chips. Although the NOR flash chips they intended to replace
operated in the -40-85 °C range, the PRAM chips operated in the 0-70°C range, indicating a
smaller operating window compared to NOR flash. This is likely due to the use of highly
temperature sensitive p-n junctions to provide the high currents needed for programming.

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EMERGING MEMORIES

CHAPTER 5
RESISTIVE RANDOM-ACCESS MEMORY (RRAM)
5.1. INTRODUCTION

Resistive random-access memory (RRAM or ReRAM) is a non-volatile memory type
under development by a number of different companies, some of which have patented versions
of ReRAM.The technology bears some similarities to CBRAM and phase change memory.
In February 2012 Rambus bought a ReRAM company called Unity Semiconductor for $35
million. Panasonic launched a ReRAM evaluation kit in May 2012, based on a tantalum oxide
1T1R (1 transistor - 1 resistor) memory cell architecture.

Different forms of ReRAM have been disclosed, based on different dielectric materials,
spanning from perovskites to transition metal oxides to chalcogenides. Even silicon dioxide has
been shown to exhibit resistive switching as early as 1967,and has recently been revisited.
Leon Chua, who is considered to be the father of non-linear circuit theory, has argued that all 2terminal non-volatile memory devices including ReRAM should be considered memristors. Stan
Williams of HP Labs has also argued that all ReRAM should be considered to be
a memristor. These claims, however, seem not to be justified given that the memristor theory in
itself is open to question. There is an ongoing discussion whether or not redox-based resistively
switching elements (ReRAM) are covered by the current memristor theory.

5.2. Mechanism
The basic idea is that a dielectric, which is normally insulating, can be made to conduct
through a filament or conduction path formed after application of a sufficiently high voltage. The
conduction path formation can arise from different mechanisms, including defects, metal
migration, etc. Once the filament is formed, it may be reset (broken, resulting in high resistance)
or set (re-formed, resulting in lower resistance) by an appropriately applied voltage. Recent data
suggest that many current paths, rather than a single filament, are probably involved.

23

EMERGING MEMORIES

A memory cell can be produced from the basic switching element in three different ways.
In the simplest approach, the single memory element can be used as a basic memory cell, and
inserted into a configuration in which parallel bit lines are crossed by perpendicular word lines
with the switching material placed between word line and bit line at every cross-point. This
configuration is called a cross-point cell. Since this architecture can lead to a large "sneak"
parasitic current flowing through non selected memory cells via neighboring cells, the crosspoint array may have a very slow read access. A selection element can be added to improve the
situation, but this selection element consumes extra voltage and power. A series connection of a
diode in every cross-point allows to reverse bias, zero bias, or at least partial bias non selected
cells, leading to negligible sneak currents. This can be arranged in a similar compact manner as
the basic cross-point cell. Finally a transistor device (ideally a MOS Transistor) can be added
which makes the selection of a cell very easy and therefore gives the best random access time,
but comes at the price of increased area consumption.

For random access type memories, a transistor type architecture is preferred while the
cross-point architecture and the diode architecture open the path toward stacking memory layers
on top of each other and therefore are ideally suited for mass storage devices. The switching
mechanism itself can be classified in different dimensions. First there are effects where the
polarity between switching from the low to the high resistance level (reset operation) is reversed
compared to the switching between the high and the low resistance level (set operation). These
effects are called bipolar switching effects. On the contrary, there are also uni-polar switching
effects where both set and reset operations require the same polarity, but different voltage
magnitude.

Another way to distinguish switching effects is based on the localization of the low
resistive path. Many resistive switching effects show a filamentary behavior, where only one or a
few very narrow low resistive paths exist in the low resistive state. In contrast, also homogenous
switching of the whole area can be observed. Both effects can occur either throughout the entire
distance between the electrodes or happen only in proximity to one of the electrodes.
Filamentary and homogenous switching effects can be distinguished by measuring the area
dependence of the low resistance state.

24

EMERGING MEMORIES

5.3. Future applications:
ReRAM has the potential to become the front runner among other non-volatile memories.
Compared to PRAM, ReRAM operates at a faster timescale (switching time can be less than
10 ns), while compared to MRAM, it has a simpler, smaller cell structure (less than 8F² MIM
stack). There is a type of vertical 1D1R (one diode, one resistive switching device) integration
used for crossbar memory structure to reduce the unit cell size to 4F² (F is the feature
dimension). Compared to flash memory and racetrack memory, a lower voltage is sufficient and
hence it can be used in low power applications.

ITRI has recently shown that ReRAM is scalable below 30 nm. The motion of oxygen
atoms is a key phenomenon for oxide-based ReRAM; one study has indicated that oxygen
motion may take place in regions as small as 2 nm. It is believed that if a filament is responsible,
it would not exhibit direct scaling with cell size. Instead, the current compliance limit (set by an
outside resistor, for example) could define the current-carrying capacity of the filament.

A significant hurdle to realizing the potential of ReRAM is the sneak path problem which
occurs in larger passive arrays. In 2010, complementary resistive switching (CRS) was
introduced as a possible solution to the interference from sneak-path currents. In the CRS
approach, the information storing states are pairs of high and low resistance states (HRS/LRS
and LRS/HRS) so that the overall resistance is always high, allowing for larger passive crossbar
arrays.
A drawback to the initial CRS solution is the high requirement for switching endurance
caused by conventional destructive readout based on current measurements. A new approach for
a nondestructive readout based on capacity measurement potentially lowers the requirements for
both material endurance and power consumption. Bi-layer structure is used to produce the
nonlinearity in LRS to avoid the sneak path problem. Single layer device exhibiting a strong
nonlinear conduction in LRS has been recently reported. Another bi-layer structure is introduced
for bipolar ReRAM to improve the HRS and stability of the memory endurance performance.

25

EMERGING MEMORIES

CHAPTER 6
ADVANTAGES AND CONCLUSION
The emerging NVM business will be very dynamic over the next five years, thanks to
improvements in scalability/cost and density of emerging NVM chips:

1. PCM devices, the densest NVM in 2012 at 1GB, will reach 8GB by 2018 -> could replace
NOR Flash Memory in mobile phones and will also be used as Storage Class Memory in
Enterprise Storage.
2. MRAM/STTMRAM chips will reach 8 - 16 GB in 2018 -> It will be widely sold as a Storage
Class Memory, and possibly as a DRAM successor in Enterprise Storage after 2018.
3. RRAM will reach between 32GB – 2TB in 2018 thanks to 3D capability -> gradually be
adopted in the Mass Storage market dominated by NAND technology, in addition to limited
market adoption in lower-density applications like Industrial and Enterprise Storage.
4. FRAM will be more stable in terms of scalability, with 8 – 16MB chips available by 2018 ->
development of new FRAM material could raise scalability, but we don’t expect it to be widely
industrialized and commercialized before 2018.

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EMERGING MEMORIES

References:
1.Modeling, Architecture, and Applications for Emerging Memory Technologies, Yuan Xie
Pennsylvania State University
2. X. Wu et al., ‘‘Hybrid Cache Architecture with Disparate Memory Technologies,’’ Proc. 36th
Int’l Symp. Computer Architecture (ISCA 09), ACM Press, 2009, pp. 34-45.
3. X. Dong et al., ‘‘Circuit and Micro architecture Evaluation of 3D Stacking Magnetic RAM
(MRAM) as a Universal Memory Replacement,’’ Proc. 45th Design Automation Conf. (DAC
08), ACM Press, 2008, pp. 554-559.
4. G. Sun et al., ‘‘A Novel Architecture of the 3D Stacked MRAM L2 Cache for CMPs,’’ Proc.
15th Int’l Symp. High Performance Computer Architecture (HPCA-15), IEEE CS Press, 2009,
pp. 239-249.
5. X. Dong, N. Jouppi, and Y. Xie, ‘‘PCRA Msim: System- Level Performance, Energy, and
Area Modeling for Phase Change RAM,’’ Proc. Int’l Conf. Computer-Aided Design (ICCAD
09), ACM Press, 2009, pp. 269-275.
6. B.C. Lee et al., ‘‘Architecting Phase Change Memory as a Scalable DRAM Alternative,’’
Proc. 36th Int’l Symp. Computer Architecture (ISCA 09), ACM Press, pp. 2-13.

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