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Digital System Design
Multiplexers and Demultiplexers,
and
Encoders and Decoders
2
Multiplexers
3
Multiplexers
 A multiplexer has
 N control inputs
 2N
data inputs
 1 output
 A multiplexer routes (or connects) the selected
data input to the output.
 The value of the control inputs determines
the data input that is selected.
4
Multiplexers
Z = A′.I0 + A.I1
Data
inputs
Control
input
5
Multiplexers
Z = A′.B'.I0 + A'.B.I1 + A.B'.I2 + A.B.I3
A B F
0 0 I0
0 1 I1
1 0 I2
1 1 I3
MSB LSB
6
Multiplexers
Z = A′.B'.C'.I0 + A'.B'.C.I1 + A'.B.C'.I2 + A'.B.C.I3 +
A.B'.C'.I0 + A.B'.C.I1 + A'.B.C'.I2 + A.B.C.I3
MSB LSB
A B C F
0 0 0 I0
0 0 1 I1
0 1 0 I2
0 1 1 I3
1 0 0 I4
1 0 1 I5
1 1 0 I6
1 1 1 I7
Fall 2010 ECE 331 - Digital System Design 7
Multiplexers
8
Multiplexers
Exercise:
Design an 8-to-1 multiplexer using
4-to-1 and 2-to-1 multiplexers only.
9
Multiplexers
Exercise:
Design a 16-to-1 multiplexer using
4-to-1 multiplexers only.
Fall 2010 ECE 331 - Digital System Design 10
Multiplexer (Bus)
11
Demultiplexers
12
Demultiplexers
 A demultiplexer has
 N control inputs
 1 data input
 2N
outputs
 A demultiplexer routes (or connects) the data input to
the selected output.
 The value of the control inputs determines the output
that is selected.
 A demultiplexer performs the opposite function of a
multiplexer.
13
Demultiplexers
A B W X Y Z
0 0 I 0 0 0
0 1 0 I 0 0
1 0 0 0 I 0
1 1 0 0 0 I
W = A'.B'.I
X = A.B'.I
Y = A'.B.I
Z = A.B.I
Out0
In
S1 S0
I
W
X
Y
Z
A B
Out1
Out2
Out3
14
Decoders
15
Decoders
 A decoder has
 N inputs
 2N
outputs
 A decoder selects one of 2N
outputs by
decoding the binary value on the N inputs.
 The decoder generates all of the minterms of
the N input variables.
 Exactly one output will be active for each
combination of the inputs.
What does “active” mean?
16
Decoders
A B W X Y Z
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1
Active-high outputs
B
W
X
Y
Z
I0
I1A
Out0
Out1
Out2
Out3
W = A'.B'
X = A.B'
Y = A'.B
Z = A.Bmsb
Fall 2010 ECE 331 - Digital System Design 17
Decoders
A B W X Y Z
0 0 0 1 1 1
0 1 1 0 1 1
1 0 1 1 0 1
1 1 1 1 1 0
Active-low outputs
W = (A'.B')'
X = (A.B')'
Y = (A'.B)'
Z = (A.B)'msb
B
W
X
Y
Z
I0
I1A
Out0
Out1
Out2
Out3
18
Decoders
msb
19
Decoder with Enable
En A B W X Y Z
1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1
0 x x 0 0 0 0
enabled
disabled
high-level
enable
Enable
B W
X
Y
Z
I0
I1A
Out0
Out1
Out2
Out3
En
20
Decoder with Enable
En A B W X Y Z
0 0 0 1 0 0 0
0 0 1 0 1 0 0
0 1 0 0 0 1 0
0 1 1 0 0 0 1
1 x x 0 0 0 0
enabled
disabled
Enable
B W
X
Y
Z
I0
I1A
Out0
Out1
Out2
Out3
En
low-level
enable
21
Decoders
Exercise:
Design a 4-to-16 decoder using
2-to-4 decoders only.
22
Encoders
23
Encoders
 An encoder has
 2N
inputs
 N outputs
 An encoder outputs the binary value of the selected
(or active) input.
 An encoder performs the inverse operation of a
decoder.
 Issues
 What if more than one input is active?
 What if no inputs are active?
24
Encoders
A B C D Y Z
0 0 0 1 0 0
0 0 1 0 0 1
0 1 0 0 1 0
1 0 0 0 1 1
D
Z
Y
I0
I1C
B I2
I3A
Out0
Out1
25
Priority Encoders
 If more than one input is active, the higher-order
input has priority over the lower-order input.
 The higher value is encoded on the output
 A valid indicator, d, is included to indicate whether or
not the output is valid.
 Output is invalid when no inputs are active
 d = 0
 Output is valid when at least one input is active
 d = 1
Why is the valid indicator needed?
26
Priority Encoders
Valid bit
msb
27
Designing logic circuits using multiplexers
28
Using an n-input Multiplexer
 Use an n-input multiplexer to realize a logic circuit for
a function with n minterms.
 m = 2n, where m = # of variables in the function
 Each minterm of the function can be mapped to an
input of the multiplexer.
 For each row in the truth table, for the function,
where the output is 1, set the corresponding input of
the multiplexer to 1.
 That is, for each minterm in the minterm expansion of the
function, set the corresponding input of the multiplexer to 1.
 Set the remaining inputs of the multiplexer to 0.
29
Using an n-input Mux
Example:
Using an 8-to-1 multiplexer, design a logic circuit
to realize the following Boolean function
F(A,B,C) = Sm(2, 3, 5, 6, 7)
30
Using an n-input Mux
Example:
Using an 8-to-1 multiplexer, design a logic circuit
to realize the following Boolean function
F(A,B,C) = Sm(1, 2, 4)
31
Using an (n / 2)-input Multiplexer
 Use an (n / 2)-input multiplexer to realize a logic
circuit for a function with n minterms.
 m = 2n, where m = # of variables in the function
 Group the rows of the truth table, for the function, into
(n / 2) pairs of rows.
 Each pair of rows represents a product term of (m – 1)
variables.
 Each pair of rows can be mapped to a multiplexer input.
 Determine the logical function of each pair of rows in
terms of the mth variable.
 If the mth variable, for example, is x, then the possible
values are x, x', 0, and 1.
32
Using an (n / 2)-input Mux
Example: F(x,y,z) = Sm(1, 2, 6, 7)
33
Using an (n / 2)-input Mux
Example: F(A,B,C,D) = Sm(1,3,4,11,12–15)
34
Using an (n / 4)-input Mux
The design of a logic circuit using an (n / 2)-input
multiplexer can be easily extended to the use of
an (n / 4)-input multiplexer.
35
Designing logic circuits using decoders
36
Using an n-output Decoder
 Use an n-output decoder to realize a logic circuit for a
function with n minterms.
 Each minterm of the function can be mapped to an
output of the decoder.
 For each row in the truth table, for the function, where
the output is 1, sum (or “OR”) the corresponding
outputs of the decoder.
 That is, for each minterm in the minterm expansion of the
function, OR the corresponding outputs of the decoder.
 Leave remaining outputs of the decoder unconnected.
37
Using an n-output Decoder
Example:
Using a 3-to-8 decoder, design a logic circuit to
realize the following Boolean function
F(A,B,C) = Sm(2, 3, 5, 6, 7)
38
Using an n-output Decoder
Example:
Using two 2-to-4 decoders, design a logic circuit
to realize the following Boolean function
F(A,B,C) = Sm(0, 1, 4, 6, 7)
39
Questions?

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Encoder, decoder, multiplexers and demultiplexers

  • 1. Digital System Design Multiplexers and Demultiplexers, and Encoders and Decoders
  • 3. 3 Multiplexers  A multiplexer has  N control inputs  2N data inputs  1 output  A multiplexer routes (or connects) the selected data input to the output.  The value of the control inputs determines the data input that is selected.
  • 4. 4 Multiplexers Z = A′.I0 + A.I1 Data inputs Control input
  • 5. 5 Multiplexers Z = A′.B'.I0 + A'.B.I1 + A.B'.I2 + A.B.I3 A B F 0 0 I0 0 1 I1 1 0 I2 1 1 I3 MSB LSB
  • 6. 6 Multiplexers Z = A′.B'.C'.I0 + A'.B'.C.I1 + A'.B.C'.I2 + A'.B.C.I3 + A.B'.C'.I0 + A.B'.C.I1 + A'.B.C'.I2 + A.B.C.I3 MSB LSB A B C F 0 0 0 I0 0 0 1 I1 0 1 0 I2 0 1 1 I3 1 0 0 I4 1 0 1 I5 1 1 0 I6 1 1 1 I7
  • 7. Fall 2010 ECE 331 - Digital System Design 7 Multiplexers
  • 8. 8 Multiplexers Exercise: Design an 8-to-1 multiplexer using 4-to-1 and 2-to-1 multiplexers only.
  • 9. 9 Multiplexers Exercise: Design a 16-to-1 multiplexer using 4-to-1 multiplexers only.
  • 10. Fall 2010 ECE 331 - Digital System Design 10 Multiplexer (Bus)
  • 12. 12 Demultiplexers  A demultiplexer has  N control inputs  1 data input  2N outputs  A demultiplexer routes (or connects) the data input to the selected output.  The value of the control inputs determines the output that is selected.  A demultiplexer performs the opposite function of a multiplexer.
  • 13. 13 Demultiplexers A B W X Y Z 0 0 I 0 0 0 0 1 0 I 0 0 1 0 0 0 I 0 1 1 0 0 0 I W = A'.B'.I X = A.B'.I Y = A'.B.I Z = A.B.I Out0 In S1 S0 I W X Y Z A B Out1 Out2 Out3
  • 15. 15 Decoders  A decoder has  N inputs  2N outputs  A decoder selects one of 2N outputs by decoding the binary value on the N inputs.  The decoder generates all of the minterms of the N input variables.  Exactly one output will be active for each combination of the inputs. What does “active” mean?
  • 16. 16 Decoders A B W X Y Z 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 0 0 0 1 Active-high outputs B W X Y Z I0 I1A Out0 Out1 Out2 Out3 W = A'.B' X = A.B' Y = A'.B Z = A.Bmsb
  • 17. Fall 2010 ECE 331 - Digital System Design 17 Decoders A B W X Y Z 0 0 0 1 1 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 0 Active-low outputs W = (A'.B')' X = (A.B')' Y = (A'.B)' Z = (A.B)'msb B W X Y Z I0 I1A Out0 Out1 Out2 Out3
  • 19. 19 Decoder with Enable En A B W X Y Z 1 0 0 1 0 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 0 1 1 1 0 0 0 1 0 x x 0 0 0 0 enabled disabled high-level enable Enable B W X Y Z I0 I1A Out0 Out1 Out2 Out3 En
  • 20. 20 Decoder with Enable En A B W X Y Z 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 1 0 0 0 1 0 0 1 1 0 0 0 1 1 x x 0 0 0 0 enabled disabled Enable B W X Y Z I0 I1A Out0 Out1 Out2 Out3 En low-level enable
  • 21. 21 Decoders Exercise: Design a 4-to-16 decoder using 2-to-4 decoders only.
  • 23. 23 Encoders  An encoder has  2N inputs  N outputs  An encoder outputs the binary value of the selected (or active) input.  An encoder performs the inverse operation of a decoder.  Issues  What if more than one input is active?  What if no inputs are active?
  • 24. 24 Encoders A B C D Y Z 0 0 0 1 0 0 0 0 1 0 0 1 0 1 0 0 1 0 1 0 0 0 1 1 D Z Y I0 I1C B I2 I3A Out0 Out1
  • 25. 25 Priority Encoders  If more than one input is active, the higher-order input has priority over the lower-order input.  The higher value is encoded on the output  A valid indicator, d, is included to indicate whether or not the output is valid.  Output is invalid when no inputs are active  d = 0  Output is valid when at least one input is active  d = 1 Why is the valid indicator needed?
  • 27. 27 Designing logic circuits using multiplexers
  • 28. 28 Using an n-input Multiplexer  Use an n-input multiplexer to realize a logic circuit for a function with n minterms.  m = 2n, where m = # of variables in the function  Each minterm of the function can be mapped to an input of the multiplexer.  For each row in the truth table, for the function, where the output is 1, set the corresponding input of the multiplexer to 1.  That is, for each minterm in the minterm expansion of the function, set the corresponding input of the multiplexer to 1.  Set the remaining inputs of the multiplexer to 0.
  • 29. 29 Using an n-input Mux Example: Using an 8-to-1 multiplexer, design a logic circuit to realize the following Boolean function F(A,B,C) = Sm(2, 3, 5, 6, 7)
  • 30. 30 Using an n-input Mux Example: Using an 8-to-1 multiplexer, design a logic circuit to realize the following Boolean function F(A,B,C) = Sm(1, 2, 4)
  • 31. 31 Using an (n / 2)-input Multiplexer  Use an (n / 2)-input multiplexer to realize a logic circuit for a function with n minterms.  m = 2n, where m = # of variables in the function  Group the rows of the truth table, for the function, into (n / 2) pairs of rows.  Each pair of rows represents a product term of (m – 1) variables.  Each pair of rows can be mapped to a multiplexer input.  Determine the logical function of each pair of rows in terms of the mth variable.  If the mth variable, for example, is x, then the possible values are x, x', 0, and 1.
  • 32. 32 Using an (n / 2)-input Mux Example: F(x,y,z) = Sm(1, 2, 6, 7)
  • 33. 33 Using an (n / 2)-input Mux Example: F(A,B,C,D) = Sm(1,3,4,11,12–15)
  • 34. 34 Using an (n / 4)-input Mux The design of a logic circuit using an (n / 2)-input multiplexer can be easily extended to the use of an (n / 4)-input multiplexer.
  • 35. 35 Designing logic circuits using decoders
  • 36. 36 Using an n-output Decoder  Use an n-output decoder to realize a logic circuit for a function with n minterms.  Each minterm of the function can be mapped to an output of the decoder.  For each row in the truth table, for the function, where the output is 1, sum (or “OR”) the corresponding outputs of the decoder.  That is, for each minterm in the minterm expansion of the function, OR the corresponding outputs of the decoder.  Leave remaining outputs of the decoder unconnected.
  • 37. 37 Using an n-output Decoder Example: Using a 3-to-8 decoder, design a logic circuit to realize the following Boolean function F(A,B,C) = Sm(2, 3, 5, 6, 7)
  • 38. 38 Using an n-output Decoder Example: Using two 2-to-4 decoders, design a logic circuit to realize the following Boolean function F(A,B,C) = Sm(0, 1, 4, 6, 7)