Error Control Codes or Channel Codes - Cyclic Codes

Module IV – Cyclic Codes - Encoding &
Decoding
Lakshmi V.S.
Assistant Professor
Electronics & Communication Department
Sree Chitra Thirunal College of Engineering, Trivandrum

Cyclic Codes
• Cyclic codes form an important subclass of linear codes. These codes are attractive for two
reasons:
 Encoding and syndrome computation can be implemented easily by employing shift
registers with feedback connections (or linear sequential circuits).
 Because they have considerable inherent algebraic structure, it is possible to find various
practical methods for decoding them.
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Department of Applied Electronics & Instrumentation

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Cyclic Codes - Properties
• If the n-tuple v = (v0, v1,…, vn-1) are cyclic shifted one place to the right, we obtain another
n-tuple
v(1) = (vn-1, v0, v1,…, vn-2)
• which is called a cyclic shift of v
•If the v are cyclically shifted i places to the right, we have
• v(i) = (vn–i, vn–i+1,…, vn-1, v0, v1, …, vn-i-1)
• Cyclically shifting v i places to the right is equivalent to cyclically shifting v (n – i) place to
the left
• An (n, k) linear code C is called a cyclic code if
1. every cyclic shift of a code vector in C is also a code vector in C. (cyclic property)
2. sum of any two codewords is also a code vector in C. (linearity property)

Cyclic Codes
•To develop the algebraic properties of a cyclic code, we treat the components of a code vector v
= (v0, v1,…, vn-1) as the coefficients of a polynomial as follows:
• v(X) = v0 + v1X + v2X2 + ···+ vn-1Xn-1
If vn-1 ≠ 0, the degree of v(X) is n – 1
If vn-1 = 0, the degree of v(X) is less than n – 1
The correspondence between the vector v and the polynomial v(X) is one-to-one
• The (7, 4) linear code given in Table 4.1 is a cyclic code
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Cyclic Codes - Example
5

Cyclic Codes Description
• Polynomial Description
 Message blocks and codewords are represented as polynomials
 Encoding and decoding is based on generator polynomial and parity check polynomial
respectively
• Matrix Description
 Message blocks and codewords are represented as vectors
 Encoding and decoding is based on generator matrix and parity check matrix respectively
(as seen in LBC)
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Cyclic Codes
•The code polynomial that corresponds to the code vector v(i) is
•v(i)(X) = vn-i + vn-i+1X + ··· + vn-1Xi-1 +v0Xi + v1Xi+1 +···+ vn-i-1Xn-1
•Multiplying v(X) by Xi
, we obtain
• Xi
v(X) = v0Xi + v1Xi+1 + ···+ vn-i-1Xn-1 + ···+ vn-1Xn+i-1
• The equation above can be manipulated into the following form
• v(i)(X) is the remainder of [Xi
v(X)/(Xn + 1) ]
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Xi
v(X) = vn-i + vn-i+1X +··+ vn-1Xi-1 + v0Xi + ···+ vn-i-1Xn-1
+ vn-i(Xn+1) + vn-i+1X(Xn+1) + ··· + vn-1Xi-1(Xn+1)
= q(X)·(Xn + 1) + v(i)(X)

Generator polynomial of Cyclic Code
• g(x) is an irreducible polynomial of degree ‘n-k’ over GF(2)
• g(x) is a factor of (xn
+ 1)
• So to find generator polynomial, find factors of (xn
+ 1)
• g(x) = g0 + g1x + … + gn-k-1xn-k-1
+ gn-kxn-k
• g0 = 1 (if g0 ≠ 1, x will be a factor of g(x) and it will not be irreducible)
• gn-k = 1 (if gn-k ≠ 1, g(x) will not be a polynomial of degree (n –k)
• g(x) = 1 + g1x + g2x2
+ … + gn-k-1xn-k-1
+ xn-k
• Every code polynomial is a multiple of g(x)
• In an (n,k) cyclic code, there exists one and only one code polynomial of degree n-k
8

Generator polynomial of Cyclic Code
• For (7, 4) cyclic code, g(x) is a factor of X7 + 1
• The polynomial X7 + 1 can be factored as follows :
• X7 + 1 = (1 + X)(1 + X + X3)(1 + X2 + X3)
• Example: For (7, 4) cyclic code, g(x) = 1+x+x3
as it divides (x7
+ 1) completely
• There are two factors of degree 3; each generates a (7, 4) cyclic code
• The (7, 4) cyclic code given by Table 4.1 is generated by g(x) = 1 + x + x3
• This code has minimum distance 3 and it is a single error correcting code
• Each code polynomial is the product of a message polynomial of degree 3 or less and the
generator polynomial g(x) = 1 + x + x3
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Non-systematic Cyclic Codes
10
• Multiply message polynomial, u(x) with g(x) to form v(x), since
code polynomial is a multiple of g(x)
• v(x) = u(x)g(x)
• u(x) – message polynomial of degree (k-1)
• u(x) = u0 + u1x + … + uk-2xk-2
+ uk-1xk-1
• g(x) – generator polynomial of degree (n-k)
• g(x) = g0 + g1x + … + gn-k-1xn-k-1
+ gn-kxn-k
• v(x) – code polynomial of degree (n-1)
• v(x) = v0 + v1x + … + vn-2xn-2
+ vn-1xn-1

Non-systematic Cyclic Codes
11
1+x3
+x5
+x6
= (1+x+x2
+x3
)•g(x)
1 0 0 1 0 1 1
( 1 1 1 1 )
x+x5
+x6
= (x+x2
+x3
)•g(x)
0 1 0 0 0 1 1
( 0 1 1 1 )
1+x+x2
+x3
+x4
+x5
+x6
= (1+x2
+x3
)•g(x)
1 1 1 1 1 1 1
( 1 0 1 1 )
x2
+x4
+x5
+x6
= (x2
+x3
)•g(x)
0 0 1 0 1 1 1
( 0 0 1 1 )
1+x2
+x6
= (1+x+x3
)•g(x)
1 0 1 0 0 0 1
( 1 1 0 1 )
x+x2
+x3
+x6
= (x+x3
)•g(x)
0 1 1 1 0 0 1
( 0 1 0 1 )
1+x+x4
+x6
= x3
•g(x)
1 1 0 0 1 0 1
( 1 0 0 1 )
x3
+x4
+x6
= x3
•g(x)
0 0 0 1 1 0 1
( 0 0 0 1 )
1+x4
+x5
= (1+x+x2
)•g(x)
1 0 0 0 1 1 0
( 1 1 1 0 )
x+x3
+x4
+x5
= (x+x2
)•g(x)
0 1 0 1 1 1 0
( 0 1 1 0 )
1+x+x2
+x5
= (1+x2
)•g(x)
1 1 1 0 0 1 0
( 1 0 1 0 )
x2
+x3
+x5
= x2
•g(x)
0 0 1 1 0 1 0
( 0 0 1 0 )
1+x2
+x3
+x4
= (1+x)•g(x)
1 0 1 1 1 0 0
( 1 1 0 0 )
x+x2
+x4
= x•g(x)
0 1 1 0 1 0 0
( 0 1 0 0 )
1+x+x3
= 1•g(x)
1 1 0 1 0 0 0
( 1 0 0 0 )
0 = 0•g(x)
0 0 0 0 0 0 0
( 0 0 0 0 )
Code polynomials
Code Vectors
Messages
TABLE 4.1 A (7, 4) CYCLIC CODE GENERATED BY g(x) = 1+x+x3
Non-Systematic Encoding
 v(x) = u(x)g(x)
• u(x) = u0 + u1x + u2x2
+ u3x3
• g(x) = g0 + g1x + g2x2
+ g3x3
• v(x) = v0 + v1x + v2x2
+ v3x3
+ v4x4
+ v5x5
+ v6x6
• For eg. u=(0 0 1 1)
• u(x) = u0 + u1x + u2x2
+ u3x3
= x2
+ x3
• v(x) = u(x) . g(x) = (x2
+ x3
) (1+ x + x3
)
• v(x) = x2
+ x3
+ x5
+ x3
+ x4
+ x6
• v(x) = x2
+ x3
+ x5
+ x3
+ x4
+ x6
• v(x) = x2
+ x4
+ x5
+ x6

Systematic Cyclic Codes
12
• Shift message bits to last k codeword bit positions - xn-k
u(x)
• u(x) = u0 + u1x + … + uk-2xk-2
+ uk-1xk-1
• xn-k
u(x) = u0 xn-k
+ u1 xn-k +1
+ … + uk-2xn-2
+ uk-1xn-1
• First (n-k) parity bits of codeword is formed by adding remainder of [xn-k
u(x)/g(x)] to xn-
k
u(x). Adding remainder to divident ensures that code polynomial is a multiple of g(x).
• Let t(x) = Remainder of [xn-k
u(x)/g(x)]
• t(x) = t0 + t1x + … + tn-k-1xn-k-1
• v(x) = t(x) + xn-k
u(x)
• v(x) = v0 + v1x + … + vn-2xn-2
+ vn-1xn-1
• v(x) = t0 + t1x + … + tn-k-1xn-k-1
+u0 xn-k
+ u1 xn-k +1
+ … + uk-2xn-2
+ uk-1xn-1
• v =(t0, t1, …, tn-k-1, u0, u1, …,uk-1)

Systematic Cyclic Codes
13
x3
(x3
+1)
(x3
+x+1)
= x + x2
1+x+x2
+x3
+x4
+x5
+x6
= (1+x2
+x5
)•g(x)
1 1 1 1 1 1 1
( 1 1 1 1 )
x2
+ x4
+x5
+x6
= (x2
+x3
)•g(x)
0 0 1 0 1 1 1
( 0 1 1 1 )
1+x3
+x5
+x6
= (1+x+x2
+x3
)•g(x)
1 0 0 1 0 1 1
( 1 0 1 1 )
x+x5
+x6
= (x+x2
+x3
)•g(x)
0 1 0 0 0 1 1
( 0 0 1 1 )
x3
+x4
+x6
= x3
•g(x)
0 0 0 1 1 0 1
( 1 1 0 1 )
1+x+x4
+x6
= (1+x3
)•g(x)
1 1 0 0 1 0 1
( 0 1 0 1 )
x+x2
+x3
+x6
= (x+x3
)•g(x)
0 1 1 1 0 0 1
( 1 0 0 1 )
1+x2
+x6
= (1+x+x3
)•g(x)
1 0 1 0 0 0 1
( 0 0 0 1 )
x+x3
+x4
+x5
= (x+x2
)•g(x)
0 1 0 1 1 1 0
( 1 1 1 0 )
1+x4
+x5
= (1+x+x2
)•g(x)
1 0 0 0 1 1 0
( 0 1 1 0 )
x2
+ x3
+x5
= x2
•g(x)
0 0 1 1 0 1 0
( 1 0 1 0 )
1+x+x2
+x5
= (1+x2
)•g(x)
1 1 1 0 0 1 0
( 0 0 1 0 )
1+x2
+x3
+x4
= (1+x)•g(x)
1 0 1 1 1 0 0
( 1 1 0 0 )
x+x2
+x4
= x•g(x)
0 1 1 0 1 0 0
( 0 1 0 0 )
1+x+x3
= 1•g(x)
1 1 0 1 0 0 0
( 1 0 0 0 )
0 = 0•g(x)
0 0 0 0 0 0 0
( 0 0 0 0 )
Code polynomials
Code Vectors
Messages
systematic
 v(x) = t(x) + xn-k
u(x)
t(x) = Remainder of [xn-k
u(x)/g(x)]
Systematic Encoding
• For eg. u=(1 0 0 1)
• u(x) = 1+ x3
• xn-k
u(x) = x3
(x3
+1) = x6
+ x3
• t(x) = x + x2
• v(x) = t(x) + xn-k
u(x)
• v(x) = x + x2
+ x3
+ x6

Generator Matrix of Non-systematic Cyclic code - Method I
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• The size of generator matrix of (n, k) cyclic code is k x n
• The generator matrix for (7,4) cyclic code with
𝐺=
[
¿ 𝑔( 𝑋 )
¿ 𝑋𝑔( 𝑋)
¿ :
¿ X k −1
𝑔( 𝑋)
]
G 4 x 7 =
[
¿1101000
¿0110100
¿0011010
¿ 0001101
]

Generator Matrix of Non-Systematic Cyclic code - Method II
• Find the non-systematic codewords corresponding to all possible unit message vectors [ eg.
for (7, 4) code, find non-systematic codewords for (1000), (0100), (0010), (0001).]
• Then arrange it as rows of G matrix.
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1+x3
+x5
+x6
= (1+x+x2
+x3
)•g(x)
1 0 0 1 0 1 1
( 1 1 1 1 )
x+x5
+x6
= (x+x2
+x3
)•g(x)
0 1 0 0 0 1 1
( 0 1 1 1 )
1+x+x2
+x3
+x4
+x5
+x6
= (1+x2
+x4
)•g(x)
1 1 1 1 1 1 1
( 1 0 1 1 )
x2
+x4
+x5
+x6
= (x2
+x3
)•g(x)
0 0 1 0 1 1 1
( 0 0 1 1 )
1+x2
+x6
= (1+x+x3
)•g(x)
1 0 1 0 0 0 1
( 1 1 0 1 )
x+x2
+x3
+x6
= (x+x3
)•g(x)
0 1 1 1 0 0 1
( 0 1 0 1 )
1+x+x4
+x6
= x3
•g(x)
1 1 0 0 1 0 1
( 1 0 0 1 )
x3
+x4
+x6
= x3
•g(x)
0 0 0 1 1 0 1
( 0 0 0 1 )
1+x4
+x5
= (1+x+x2
)•g(x)
1 0 0 0 1 1 0
( 1 1 1 0 )
x+x3
+x4
+x5
= (x+x2
)•g(x)
0 1 0 1 1 1 0
( 0 1 1 0 )
1+x+x2
+x5
= (1+x2
)•g(x)
1 1 1 0 0 1 0
( 1 0 1 0 )
x2
+x3
+x5
= x2
•g(x)
0 0 1 1 0 1 0
( 0 0 1 0 )
1+x2
+x3
+x4
= (1+x)•g(x)
1 0 1 1 1 0 0
( 1 1 0 0 )
x+x2
+x4
= x•g(x)
0 1 1 0 1 0 0
( 0 1 0 0 )
1+x+x3
= 1•g(x)
1 1 0 1 0 0 0
( 1 0 0 0 )
0 = 0•g(x)
0 0 0 0 0 0 0
( 0 0 0 0 )
Code polynomials
Code Vectors
Messages
Non-Systematic Encoding
 v(x) = u(x)g(x)

Generator Matrix of Systematic Cyclic code - Method I
16
• Systematic generator matrix is generated from non-systematic version through row
transformations
• Systematic generator matrix can be obtained if the first row is added to the third row and
the sum of the first two rows is added to the fourth row
G non −sys=
[
¿1101000
¿0110100
¿0011010
¿0001101
] G sys=
[
¿1101000
¿0110100
¿1110010
¿1010001
] R3’- R3+R1
R4’- R4+R2 +R1

Generator Matrix of Systematic Cyclic code - Method II
• Find the systematic codewords corresponding to all possible unit message vectors [ eg. for (7,
4) code, find systematic codewords for (1000), (0100), (0010), (0001).]
• Then arrange it as rows of G matrix.
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1+x+x2
+x3
+x4
+x5
+x6
= (1+x2
+x5
)•g(x)
1 1 1 1 1 1 1
( 1 1 1 1 )
x2
+ x4
+x5
+x6
= (x2
+x3
)•g(x)
0 0 1 0 1 1 1
( 0 1 1 1 )
1+x3
+x5
+x6
= (1+x+x2
+x3
)•g(x)
1 0 0 1 0 1 1
( 1 0 1 1 )
x+x5
+x6
= (x+x2
+x3
)•g(x)
0 1 0 0 0 1 1
( 0 0 1 1 )
x3
+x4
+x6
= x3
•g(x)
0 0 0 1 1 0 1
( 1 1 0 1 )
1+x+x4
+x6
= (1+x3
)•g(x)
1 1 0 0 1 0 1
( 0 1 0 1 )
x+x2
+x3
+x6
= (x+x3
)•g(x)
0 1 1 1 0 0 1
( 1 0 0 1 )
1+x2
+x6
= (1+x+x3
)•g(x)
1 0 1 0 0 0 1
( 0 0 0 1 )
x+x3
+x4
+x5
= (x+x2
)•g(x)
0 1 0 1 1 1 0
( 1 1 1 0 )
1+x4
+x5
= (1+x+x2
)•g(x)
1 0 0 0 1 1 0
( 0 1 1 0 )
x2
+ x3
+x5
= x2
•g(x)
0 0 1 1 0 1 0
( 1 0 1 0 )
1+x+x2
+x5
= (1+x2
)•g(x)
1 1 1 0 0 1 0
( 0 0 1 0 )
1+x2
+x3
+x4
= (1+x)•g(x)
1 0 1 1 1 0 0
( 1 1 0 0 )
x+x2
+x4
= x•g(x)
0 1 1 0 1 0 0
( 0 1 0 0 )
1+x+x3
= 1•g(x)
1 1 0 1 0 0 0
( 1 0 0 0 )
0 = 0•g(x)
0 0 0 0 0 0 0
( 0 0 0 0 )
Code polynomials
Code Vectors
Messages
 v(x) = xn-k
u(x) + t(x)
t(x) = Remainder of [xn-k
u(x)/g(x)]
Systematic Encoding

Encoding of Cyclic codes from Generator Matrix
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• If the generator matrix of cyclic code is known, the codewords can be obtained by just
multiplying message block, u with the generator matrix, G (as in (n, k) LBC).
• v = u.G

Parity check polynomial of Cyclic code
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•The generator polynomial g(X) is a factor of Xn + 1
•Relation between g(x) and h(x) is Xn + 1 = g(X)h(X)
h(X) = (1+Xn
)/g(X)
Parity check polynomial, h(X) has the degree k and is of the following form :
h(X) = h0 + h1X + ···+ hkXk
with h0 = hk = 1
Eg: (7,4) code with g(X)=1+X+X3
h(X) = (1+X7
)/g(X) =1+X+X2
+X4

Parity check Matrix of Non-Systematic Cyclic code
20
•To construct parity check matrix H, the reciprocal of h(X) is used.
•Reciprocal of h(X) Xk h(X-1) = hk + hk-1X + ···+ h0Xk
Since, h(X-1) = h0 + h1X-1 + ···+ hkX-k
•Xk h(X-1) is also a factor of Xn + 1
Eg. For (7,4) cyclic code, h(X) = 1+X+X2
+X4
Reciprocal of h(X) X4
h(X-1
)=X4
(1+X-1
+X-2
+X-4
)=1+X2
+X3
+X4

Parity check Matrix of Non-Systematic Cyclic code
• The size of parity check matrix of (n, k) cyclic code is (n-k) x n
• The parity check matrix for (7,4) cyclic code with
21
𝐻 =
[
¿ 𝑋 k
h ( 𝑋 −1
)
¿ 𝑋
k +1
h( 𝑋
−1
)
¿ :
¿ 𝑋
k+(𝑛−𝑘 − 1)
h( 𝑋
−1
)
]



H(3 x 7) =

Parity check Matrix of Systematic Cyclic code
• Systematic parity check matrix is generated from non-systematic version through row
transformations
• Systematic parity check matrix can be obtained if the first row is added to the third row
22
Hnon-sys = Hsys = R1’- R1+R3

Encoder Circuit for Cyclic Codes
• Generation of non-systematic cyclic codes requires multiplication circuit
• v(x) = u(x)g(x)
• Generation of systematic cyclic codes requires division circuit to find the remainder.
• v(x) = t(x) + xn-k
u(x)
• Both can be realized using (n – k) bit shift registers along with modulo 2 adders
• Multiplication circuit can be realized using feed forward shift register
• Division circuit can be realized using feed back shift register
23

Encoder Circuit for Non-Systematic Cyclic Code
Fibanocci Form – General Non-Systematic Encoder circuit
Encoder circuit for (7,4) Non-systematic Cyclic Code with
u(x)
g1
SRn-k-1
g2
…
SR2
gn-k-1
SR1
gn-k =1
v(x)
gn-k-2 g0 =1
SRn-k
u(x) SR2
SR1
g3 =1 g0 =1
SR3
v(x)
g2 = 0 g1 = 1
Department of Applied Electronics & Instrumentation 24

Suppose that the message u = (1 0 1 1) is
to be encoded
v = (1 1 1 1 1 1 1)
v(x) = 1 + x+ x2
+ x3
+ x4
+ x5
+ x6
Fibanocci Form - Encoder circuit for (7,4) non- systematic Cyclic Code with
u(x) SR2
SR1
g3 =1 g0 =1
SR3
v(x)
g2 = 0 g1 = 1
Shift
Number
Input
Queue
Bit Shifted
In, u
Contents of shift register
Output, v Remarks
SR1 SR2 SR3
0 0001011 - 0 0 0 - Reset or initial state
1 000101 1 1 0 0 1 Co-efficient of x6
2 00010 1 1 1 0 1 Co-efficient of x5
3 0001 0 0 1 1 1 Co-efficient of x4
7 - 0 0 0 0 1 Co-efficient of x0
• SR1c = uc
• SR2c = SR1p
• SR3c = SR2p
• outputc = uc + SR2p + SR3p
• subscript, c – current
• subscript, p - previous

26
1+x3
+x5
+x6
= (1+x+x2
+x3
)•g(x)
1 0 0 1 0 1 1
( 1 1 1 1 )
x+x5
+x6
= (x+x2
+x3
)•g(x)
0 1 0 0 0 1 1
( 0 1 1 1 )
1+x+x2
+x3
+x4
+x5
+x6
= (1+x2
+x4
)•g(x)
1 1 1 1 1 1 1
( 1 0 1 1 )
x2
+x4
+x5
+x6
= (x2
+x3
)•g(x)
0 0 1 0 1 1 1
( 0 0 1 1 )
1+x2
+x6
= (1+x+x3
)•g(x)
1 0 1 0 0 0 1
( 1 1 0 1 )
x+x2
+x3
+x6
= (x+x3
)•g(x)
0 1 1 1 0 0 1
( 0 1 0 1 )
1+x+x4
+x6
= x3
•g(x)
1 1 0 0 1 0 1
( 1 0 0 1 )
x3
+x4
+x6
= x3
•g(x)
0 0 0 1 1 0 1
( 0 0 0 1 )
1+x4
+x5
= (1+x+x2
)•g(x)
1 0 0 0 1 1 0
( 1 1 1 0 )
x+x3
+x4
+x5
= (x+x2
)•g(x)
0 1 0 1 1 1 0
( 0 1 1 0 )
1+x+x2
+x5
= (1+x2
)•g(x)
1 1 1 0 0 1 0
( 1 0 1 0 )
x2
+x3
+x5
= x2
•g(x)
0 0 1 1 0 1 0
( 0 0 1 0 )
1+x2
+x3
+x4
= (1+x)•g(x)
1 0 1 1 1 0 0
( 1 1 0 0 )
x+x2
+x4
= x•g(x)
0 1 1 0 1 0 0
( 0 1 0 0 )
1+x+x3
= 1•g(x)
1 1 0 1 0 0 0
( 1 0 0 0 )
0 = 0•g(x)
0 0 0 0 0 0 0
( 0 0 0 0 )
Code polynomials
Code Vectors
Messages
Non-Systematic Cyclic Code

Galois Form – General Non-Systematic Encoder circuit
Encoder circuit for (7,4) Non- systematic Cyclic Code with
u(x)
g0 =1
SRn-k
g1
SRn-k-1
g2
… SR2
gn-k-1
SR1
gn-k =1
v(x)
u(x)
g0 =1
SR3 SR2
SR1
g1 =1 g3 =1
g2 = 0
v(x)

Galois Form - Encoder circuit for (7,4) non-systematic Cyclic Code with
Suppose that the message u = (1 0 1 1) is
to be encoded
v = (1 1 1 1 1 1 1)
v(x) = 1 + x+ x2
+ x3
+ x4
+ x5
+ x6
Shift
Number
Input
Queue
Bit Shifted
In
Output Remarks
SR3 SR2 SR1
1 000101 1 1 1 0 1 Co-efficient of x6
2 00010 1 1 0 1 1 Co-efficient of x5
7 - 0 0 0 0 1 Co-efficient of x0
u(x)
g0 =1
SR3 SR2
SR1
g1 =1 g3 =1
g2 = 0
v(x)
• SR3c = uc
• SR2c = uc + SR3p
• SR1c = SR2p
• outputc = uc + SR1p

Encoder Circuit for Systematic Cyclic Code
•Encoding of an (n, k) cyclic code in systematic form consists of three steps:
1. Multiply the message polynomial u(x) by xn-k
2. Divide xn-k u(x) by g(x) to obtain the remainder t(x)
3. Form the code word t(x) + xn-k u(x)
• All these three steps can be accomplished with a division circuit which is a linear (n-k)-
stage shift register with feedback connections based on the generator polynomial

30
Steps
1. The switch S is in position 1 to allow the transmission of message bits directly to the
output shift register during the first k shifts.
2. At the same time, GATE (switch) is ON to allow transmission of message bits into the
(n-k) stage encoding shift register
3. After transmission of the kth message bit, the GATE is turned OFF and the switch S is
moved to position 2

31
Steps
4. (n-k) zeros introduced at A after step 3, clear the encoding register by moving the
parity bits to the output register
5. The total number of shifts is equal to n and the contents of the output register is the
codeword polynomial, v(x) = t(x) + xn-k
u(x)
6. After step 4, the encoder is ready to take up encoding of the next message input.

Encoder circuit for (7,4) Systematic Cyclic Code with

Encoder circuit for (7,4) Systematic
Cyclic Code with
• Suppose that the message u = (1 0 1 1) is to be encoded. As the
message digits are shifted into the register, the contents in the
register are as given in table.
• After four shifts, the contents of the register are (1 0 0)
which is the remainder of the division
• v =(1 0 0 1 0 1 1)
• v(x) = 1 + x3
+ x5
+ x6
Shift
Number
Input
Queue
Bit Shifted
In, u
Output, v Remarks
p0 p1 p2
1 000101 1 1 1 0 1 Gate ON & S in 1
2 00010 1 1 0 1 1 “
3 0001 0 1 0 0 0 “
4 000 1 1 0 0 1 “
5 00 0 0 1 0 0 Gate OFF & S in 2
6 0 0 0 0 1 0 “
7 - 0 0 0 0 1 “
Upto shift 4 (GATE ON)
• p0c = uc+ p2p
• p1c = uc + p2p + p0p
• p2c = p1p
• outputc = uc
From shift 5 to 7 (GATE OFF)
• uc = 0 (or A with zeros)
• p0c = 0
• p1c = p0p
• p2c = p1p
• outputc = p2p

34
1+x+x2
+x3
+x4
+x5
+x6
= (1+x2
+x5
)•g(x)
1 1 1 1 1 1 1
( 1 1 1 1 )
x2
+ x4
+x5
+x6
= (x2
+x3
)•g(x)
0 0 1 0 1 1 1
( 0 1 1 1 )
1+x3
+x5
+x6
= (1+x+x2
+x3
)•g(x)
1 0 0 1 0 1 1
( 1 0 1 1 )
x+x5
+x6
= (x+x2
+x3
)•g(x)
0 1 0 0 0 1 1
( 0 0 1 1 )
x3
+x4
+x6
= x3
•g(x)
0 0 0 1 1 0 1
( 1 1 0 1 )
1+x+x4
+x6
= (1+x3
)•g(x)
1 1 0 0 1 0 1
( 0 1 0 1 )
x+x2
+x3
+x6
= (x+x3
)•g(x)
0 1 1 1 0 0 1
( 1 0 0 1 )
1+x2
+x6
= (1+x+x3
)•g(x)
1 0 1 0 0 0 1
( 0 0 0 1 )
x+x3
+x4
+x5
= (x+x2
)•g(x)
0 1 0 1 1 1 0
( 1 1 1 0 )
1+x4
+x5
= (1+x+x2
)•g(x)
1 0 0 0 1 1 0
( 0 1 1 0 )
x2
+ x3
+x5
= x2
•g(x)
0 0 1 1 0 1 0
( 1 0 1 0 )
1+x+x2
+x5
= (1+x2
)•g(x)
1 1 1 0 0 1 0
( 0 0 1 0 )
1+x2
+x3
+x4
= (1+x)•g(x)
1 0 1 1 1 0 0
( 1 1 0 0 )
x+x2
+x4
= x•g(x)
0 1 1 0 1 0 0
( 0 1 0 0 )
1+x+x3
= 1•g(x)
1 1 0 1 0 0 0
( 1 0 0 0 )
0 = 0•g(x)
0 0 0 0 0 0 0
( 0 0 0 0 )
Code polynomials
Code Vectors
Messages
Systematic Cyclic Code

Decoding of Cyclic Codes
• Let the transmitted code vector be v = (v0, v1,…, vn-1) and the received code vector be r = (r0, r1,
…, rn-1) .
• As in LBC, the decoder first computes the syndrome to check whether the received code
vector is valid or not.
• If the syndrome is all zero, then ‘r’ is a valid codeword
• Then r(x) must be divisible by g(x) since v(x) = u(x).g(x).
• If the syndrome is non-zero, then ‘r’ contains errors and needs error correction.
35

Syndrome Computation and Error Detection
•The received vector r is treated as a polynomial of degree n – 1
r(x) = r0 + r1x + ···+ rn-1xn-1
• Dividing r(X) by the generator polynomial g(x), we obtain
• where a(x) is the quotient
• The remainder, s(x) is syndrome polynomial of degree n – k – 1 or less. The n – k
coefficients of s(x) form the syndrome s
• s(x) = s0 + s1x + ···+ sn-k-1xn-k-1
• The syndrome calculation can be accomplished by a divider circuit which is similar to the
encoder circuit of systematic cyclic codes
36

Relation between Syndrome and Error pattern
• The received polynomial is r(x)=v(x)+e(x)
• e(x) is the polynomial representing error pattern caused by the channel
• e(x) = e0 + e1x + ···+ en-1xn-1
• Error polynomial, e(x) = v(x) + r(x)
• Since v(x) = u(x)g(x) and
• e(x) = v(x) + r(x)
• e(x) = u(x)g(x) +
• e(x)=[a(x)+u(x)]g(x)+s(x)
• This shows that the syndrome is actually equal to the remainder resulting from dividing the
error pattern by the generator polynomial.
37

Error Detection - Syndrome Calculator Circuit
Steps
1. The register is first initialized with Gate 2 ON and Gate 1 OFF, and the received vector, r is
entered into the register
2. After the entire ‘r’ is shifted into the register, the contents of the register will be the
syndrome, which is shifted out of the register by turning Gate 1 ON and Gate 2 OFF.
38
g1
s0 s1
…
Gate 2
g2 gn-k-1
sn-k-1
r(X)
Received
vector
Gate 1
s(X)
g0 =1 gn-k =1

Syndrome Calculation - Example
39
Shift Input Register contents
r s0s1s2
0 0 0 (initial state)
1 0 0 0 0
2 1 1 0 0
3 1 1 1 0
4 0 0 1 1
5 1 0 1 1
6 0 1 1 1
7 0 1 0 1 (syndrome s)
Suppose that the receive vector is r = (0 0 1 0 1 1 0). The syndrome of r is s = (1 0 1).
A syndrome circuit for the (7, 4) cyclic code
generated by g(x) = 1 + x + x3
s0 s1
r(X)
Received
vector
g0 =1
s2
Gate 2
Gate 1 s(X)
g1 =1 g3 =1
g2 = 0
Upto shift 7 (GATE 2 ON)
• s0c = rc+ s2p
• s1c = s2p + s0p
• s2c = s1p

General Decoder for Cyclic Codes
40
Gate 2
Syndrome Register
Error pattern Detector
(Combinational Logic Circuit)
ei
Feedback Connections
Buffer Register Gate 2
Gate 1
Gate
1
Received
Code vector
Corrected
Code vector
Input

Step1
• Received data is shifted into the buffer register and syndrome registers with Gates 1
(switches) ON and Gates 2 OFF. Error correction is performed with Gates 1 OFF and Gates 2
ON.
41
Gate 2
Syndrome Register
ei
Gate
1
Gate
1
Received
Code vector
Corrected
Code vector
Input

Step 2
• The detector is a combinational logic circuit which is designed in such a way that its output is 1 iff the syndrome
in the syndrome register corresponds to a correctable error pattern with an error at the highest-order position Xn–
1
• If a “1” appears at the output of the detector, the received symbol in the rightmost stage of the buffer register is
assumed to be erroneous and must be corrected
• If a “0” appears at the output of the detector, the received symbol at the rightmost stage of the buffer register is
assumed to be correct and no correction necessary
• Thus the detector output is the estimate error value for the symbol coming out of the buffer register
42
Gate 2
Syndrome Register
ei
Gate
1
Gate
1
Received
Code vector
Corrected
Code vector
Input

Step 3
• The first received digit in the syndrome register is shifted right once.
• If the first received digit is in error, the detector output will be 1 which is used for error correction.
• The output of the detector is also fed back to the syndrome register to modify the syndrome
• This results in a new syndrome corresponding to the altered received codeword shifted to the right by one
place.
43
Gate 2
Syndrome Register
ei
Gate
1
Gate
1
Received
Code vector
Corrected
Code vector
Input

Step 4
• The new syndrome is now used to check whether the second received digit, which is now at the rightmost
position, is an erroneous digit.
• If so, it is corrected, a new syndrome is calculated as in step 3 and the procedure is repeated.
Step 5
• The decoder operates on the received data digit by digit until the entire received codeword is shifted out of the
buffer register,
This decoder is known as Meggitt decoder
44
Gate 2
Syndrome Register
ei
Gate
1
Gate
1
Received
Code vector
Corrected
Code vector
Input

Meggitt decoder
At the end of the decoding operation, after the received codeword is shifted out of the buffer, all those errors
corresponding to correctable error patterns will have been corrected and the syndrome register will contain
all zeros.
If the syndrome register does not contain all zeros, this means that an un correctable error pattern has been
detected.
45
Gate 2
Syndrome Register
ei
Gate
1
Gate
1
Received
Code vector
Corrected
Code vector
Input

Meggitt Decoder for (7, 4) Cyclic Code
• After seven shifts, the input r(x) is disconnected from both syndrome register and buffer register
• After the seventh shift whenever the shift register content becomes (100), the output of the coincidence gate becomes
‘1’. This is because (100) corresponds to the remainder obtained for error pattern, e = (1000000) when divided by g(x).
• At that instant, the bit of r(x) coming out of the 7 bit buffer gets corrected at the output of the coincidence gate.
46
• s0c = rc+ s2p
• s1c = s2p + s0p
• s2c = s1p
s0 s1
r(x)
Received
vector
g0 =1
s2
g1 =1 g3 =1
g2 = 0
7 bit Buffer Register
Corrected
Code vector
Coincidence gate
Output = 1 if (s0s1s2) =(100)

47
r s0s1s2
1 0 0 0 0
2 1 1 0 0
3 0 0 1 0
4 1 1 0 1
5 0 1 0 0
6 0 0 1 0
8 0 1 0 0 (syndrome s(1)
)
• Suppose r =(1001010) for (7, 4) cyclic code with g(x)
= 1 + x + x3
, then s = (101) and , e = (0000001)
• The corrected code vector =(1001011) as the
syndrome is (100) at the 8th
shift.
• s0c = rc+ s2p
• s1c = s2p + s0p
• s2c = s1p
s0 s1
r(x)
Received
vector
g0 =1
s2
g1 =1 g3 =1
g2 = 0
Corrected
Code vector
Coincidence gate
Output = 1 if (s0s1s2)
=(100)

48
r s0s1s2
1 1 1 0 0
2 1 1 1 0
3 1 1 1 1
4 1 0 0 1
5 0 1 1 0
6 0 0 1 1
8 0 1 1 1 (syndrome s(1)
)
9 0 1 0 1
10 0 1 0 0
• Suppose r =(1001111) for (7, 4) cyclic code with g(x)
= 1 + x + x3
, then s = (011) and , e = (0000100)
• The corrected code vector =(1001011) as the
syndrome is (100) at the 10th
shift.
• s0c = rc+ s2p
• s1c = s2p + s0p
• s2c = s1p
s0 s1
r(x)
Received
vector
g0 =1
s2
g1 =1 g3 =1
g2 = 0
Corrected
Code vector
Coincidence gate
Output = 1 if (s0s1s2)
=(100)

THANK YOU…
Department of Electronics & Communication 49

Error Control Codes or Channel Codes - Cyclic Codes

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