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Alpha Science International Ltd.
Oxford, U.K.
S.S.S.P. Rao
Field Programmable Gate Arrays
and Applications

S.S.S.P. Rao
Department of Computer Science & Engineering
Indian Institute of Technology Powai
Mumbai
Copyright © 2016
ALPHA SCIENCE INTERNATIONAL LTD.
7200 The Quorum, Oxford Business Park North
Garsington Road, Oxford OX4 2JZ, U.K.
www.alphasci.com
ISBN 978-1-78332-215-2
All rights reserved. No part of this publication may be reproduced, stored in
a retrieval system, or transmitted in any form or by any means, electronic,
mechanical, photocopying, recording or otherwise, without prior written
permission of the publisher.
Field Programmable Gate Arrays
and Applications
372 Pags. | 203 Figs. | 41 Tabls.
E-ISBN 978-1-78332-324-1

Dedicated to
Srikantam Krishna Rao
and
Srikantam Saradamba

As Professor of Computer Science and Engineering, Indian Institute of Technology-Bombay,
I started teaching Architectural details and design methodologies of Field Programmable
gate Arrays (FPGAs) since their introduction in 1983. My students at undergraduate
and postgraduate levels did projects during my tenure of Professorship using right from
Xilinx XC 2000 to Spartan 6. Public and Private sectors in India sponsored projects to me
to do FPGA based embedded systems and my project engineers successfully completed
them to the satisfaction of the sponsor. After my retirement from IIT-Bombay, I got an
opportunity to join Xilinx Centre established in Hyderabad by Akshya Prakash of Xilinx,
USA as their Chief Technology Officer. After my tenure in this organization I joined CMC
Limited, Hyderabad and advised CMC engineers in their FPGA projects in the Embedded
Systems Group. Then I thought of putting all my academic and industrial experience in a
book form and with the help of some experts finalized the contents of the book. Since Field
Programmable gate arrays belong to the family of programmable devices and designing
with FPGAs require knowledge of Digital design, Chapter 1 was devoted to cover an
overview of Boolean Algebra and Logic Design. This chapter covers gates, minimization
techniques of Boolean expressions and combinational and sequential logic circuits and state
machines with design examples. The next topic is on Programmable Logic Devices which is
covered in Chapter 2. In this chapter; SPLDs and CPLDs are explained and their internal
organization is presented which include ROM, PAL and PLA. PLD Design methodologies
with tools are covered with design examples. Introduction to Field programmable devices
(FPGAs) are then explained right from the basic FPGA which was used as glue logic to
present day very advanced FPGA used in Embedded Systems. Design flow for FPGA is
then given and applications of FPGAs are listed. Comparison of Microcontrollers, FPGAs
and ASIC is discussed. Chapter 3 is completely devoted to evolution of Xilinx FPGAs and
their architectural features. Chapter 4 covers Altera FPGAs and Actel/Microsemi FPGAS
are reviewed in Chapter 5. Since designing with FPGAs require knowledge of hardware
description languages, Verilog and VHDL with many design examples in Verilog and
VHDL and brief introduction to System Verilog form the chapter 6. In chapter 7 complete
Xilinx FPGA design flow is covered right from architectural specification to obtaining bit
Preface

stream to be loaded into FPGA and testing methodologies. Chapter 8 completely covers
design exercises using Spartan Series that include an ALU, Multiplier unit and Arbiter
using round robin algorithm. These applications give the reader good understanding of
designing systems using FPGAs with design tools. Having seen SRAM, Antifuse, Flash
FPGA Programming Technologies, a comparison of these technologies would greatly help
the designer to choose the right one for his application based on conditions under which
his product functions reliably and safely. In chapter 9, this comparison is given along with
the important research issues of FPGA Security and Future of FPGAs for the next decade.
S.S.S.P. Rao
viii Preface

Advent of digital logic systems was facilitated by VLSI technology. It is interesting that one
can implement even a complex system such as a digital computer by using only AND, OR,
and NOT gates, further, we can implement using only NAND or NOR gates. A transistor
is basically an inverter and as such synthesis using only NAND or NOR gates, is possible,
but one needs a large number of transistors. VLSI made it possible to have large number of
gates on a chip. Difference between different systems was in the interconnection between
the gates. Technology produced a gate array which is an array of large number of gates.
It led to field programmable gate array chips with a matrix of interconnects which can be
modified to suit the required logic by removing undesirable inter connects by selectively
burning out chosen ones.
They number of gates on a FPGA (Field Programmable Gate Array) can be in thousands
and one can fabricate in the lab even a small special purpose computer in a short time.
Early advertisements mentioned that “one can conceive a special purpose chip at breakfast
and have the chip ready by dinner time! FPGA’s have made it easy for students to fabricate
their projects and have the satisfaction of building the desired system. FPGA is a boon to
remote colleges teaching digital design.
Dr. SSSP Rao has over 30 years of experience in teaching and design of digital systems
and is welcome that he has chosen to write a book on FPGA. It is like “hearing from the
horse’s mouth”! Coverage is comprehensive and the book is suited for a textbook as well
as for self-study, and It is appropriate that it is based on XILINX technology, which is
easily available in India.
I thank Dr. Rao for the book and wish all success to the book.
Prof. H N Mahabala
(Retd.) Professor
Department of Computer Science and Engineering
Indian Institute of Technology Madras
Chennai
Foreword-1

Ever since the transistor was invented in the middle years of the 20th century an era of
miniaturization in electronics has been heralded worldwide based on silicon technology
and the resulting microchip revolution. These have now become the corner stone in almost
every product/service developed for the benefit of mankind and enabled the launching of
new industries like design, technology, packaging, testing, applications, leading to the
present-day Information Age. The Field Programmable Gate Arrays (FPGAs) constitute
an important class of microchips that can be programmed in the laboratory or on the shop
floor to perform specific electronic functions in digital logic form. Since their inception
in the 1980s decade, FPGAs have grown in capacity and complexity to include millions
of logic gates, megabytes of memory and high speed interfaces in microchip form in the
current versions and have become the preferred choice in a wide range of applications,
such as consumer products, computing/communication/control/instrumentation areas as
well as military/space systems.
As a result, good knowledge/expertise in “FPGAs and Applications” is now expected
from graduating engineers in electrical/electronic/computer and related branches so that
they can exploit the emerging opportunities and prepare themselves for good careers in
this subject area. But, the absence of a comprehensive/contemporary text/reference book
covering this subject matter has been a long felt limitation at Indian Universities and
Institutions. Recognizing this, Prof. SSSP Rao, a senior computer science academic and
researcher with high expertise and long experience in working with FPGAs at the Indian
Institute of Technology, Mumbai has prepared this Book entitled, “Field Programmable
Gate Arrays and Applications” which can serve as text/reference source for engineering
& technology students at both UG/PG levels and professionals alike.
The book is well planned and organized to provide the reader with a good insight into
the fascinating world of FPGAs. Beginning with an Overview of Boolean Algebra and Logic
Design in Chapter 1 followed by state of the art coverage on Programmable Logic Devices
in Chapter 2, An Introduction to FPGAs, XILINX, ALTERA, ACTEL/MICROSEMI and
Overview of Hardware Descriptive Languages are covered in the next four Chapters.
Foreword-2

The FPGA Design Flow is then described in Chapter 7 followed by a range of Selected
Applications of Xilinx FPGAs to provide a flavour of the potential uses of FPGAs in present
day electronic product and services in chapter 8. The last Chapter covers the important
issue of FPGA Security and Future of FPGAs. An excellent Bibliography given at the end
of the chapter is very helpful to the reader in learning and gaining more experience in
this subject area. On the whole, the Book is an excellent addition to text/reference sources
now available in the broad area of VLSI Design and Applications of considerable use
in both learning/teaching and R&D/industry. I would like to compliment the author for
undertaking this commendable task and making a significant contribution to the world of
academic and research endeavour.
Prof. B. S. Sonde
Former Vice Chancellor
University of Goa
xii Foreword-2

Since the introduction of Field Programmable Gate Arrays (FPGAs) in around 1982, as
Faculty member of Indian Institute of Technology (IIT)-Bombay, I started teaching and
offering FPGA based projects from 1982 to 2005, using Xilinx XC 2000 to Spartan 6, to
Undergraduate, Post Graduate students of Electrical and Computer Science Engineering
Departments. Also FPGA based sponsored projects from public and private sectors were
successfully completed by project engineers under my guidance in IIT-Bombay. After my
retirement in IIT-Bombay, I joined Xilinx Centre established in Hyderabad in 2005 as
their Chief Technology Officer. This centre is established initially in CMC -Hyderabad
by Akshya Prakash from Xilinx, USA. After my tenure in Xilinx Centre, I joined CMC
Limited Hyderabad as their Chief Advisor and mentor and handled FPGA based projects
in the Embedded Systems Group. At that time I thought of putting all my academic and
industrial experience in designing with FPGAs in the form of a book and drafted the
contents. The contents of the book were reviewed by experts Akshya Prakash of Xilinx,
USA, Ms Usha Priyadharshini of IBM-Bangalore and Dr. Vamsi Srikantam of AMCC, USA
and contents of the book were finalized. My sincere thanks to all these experts. I should
place on record my sincere thanks to N.K. Mehra of Narosa Publishing House, Delhi who
on my communication readily agreed to publish the book. I should then place on record
my sincere thanks and appreciation to my colleagues from IIT-Bombay retired Professor
M.R Bhujade and Professor M.P. Desai for providing some excellent subject matter
for chapter 1 on Boolean Algebra and Logic Design: an Overview. Their help is greatly
acknowledged. Ron Wilson of ALTERA, USA and Gautam Sachin of MICROSEMI greatly
helped me in writing the chapters on ALTERA and ACTEL/MICRSEMI FPGAS by
providing technical information on their Company FPGAs. I would like to place on record
my sincere thanks and appreciation to both the experts. My interaction with Sachin Gupta
of Microsemi was excellent and I would like to sincerely thank him once again for his
untiring efforts to make this chapter on Actel/Microsemi FPGAs look highly technical
and informative. The contribution of Ms. Saambhavi of Xilinx Centre, Hyderabad needs
special mention of excellence in contributing to the chapter 6 on Hardware description
Acknowledgment

Languages (Verilog/VHDL). Her assistance is highly appreciated and I am very grateful
for her help.. In writing Chapter 7 on FPGA Design Flow, I got immense help from Akshya
Prakash of Xilinx, USA, Dr. Sudip Nag of Xilinx, USA and Mrinal Sarmah of Xilinx
Centre, Hyderabad. I would like to express my heartfelt gratitude to Mrinal Sarmah for
the excellent support he gave me in writing this chapter and also providing the subject
matter for this very important chapter. Special and sincere thanks to Mrinal for his great
contribution in shaping this design flow chapter. His untiring and excellent support is
gratefully acknowledged. Chapter 8 deals with Design Exercises using FPGAs. In this
chapter, instead of giving pure academic material, I thought of giving projects really
implemented and tested so that readers get real experience and understanding in FPGA
designs. Towards this end I sought help from a FPGA training Institute. Xilinx, USA has
given approval to an Institute in Bangalore, India called Sandeepani-School of Embedded
System Design, CG-CoreEl Technologies, Bangalore to give training to students and
practicing engineers in Xilinx FPGA based designs. On my request Sandeepani-CG-
coreEl Technologies agreed to provide FPGA based designs right from specifications to
implementation and test results done by students of the training Institute under the
supervision of Ms. Deepa and Padmanabhan in consultation with me. I am very confident
that these design projects give readers very good understanding of FPGA design practices. I
am highly grateful for all the assistance given by Deepa and Padmanabhan of Sandeepani-
CG Core El Technologies for giving material for this chapter a picture of reality. After
these three simple design exercises, a complex project involving design of High Speed
Telescope Data Acquisition System using FPGAs is explained. This design illustrates
how a complex FPGA design is translated from high level specifications to detailed micro-
architecture and how a self-checking test bench architecture is designed for a complex
FPGA design. This complex Project was done by Sunil Puranik of Computational Research
Laboratory, Pune and
Dr. Subrahmanya of Raman Research Institute, Bangalore. On my request they provided
me this information so that reader will understand how complex projects could be designed
using FPFGAs. I would like to thank both of them profusely for their untiring efforts
to help me in presenting this design. My sincere thanks to both the experts. I thank
profusely Prof. H.N. Mahabala, Retired Professor from the Department of Computer
Science and Engineering, IIT-Madras for writing Foreword -1. Now I would like to thank
and express my gratitude to Prof. Sonde, retired Professor from IISc, Bangalore and
former Vice Chancellor of Goa University who while writing Foreword-2 for my book after
going through some chapters he suggested to me to include some research oriented issues
related to FPGAs like FPGA security since FPGAs are being used in very sensitive and
very confidential projects in industrial and military applications. Dr. Trimberger of Xilinx,
USA presented a paper on FPGA security which is published by IEEE proceedings. With
the permission of the author and publisher IEEE, I included this research oriented topic
in chapter 9. I hereby express my thanks and gratitude to Dr.Trimberger and IEEE for
giving permission to take material from the paper ` FPGA Security: Motivations, Features,
and Applications, Proceedings of IEEE, Vol. 102, No.8, August 2014, pp 1248-1265.. In
a ACM work shop, industry people like Xilinx CTO and Senior Vice President Dr. Ivo
Bolsens and Altera CTO and senior vice president of Research and Development, Misha
xiv Acknowledgment

Burich etc and academicians like Prof. Peter Cheung, Head of Department of Electrical
and Electronic Engineering, Imperial College, London debated on Future of FPGS till 2032
which gives very interesting topics for research. The discussion that took place in this ACM
conference was published by Ron Wilson, Editor-in Chief of Altera. I met him in Altera
and had discussions on this topic and with his permission I included this topic in Chapter
9 which will help research scholars to do further research on this. My sincere thanks to
Ron Wilson for all the help he gave in writing this material on Future of FPGAs till 2032.
I am extremely thankful to Ms N.P. Shravya of CMC Limited for drawing diagrams for this
book with a fine comb. Finally I should express my sense of appreciation and gratitude to
my wife Mrs. Rajeswari who gave me immense encouragement and support while I was
busy with my writing at home. I hope with all the material in this book it will greatly help
students and practicing engineers in understanding FPGA based designs and research
scholars to do further research on future of FPGAs and FPGA Security methods.
S.S.S.P. Rao
Acknowledgment xv

Preface..................................................................................................................................................... vii
Foreword-1..............................................................................................................................................ix
Foreword-2..............................................................................................................................................xi
Acknowledgement..................................................................................................................................xiii
1. Boolean Algebra and Logic Design: An Overview..........................................................1.1—1.45
1.1 Introduction...........................................................................................................................1.1
1.2 Truth Table............................................................................................................................1.1
1.3 Basic Logic Gates.................................................................................................................1.3
1.3.1 AND Gate................................................................................................................1.3
1.3.2 OR Gate...................................................................................................................1.3
1.3.3 NAND Gate.............................................................................................................1.3
1.3.4 NOR Gate................................................................................................................1.4
1.3.5 Buffer.......................................................................................................................1.4
1.3.6 Inverting Buffer.......................................................................................................1.4
1.3.7 Exclusive OR Gate..................................................................................................1.5
1.3.8 Exclusive NOR Gate...............................................................................................1.5
1.3.9 Tri-state Gate...........................................................................................................1.5
1.4 Boolean function Minimization............................................................................................1.6
1.4.1 Theorems.................................................................................................................1.6
1.4.2 Karanugh Map.........................................................................................................1.8
1.4.2.1 Boolean Algebra Expression Minimization by Karanugh Map.............1.8
1.4.2.2 Minimization Rules................................................................................1.9
1.4.2.3 Summmary...........................................................................................1.11
1.4.2.4 Don’t cares...........................................................................................1.12
1.4.2.5 Design Example Race hazards.............................................................1.12
1.4.2.6 Some Examples....................................................................................1.12
Contents

1.4.3 Elimination of Race Hazards.................................................................................1.15
1.4.4 Quine-McCluskey Algorithm................................................................................1.16
1.4.4.1 Example...............................................................................................1.16
1.4.4.2 Alternate Method.................................................................................1.19
1.4.5 Logic Circuits........................................................................................................1.22
1.4.5.1 Combinational Circuits........................................................................1.22
1.4.5.2 Examples of Combinational Circuits...................................................1.22
1.4.5.3 Half Adder............................................................................................1.23
1.4.5.4 Full Adder............................................................................................1.23
1.4.5.5 2 to 4 Line Decoder..............................................................................1.24
1.4.5.6 4 to 1 Multiplexer.................................................................................1.25
1.4.5.7 BCD to Excess-3 Code Converter BCD Input Excess-3 Output
Decimal................................................................................................1.26
1.4.5.8 Programmable Logic Devices are Discussed in Chapter 2..................1.28
1.4.5.9 An Example of a Combinational Circuit Design.................................1.28
1.4.6 Sequential Circuits.................................................................................................1.29
1.4.6.1 Examples..............................................................................................1.29
1.4.7 Sequential Circuit Design......................................................................................1.35
1.4.7.1 Sequential Circuit Design Example.....................................................1.35
1.4.8 State Machine........................................................................................................1.37
1.4.8.1 An Example of a State Machine is the Digital Computer....................1.38
1.4.8.2 Design Example 1................................................................................1.38
1.4.8.3 Design Example 2................................................................................1.41
1.5 Summary.............................................................................................................................1.44
2. Programmable Logic Devices (PLDs)..............................................................................2.1—2.31
2.1 Introduction...........................................................................................................................2.1
2.2 SPLDs .................................................................................................................................2.2
2.2.1
A Commercial PAL 22V10 is shown in Fig. 2.4. Programming this Chip is Ex-
plained Later............................................................................................................2.5
2.3 Complex Programmable Logic Devices (CPLD).................................................................2.5
2.3.1 Comparison of SPLD and CPLD ...........................................................................2.7
2.3.2 Some Commercial PLDs.........................................................................................2.7
2.3.3 Design Methodologies for PLDs.............................................................................2.9
2.3.3.1 Steps involved in manual programming................................................2.9
2.3.3.2
Steps Involved in Designing with SPLDs Using CAD Tools are
Shown in Fig 2.8.................................................................................2.13
2.4 Field Programmable Gate Array (FPGA)...........................................................................2.16
2.4.1 XILINX FPGAS In the beginning.........................................................................2.18
2.4.2 Advanced FPGAs..................................................................................................2.18
xviii Contents

2.4.3 Spartan Family.......................................................................................................2.20
2.4.4 Designing with Xilinx FPGAs...............................................................................2.20
2.4.5 Applications of FPGAs..........................................................................................2.21
2.5 Microcontrollers.................................................................................................................2.22
2.6 Application Specific Integrated Circuit (ASIC).................................................................2.24
2.6.1 Full-Custom ASIC.................................................................................................2.25
2.6.2 Standard Cell ASIC...............................................................................................2.25
2.6.3 Gate Array ASIC....................................................................................................2.25
2.6.4 Generalised ASIC Design Flow Steps...................................................................2.25
2.6.5 ASIC Design Flow................................................................................................2.26
2.7 Comparisons.......................................................................................................................2.26
2.7.1 Comparison of Microcontrollers vs FPGA............................................................2.26
2.7.2 Comparison of FPGA vs ASIC..............................................................................2.28
2.8 Current Status.....................................................................................................................2.28
2.9 Conclusions.........................................................................................................................2.28
3. Xilinx FPGAs.....................................................................................................................3.1—3.43
3.1 Introduction...........................................................................................................................3.1
3.1.1 Look-up Table (LUT)..............................................................................................3.2
3.1.2 Slice.........................................................................................................................3.2
3.1.3 Fast Carry Logic......................................................................................................3.3
3.1.4 Multiplier Unit.........................................................................................................3.5
3.1.5 Shift Register...........................................................................................................3.5
3.2 Configurable Logic Block (CLB).........................................................................................3.6
3.3 Interconnect and Routing .....................................................................................................3.7
3.3.1 Direct Connections..................................................................................................3.9
3.3.2 Single-Length Lines................................................................................................3.9
3.3.3 Double-Length Lines.............................................................................................3.10
3.3.4 Long Lines.............................................................................................................3.10
3.3.5 Global lines............................................................................................................3.10
3.4 IOB-INPUT.OUTPUT BLOCK.........................................................................................3.10
3.4.1 Pull-up and Pull-down Resistors...........................................................................3.12
3.4.2 Digitally Controlled Impedance............................................................................3.12
3.5 Further advances in FPGAs................................................................................................3.13
3.6 Virtex Architecture..............................................................................................................3.13
3.6.1 Main features of Virtex .........................................................................................3.14
3.6.2 Block RAM...........................................................................................................3.14
3.6.3 Delay-Locked Loop (DLL)...................................................................................3.15
Contents xix

3.7 Virtex-II..............................................................................................................................3.18
3.7.1 Digital Clock Manager (DCM).............................................................................3.19
3.8 Virtex-II Pro........................................................................................................................3.20
3.8.1 Main Features of Virtex-II Pro..............................................................................3.20
3.8.2 Rocket IO Transceiver Features............................................................................3.21
3.8.3 Processors in Xilinx FPGA....................................................................................3.21
3.8.3.1 Hard Core Processor IBM POWER PC 405........................................3.21
3.8.3.2 A Power PC based embedded system..................................................3.22
3.8.4 Soft Core Processor MICROBLAZE....................................................................3.23
3.8.4.1 An Embedded System Using Microblaze and Power PC....................3.24
3.9 Virtex-4...............................................................................................................................3.25
3.9.1 Sub Families..........................................................................................................3.26
3.10 Virtex-5...............................................................................................................................3.27
3.11 Virtex-6...............................................................................................................................3.29
3.11.1 Virtex-6 sub-families.............................................................................................3.31
3.12 Virtex-7...............................................................................................................................3.31
3.13 Spartan Family....................................................................................................................3.34
3.13.1 Spartan-3................................................................................................................3.34
3.13.2 Spartan-6................................................................................................................3.35
3.14 Boundary Scan....................................................................................................................3.40
3.15 FPGA Design flow..............................................................................................................3.40
3.16 FPGA vs ASIC....................................................................................................................3.41
3.17 Conclusions.........................................................................................................................3.43
4. Altera FPGAs.....................................................................................................................4.1—4.23
4.1 Introduction...........................................................................................................................4.1
4.2 New Application, New Techniques......................................................................................4.3
4.3 Enter the Processors, and The Great Crash...........................................................................4.4
4.4 Trends in IP...........................................................................................................................4.6
4.5 Stratix FPGA.........................................................................................................................4.8
4.6 Cyclone FPGAs....................................................................................................................4.9
4.7 Arria FPGA.........................................................................................................................4.15
4.8 An Evolving Methodology.................................................................................................4.17
4.9 The CPU-Centric Phase......................................................................................................4.18
4.10 Core and Multicore.............................................................................................................4.19
4.11 Consensus and Hardening...................................................................................................4.21
4.12 Conclusions.........................................................................................................................4.23
5. Microsemi FPGAs..............................................................................................................5.1—5.41
5.1 Introduction...........................................................................................................................5.1
xx Contents

5.2 Technologies.........................................................................................................................5.2
5.3 The Antifuse/Flash Advantage over SRAM based FPGAs..................................................5.2
5.3.1 Lower-Total-Cost-of-Ownership............................................................................5.2
5.3.2 Instant-on ...............................................................................................................5.3
5.3.3 Low-Power..............................................................................................................5.5
5.3.4 Reliability ...............................................................................................................5.5
5.4 FPGA Security......................................................................................................................5.5
5.4.1 Design Security.......................................................................................................5.5
5.4.2 Data Security...........................................................................................................5.6
5.5 Faster Time-to-Market..........................................................................................................5.7
5.6 Antifuse FPGAs of Microsemi.............................................................................................5.7
5.6.1 SX-A/SX Architecture is shown in Fig. 5.3............................................................5.8
5.6.2 MX FPGAs..............................................................................................................5.9
5.7 ProASIC3 FPGA Overview ...............................................................................................5.10
5.7.1 The ProASIC3 series ............................................................................................5.11
5.8 Third-Generation(ProASIC3) FPGAArchitecture (Fig. 5.7).............................................5.12
5.9 IGLOO Low Power FPGA Family.....................................................................................5.13
5.10 IGLOO FPGA Family Overview .......................................................................................5.14
5.11 Flash*Freeze Technology...................................................................................................5.15
5.12 Small Footprint Packages...................................................................................................5.15
5.13 SmartFusion2 SoC FPGA...................................................................................................5.15
5.14 Reliability...........................................................................................................................5.17
5.15 Highest Security Devices....................................................................................................5.17
5.16 Design Security...................................................................................................................5.17
5.17 Data Security......................................................................................................................5.18
5.18 Low Power..........................................................................................................................5.19
5.19 High-Performance FPGA Fabric........................................................................................5.19
5.20 Dual-Port Large SRAM (LSRAM)....................................................................................5.19
5.21 Three-Port Micro SRAM (uSRAM)...................................................................................5.19
5.22 Mathblocks for DSP Applications......................................................................................5.20
5.23 Microcontroller Subsystem (MSS).....................................................................................5.20
5.23.1 ARM Cortex-M3 Processor...................................................................................5.20
5.23.2 Cache Controller....................................................................................................5.20
5.23.3 DDR Bridge...........................................................................................................5.21
5.23.4 AHB Bus Matrix (ABM).......................................................................................5.21
5.23.5 System Registers...................................................................................................5.21
5.23.6 Fabric Interface Controller (FIC)..........................................................................5.21
5.23.7 Embedded SRAM (eSRAM).................................................................................5.22
5.23.8 Embedded NVM (eNVM).....................................................................................5.22
Contents xxi

5.23.9 DMA Engines........................................................................................................5.22
5.23.10 APB Configuration Bus.........................................................................................5.22
5.23.11 Peripherals.............................................................................................................5.22
5.24 Clock Sources: On-Chip Oscillators, PLLs, and CCCs......................................................5.24
5.25 High Speed Serial Interfaces..............................................................................................5.25
5.26 High Speed Memory Interfaces: DDRx Memory Controllers............................................5.25
5.27 MDDR Subsystem.............................................................................................................5.26
5.28 FDDR Subsystem .............................................................................................................5.26
5.29 IGLOO2 FPGAs .............................................................................................................5.26
5.29.1 High-Performance FPGA Fabric...........................................................................5.27
5.29.2 Dual-Port Large SRAM (LSRAM).......................................................................5.28
5.29.3 Three-Port Micro SRAM (uSRAM)......................................................................5.28
5.29.4 Mathblocks for DSP Applications.........................................................................5.28
5.29.5 High-Performance Memory Subsystem (HPMS)..................................................5.28
5.29.6 DDR Bridge...........................................................................................................5.29
5.29.7 AHB Bus Matrix (ABM).......................................................................................5.29
5.29.8 Fabric Interface Controller (FIC)..........................................................................5.29
5.29.9 Embedded SRAM (eSRAM).................................................................................5.29
5.29.10 Embedded NVM (eNVM).....................................................................................5.30
5.29.11 DMA Engines........................................................................................................5.30
5.29.12 APB Configuration Bus.........................................................................................5.30
5.29.13 Peripherals.............................................................................................................5.30
5.30 Clock Sources: On-Chip Oscillators, PLLs, and CCCs......................................................5.30
5.31 High Speed Serial Interfaces..............................................................................................5.31
5.32 High Speed Memory Interfaces: DDRx Memory Controllers............................................5.32
5.33 MDDR Subsystem.............................................................................................................5.32
5.34 FDDR Subsystem .............................................................................................................5.32
5.35 Software Development Tools..............................................................................................5.33
5.35.1 LiberoSoC..............................................................................................................5.33
5.35.2 Libero IDE ............................................................................................................5.35
5.36 Programming and Debugging.............................................................................................5.37
5.36.1. FlashPro Hardware Programmer............................................................................5.37
5.36.2 FlashPro5 .............................................................................................................5.38
5.36.3 FlashPro4 .............................................................................................................5.39
5.36.4 FlashProLite..........................................................................................................5.39
5.37 Evaluation and Development Kits.......................................................................................5.40
5.37.1 SmartFusion2 Security Evaluation Kit..................................................................5.40
xxii Contents

6. Hardware Description Languages (Verilog and VHDL)................................................6.1—6.39
6.1 Introduction...........................................................................................................................6.1
6.2 Verilog HDL.........................................................................................................................6.1
6.2.1 Terminology and Basic Concepts of Verilog...........................................................6.2
6.3 Examples of Hardware Modeling in Verilog......................................................................6.10
6.4 VHDL.................................................................................................................................6.19
6.5 Examples of Hardware Modeling in VHDL.......................................................................6.25
6.6 System Verilog....................................................................................................................6.37
6.7 Summary.............................................................................................................................6.38
7. FPGA Design Flow.............................................................................................................7.1—7.26
7.1 Introduction...........................................................................................................................7.1
7.2 Architecture Specification....................................................................................................7.1
7.2.1 Requirement Gathering...........................................................................................7.2
7.2.2 Data Flow Specification..........................................................................................7.2
7.2.3 Control Flow Specification......................................................................................7.4
7.2.4 Clocking and Reset Specification............................................................................7.4
7.2.5 Performance Specification.......................................................................................7.5
7.3 Behavioral Simulation..........................................................................................................7.5
7.3.1 Simulation using C based simulator........................................................................7.6
7.3.2 Simulation using MATLAB....................................................................................7.6
7.4 RTL Coding .........................................................................................................................7.7
7.4.1 RTL Coding Considerations....................................................................................7.7
7.4.1.1 Clock Considerations.............................................................................7.7
7.4.1.2 Reset Considerations..............................................................................7.8
7.4.1.3 RTL Design Considerations...................................................................7.8
7.4.2 Use of pre-verified IP..............................................................................................7.9
7.4.3 Use of High Level Synthesis ................................................................................7.10
7.5 Functional Simulation.........................................................................................................7.12
7.5.1 RTL Simulation with Directed Tests.....................................................................7.13
7.5.2 RTL Verification with Constraint Random Test....................................................7.13
7.6 Synthesis.............................................................................................................................7.14
7.6.1 User Constraint Specification.............................................................................................7.15
7.6.2 Synthesis Strategy.................................................................................................7.15
7.7 Implementation...................................................................................................................7.16
7.7.1 Design Optimization..............................................................................................7.17
7.7.2 Technology Mapping.............................................................................................7.17
7.7.3 Place and Route.....................................................................................................7.17
7.8 Static Timing Analysis........................................................................................................7.17
7.8.1 Definition of Setup and Hold Time.......................................................................7.17
Contents xxiii

7.8.2 Static Timing Report Analysis...............................................................................7.18
7.8.3 Handling Static Timing Violation in the Design...................................................7.19
7.9 Post Route Timing Simulation............................................................................................7.19
7.9.1 Running Post Route Timing Simulation................................................................7.20
7.9.2 Handling Post Route Timing Failures...................................................................7.20
7.10 Power Estimation................................................................................................................7.20
7.10.1 Static Power Analysis............................................................................................7.22
7.10.2 Dynamic Power Analysis......................................................................................7.22
7.11 Device Configuration..........................................................................................................7.22
7.11.1 Bitstream Generation.............................................................................................7.22
7.11.2 Device Programming.............................................................................................7.23
7.12 System Debugging .............................................................................................................7.24
7.12.1 FPGA Debug Interfaces.........................................................................................7.24
7.12.2 Board Level Debugging........................................................................................7.24
7.12.3 RTL Design Debugging.........................................................................................7.24
8. Design Exercises.................................................................................................................8.1—8.83
8.1 Introduction...........................................................................................................................8.1
8.2 Design Exercise 1: Design of a 4 bit ALU...........................................................................8.1
8.2.1 Tools: Modelsim 6.4, Xilinx ISE v14.2...................................................................8.2
8.2.3 ALU Operations......................................................................................................8.2
8.2.4 ALU Block Diagram...............................................................................................8.3
8.2.5 ALU Operation Flow Chart.....................................................................................8.4
8.2.6 Verilog Code............................................................................................................8.5
8.2.7 Verilog Test Bench...................................................................................................8.6
8.2.8 Simulation Results...................................................................................................8.8
8.2.9 Synthesis Result.....................................................................................................8.13
8.2.10 Timing Summary...................................................................................................8.13
8.3 Background of Round Robin Algorithm.............................................................................8.14
8.3.1 Background of Round Robin Algorithm...............................................................8.14
8.3.2 Scope of Work.......................................................................................................8.14
8.3.3 Project Overview...................................................................................................8.14
8.3.3.1 Abstract................................................................................................8.14
8.3.4 Round Robin Arboter Specification.......................................................................8.15
8.3.5 Design of the Round Robin Arbiter Core..............................................................8.15
8.3.6 Top Design.............................................................................................................8.15
8.3.7 Pin Description......................................................................................................8.16
8.3.8 Top Design with Submodule.................................................................................8.17
8.3.9 Verilog Code..........................................................................................................8.18
8.3.10 Submodules...........................................................................................................8.19
8.3.10.1 Priority Logic.......................................................................................8.19
xxiv Contents

8.3.11 Verilog Code .........................................................................................................8.20
8.3.11.1 Verilog Code Leaf_Level Priority Logic.............................................8.21
8.3.11.2 Verilog Code for Or_4:-.......................................................................8.23
8.3.12 Arbitration Edge Detector.....................................................................................8.23
8.3.13 Verilog Code..........................................................................................................8.24
8.3.16 Feedback Logic.....................................................................................................8.25
8.3.15 Verilog Code..........................................................................................................8.26
8.3.16 Output Logic..........................................................................................................8.26
8.3.17 Verilog Code .........................................................................................................8.27
8.3.18 FSM Approach for the Round Robin Arbiter........................................................8.28
8.3.19 FSM Verilog Code.................................................................................................8.29
8.3.20 Test Benches Codes for DUT and FSM................................................................8.35
8.3.20.1 Verilog Code Test Bench for Arbiter_FSM .........................................8.35
8.3.20.2 Verilog Code for DUT.........................................................................8.37
8.3.21 Simulation Result..................................................................................................8.39
8.3.22 Implementation Results.........................................................................................8.40
8.3.23 Device and Tool Details........................................................................................8.41
8.3.24 Process Properties .................................................................................................8.41
8.3.25 Resource utilization Summary..............................................................................8.41
8.3.26 Applications...........................................................................................................8.41
8.4 Design Exercise 3: Design and Implementation of Booth Multiplier................................8.42
8.4.1 Introduction...........................................................................................................8.42
8.4.2 Booth’s Multiplication Algorithm.........................................................................8.42
8.4.3 Description............................................................................................................8.43
8.4.4 Examples .............................................................................................................8.43
8.4.5 Design Details.......................................................................................................8.45
8.4.5.1 PIN Description Table..........................................................................8.45
8.4.6
BLOCK DIAGRAM: Block Diagram of Booths Multiplier is shown in
Fig 8.26..................................................................................................................8.46
8.4.7 Implementation......................................................................................................8.46
8.4.8 Verilog Code..........................................................................................................8.46
8.4.9 Test/Verification Plan.............................................................................................8.48
8.4.10 Test Bench.............................................................................................................8.50
8.4.11 Simulation Results.................................................................................................8.53
8.4.12 RTL Schematic......................................................................................................8.53
8.4.13 Technology Schematic...........................................................................................8.54
8.4.14 Device Utilization Summary.................................................................................8.54
8.4.15 Timing Summary...................................................................................................8.55
Contents xxv

8.5 Background.........................................................................................................................8.55
8.6 Specifications of Data Partitioning System........................................................................8.56
8.7 High Level Design (Macro-Architecture) of DAS.............................................................8.57
8.7.1 Pooler Card Macro-Architecture ..........................................................................8.58
8.7.2 Bridge Card Macro-Architecture (virtex-5 board)................................................8.59
8.7.3 The Bridge Card Micro-architecture.....................................................................8.61
8.7.3.1 Aurora Receiver IPs (Aurora_receiver_inst1/inst2)............................8.61
8.7.3.2
Frame Buffers (Frame_buffer_l1_pi1-pi8 Frame_buffer_l1_po1-
po8, Frame_buffer_l2_pi1-pi8 Frame_buffer_l2_po1-po8)............8.62
8.7.3.3 Frame Write Controllers (Frame_wr_cntlr1 Frame_wr_cntlr2)......8.62
8.7.3.4 Frame Read/Write Controller (Frame_rdwr_cntlr)..............................8.62
8.7.3.5 DDR2 Memory Controller...................................................................8.63
8.7.3.6 Burst Fetcher (brst_fschr)....................................................................8.63
8.7.3.7 Burst Fifo (brst_fifo)............................................................................8.64
8.7.3.8 Burst Fifo Read Controllers (brst_frd_cntlr1-brst_frd_cntlr4)............8.64
8.7.4 Test Bench Framework for Bridge Card................................................................8.65
8.7.5 Synthesis of Bridge Card ......................................................................................8.66
8.7.6 Conclusions...........................................................................................................8.81
9. Conclusions.........................................................................................................................9.1—9.10
9.1 Having seen SRAM based, Anti-fuse and Flash FPGAs, a comparison of these FPGAs
in the concluding chapter will be well in place....................................................................9.1
9.1.1 SRAM based FPGAs...............................................................................................9.1
9.1.2 Antifuse-Based FPGAs...........................................................................................9.2
9.1.3 E2PROM/Flash-Based FPGAs................................................................................9.3
9.1.4 Hybrid Flash-SRAM FPGAs...................................................................................9.3
9.2 FPGA Security......................................................................................................................9.4
9.2.1 Need for FPGA Security..........................................................................................9.4
9.2.2 Security Methods.....................................................................................................9.5
9.2.3 Modern FPGA Security...........................................................................................9.6
9.3 Future of FPGAs...................................................................................................................9.7
9.3.1 Advances in Microelectronics.................................................................................9.7
9.3.2 Architecture.............................................................................................................9.9
9.3.3 Design Tools..........................................................................................................9.10
xxvi Contents

1
Boolean Algebra and Logic Design:
An Overview
1.1 INTRODUCTION
All digital devices use binary number system. Binary number system will have two states
‘1’ and ‘0’. Active electronic components like transistors are used to represent these two
states. In one state say ‘1’, the transistor is not at all conducting and is in OFF state. To
represent the other state ‘0’ transistor will be fully conducting. These are two stable states
representing the binary digit called BIT. Boolean algebra, developed by George Boole in
the 1840s, is the logical calculus of truth tables and operates on elements that have one
of two values ‘1’ or ‘0’ Since this book deals with digital devices called programmable logic
devices using which Boolean functions will be implemented, it is appropriate to have a brief
overview of Boolean Algebra.
1.2 TRUTH TABLE
A truth table shows how a logic circuit’s output responds to various combinations of the
inputs, using logic 1 for true and logic 0 for false. All permutations of the inputs are listed
on the left, and the output of the circuit is listed on the right. The desired output can be
achieved by a combination of logic gates.
An example of a truth table for three input variables A, B, C is shown in Table 1.1
Since there are three binary variables there will be 23 = 8 input combinations. For certain
combinations of the input variables A, B, C the out is 0 and for other combinations the
output is 1.

1.2 Field Programmable Gate Arrays and Applications
Input Output
Table 1.1: Truth Table for 3 variables
A B C Z
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1
A minterm is a special product of literals, in which each input variable appears exactly
once. For example, in the above truth table the minterm A’ B’ C gives the output of ‘1’. A’ is
called complement of A so if A = 1, A’ will be 0 and if A = 0, A’ will be ‘1’,
A Boolean function can be expressed algebraically from a given truth table by forming
a minterm which is a product of literals for each combination of the variables that produces
a 1 in the function and then taking the OR (+) of all those terms. For the truth table 1, this
Boolean function is:
Z = A’B’C + A’BC’ + AB’C’ + ABC
This Boolean function formed out of minterms of the truth table is called SUM OF
PRODUCT TERM (SOP)
The above boolean function can also be written as:
Z = m1 + m2 + m4 + m7
Or
Z = S(m1, m2, m4, m7)
A maxterm is a sum of literals, in which each input variable appears exactly once. Each
maxterm is false for exactly one combination of inputs. A Boolean function can be expressed
algebraically from a given truth table by forming a maxterm for each combination of the
variables that produces a 0 in the function and then taking the AND (.) of all those terms.
For the truth table 1.1, it can be seen that it is 0 for rows 0,3,5,6. So
Z = M0· M3· M5· M6
= ( ) . ( ) . ( ) . ( )
A B C A B C A B C A B C
+ + + + + + + +
This form also lends itself to a compact notation: using the Greek letter capital pi to
denote a product, we write only the numbers of the maxterms included in:
Z = P(0,3,5,6)
The inverse of the function can be expressed as a product
(AND) of its 1-maxterms. It can be noted that in this case Z’ will be
Z’ = (A + B + C’) · (A’ + B + C) · (A’ + B + C’)
Z’ = P(1,2,4,7)

Boolean Algebra and Logic Design: An Overview 1.3
This Boolean function formed out of maxterms of the truth table is called PRODUCT
of SUM TERM (POS)
Boolean functions expressed as a sum of minterms or product of maxterms are said to
be in canonical form.
Boolean functions in canonical form can be implemented using basic logic gates.
1.3 BASIC LOGIC GATES
1.3.1 AND Gate
The output is high only when both inputs A and B are high.
The AND operation will be signified by AB or A * B other common mathematical
notations for it are A Ù B and A ∩ B, called the intersection of A and B.
1.3.2 OR Gate
The output is high when either or both of inputs A or B is high.
The OR operation will be signified by A + B other common mathematical notations for
it, are A Ú B and A ∪ B, called the union of A and B.
1.3.3 NAND Gate
The output is high when either of inputs A or B is high, or if neither is high. In other words,
it is normally high, going low only if both A and B is high.

1.3.4 NOR Gate
The output is high only when neither A nor B is high. That is, it is normally high but any
kind of non-zero input will take it low.
The NOR gate and the NAND gate can be said to be universal gates since combinations
of them can be used to accomplish any of the basic operations and can thus produce an
inverter, an OR gate or an AND gate. The non-inverting gates do not have this versatility
since they cannot produce an invert.
A B Out
0 0 1
0 1 0
1 0 0
1 1 0
NOR
A
B
A + B
1.3.5 Buffer
The buffer is a single-input device which has a gain of 1, mirroring the input at the output.
It has value for impedance matching and for isolation of the input and output and may
have more fan-out capacity.
In Out
0 0
1 1
In Out
1.3.6 Inverting Buffer
The inverting buffer is a single-input device which produces the state opposite the input.
If the input is high, the output is low and vice versa.
In Out
0 1
1 0
In Out
This device is commonly referred to as just an inverter.

1.3.7 Exclusive OR Gate
The output is high when either of inputs A or B is high, but not if both A and B are low or
high.
A B Out
0 0 0
0 1 1
1 0 1
1 1 0
XOR
A
B
A B

1.3.8 Exclusive NOR Gate
The output is high when both inputs A and B are low or high and low when neither A nor
B is high.
A B Out
0 0 1
0 1 0
1 0 0
1 1 1
XNOR
A
B
A B

1.3.9 Tri-state Gate
There is another gate called tri-state buffer. This is commonly used in Bus based systems.
x z
c
Tri-state buffer with
active high control
x z
c
Tri-state buffer with
active low control
Apart from input and output, this gate will have a control signal which can be active
HIGH or active LOW. When this control signal is not activated the gate allows the input to
output. That means X = Z. When the control signal is activated, it will not allow the input
signal to output but places the output in a High Impedance state.
If the Boolean functions in canonical form are implemented using the logic gates, it may
so happen that many logic gates may be required to realize the Boolean function. Since logic
gate is an electronic circuit, there will be some delay from input to reliable output. Reducing
the number of gates not only reduces the cost of implementation and also the delay from

inputs to outputs, Boolean functions can be minimized using various Boolean theorems.
This minimization will yield the same result with reduction in number of logic gates and
the delay from input to output.
1.4 BOOLEAN FUNCTION MINIMIZATION
Minimization theorems with proof and also some methods are discussed in the following
sections.
1.4.1 Theorems
Theorem 1: a + b = b + a, ab = ba (commutative)
Theorem 2 : a + bc = (a + b) (a + c) (distributive)
a(b + c) = ab + ac
Theorem 3: a + 0 = a, a1 = a (identity)
Theorem 4: a + a’ = 1, a a’ = 0 (complement)
Theorem 5 (Involution Laws):
For every element a in B, (a’)’ = a
Proof: a is one complement of a’.
The complement of a′ is unique
Thus a =(a′)′
Theorem 6: For every pair a,b in B, a· (a + b) = a; a + a· b = a.
Proof: a(a + b)
(Absorption Law):
= (a + 0) (a + b) (P1)
= a + ab + 0.a + 0·b (P2)
= a + ab + 0 + 0 (P3)
= a + ab (P4)
= a(1 + b) (P5)
= a (p6)
Theorem 7: For every pair a, b in B
a + a’ × b =a + b; a × (a’ + b) = a × b
Proof: a + a’ × b
= (a + a’) × (a + b) (P1)
= (1) × (a + b) (P2)
= (a + b) (P3)
Theorem 8 (Demorgan’s Theorem):
For every pair a, b in set B:

(a + b)’ = a’b’, and (ab)’ = a’ + b’.
Proof: We show that a + b and a’b’ are complementary.
In other words, we show that both of the following are true (P1):
(a + b) + (a’ b’) = 1, (a + b) (a’ b’) = 0.
This Demorgan’s theorem can be proved using Truth Tables
A B A + B (A + B)’ A’B’
0 0 0 + 0 1 1
0 1 0 + 1 0 0
1 0 1 + 0 0 0
1 1 1 + 1 0 0
The above truth table proves the Demorgan theorem (A + B)’ = A’B’
A B (AB)’ A’ + B’
0 0 1 1
0 1 1 1
1 0 1 1
1 1 0 0
The above truth table proves the Demorgan theorem (AB)’ = A’ + B’
Theorem 9. Boolean Transformation
Show that a’b’ + ab + a’b = a’ + b
Proof 1: a’b’ + ab + a’b = a’b’ + (a + a’)b (P1)
= a’b’ + b (P2)
= a’ + b
Proof 2: a’b’ + ab + a’b
= a’b’ + ab + a’b + a’b
= a’b’ + a’b + ab + a’b (P1)
= a’(b’ + b) + (a + a’)b (P2)
= a’ × 1 +1 × b (P3)
= a’ + b (P4)
Theorem 10. Boolean Transformation
(a’b’ + c)(a + b) (b’ + ac)’
= (a’b’ + c) (a + b) (b(ac)’) (De Morgan’s)
= (a’b’ + c) (a + b) b(a’ + c’) (DeMorgan’s)
= (a’b’ + c)b (a’ + c’) (Absorption)
= (a’b’b + bc) (a’ + c’) (P1)

= (0 + bc) (a’ + c’) (P2)
= bc(a’ + c’) (P3)

= a’bc + bcc’ (P4)
= a’bc + 0 (P5)
= a’bc (P6)
1.4.2 Karanugh Map
The Karnaugh map, also known as the K-map, is a method of simplifying Boolean algebra
expressions. This K-Map was introduced by Maurice Karnaugh as an improvement over
the Veitch Diagram method suggested by Edward Veitch in 1952. The Karnaugh map
reduces the need for extensive calculations by taking advantage of humans’ pattern-
recognition capability. It also permits the rapid identification and elimination of potential
race conditions.
The required Boolean results are transferred from a truth table onto a two-dimensional
grid where the cells are ordered in Gray Code and each cell position represents one
combination of input conditions, while each cell value represents the corresponding output
value. Optimal groups of 1s or 0s are identified, which represent the terms of a canonical
form of the logic in the original truth table. These terms can be used to write a minimal
Boolean expression representing the required logic.
Karnaugh maps are used to simplify real-world logic requirements so that they can be
implemented using a minimum number of physical logic gates. A Sum of Products (SOP)
can always be implemented using Logic AND and OR gates. AND gates feeding into an OR
gate and a Product of SUM (POS) expression uses OR gates feeding an AND gate.
1.4.2.1 Boolean Algebra Expression Minimization by Karanugh Map
If there are two input variables, there will be four combinations. Karanugh map will be
arranged in a 2 × 2grid with two rows and two columns. For three input variables there will
be eight combinations and Karanugh map grid will be 2 × 4 with 2 rows and 4 columns or
4 rows and 2 columns. For four input variables, because of 16 combinations, the Karanugh
map will be organized as 4 × 4 grid with four rows and four columns as shown in Fig..1.1.
2 variables:
A
B
0
1
0 1
3 variables:
A
BC
0
1
00 01 11 10

4 variables:
AB
CD
00
01
11
10
00 01 11 10
Fig. 1.1 Karanugh Maps for two, three and four variables.
The row and column values are shown across the top, and down the left side of the
Karnaugh map and they are ordered in Gray Code rather than binary numerical order.
Gray code ensures that only one variable changes between each pair of adjacent cells. Each
cell of the completed Karnaugh map contains a binary digit representing the function’s
output for that combination of inputs.
After the Karnaugh map has been constructed it is used to find one of the simplest
possible forms—a canonical form—for the information in the truth table. Adjacent 1s in the
Karnaugh map represent opportunities to simplify the expression. The minterms (‘minimal
terms’) for the final expression are found by encircling groups of 1s in the map. Minterm
groups must be rectangular and must have an area that is a power of two (i.e., 1, 2, 4, 8…).
Minterm rectangles should be as large as possible without containing any 0s. Groups may
overlap in order to make each one larger. The grid is toroidally connected, which means
that rectangular groups can wrap across the edges. Cells on the extreme right are actually
‘adjacent’ to those on the far left; similarly, so are those at the very top and those at the
bottom.
1.4.2.2 Minimization Rules
The Karnaugh map uses the following rules for the simplification of expressions by
grouping together adjacent cells containing ones. Examples of correct grouping and wrong
grouping are illustrated in Fig. 1.2
● Groups may not include any cell containing a zero.
B
A 0 1
0
1
0
1
Wrong X
B
A 0 1
0
1 1
Right ✓
✓
1
X

● Groups may be horizontal or vertical, but not diagonal.
B
A 0 1
0
1
0 1
Wrong X
1 0
X
B
A 0 1
0
1
0
1
Right ✓
1
1
✓
● Groups must contain 1, 2, 4, 8, or in general 2n cells.

That is if n = 1, a group will contain two 1’s since 21 = 2.
If n = 2, a group will contain four 1’s since 22 = 4.
B
A 0 1
0
1
1
0
Right ✓
1
0
✓
Group of 2 C
AB 00 01
0
1
0
0
Wrong X
1
0
Group of 3
11 10
1 1
0 0
X
B
A 0 1
0
1
1
1
Right ✓
1
1
Group of 4 C
AB 00 01
0
1
1
0
Wrong X
1
0
Group of 5
11 10
1 1
0 1
X
● Each group should be as large as possible.
C
AB 00 01
0
1
1
0
Wrong X
1
0
11 10
1 1
0 1
X
C
AB 00 01
0
1
1
0
Right ✓
1
0
11 10
1 1
1 1
✓
● Each cell containing a one must be in at least one group.
C
AB 00 01
0
1
0
0
0
0
11 10
1 1
0 1
Group I
Group II
I present in at least one group.

● Groups may overlap.
C
AB 00 01
0
1
1
0
1
0
11 10
1 1
1 1
Groups overlapping
Right ✓
✓
C
AB 00 01
0
1
1
0
1
0
11 10
1 1
1 1
Groups not overlapping
Wrong X
X
● Groups may wrap around the table. The leftmost cell in a row may be grouped with
the rightmost cell and the top cell in a column may be grouped with the bottom cell.
AB
C
Leftmost cell
Bottom cell
Rightmost cell
0
1 1
1 1 1
1
00 01 11 10
1
1
Top cell
● There should be as few groups as possible, as long as this does not contradict any
of the previous rules.
Fig. 1.2 Examples of correct grouping and wrong grouping in Kanranugh Maps.
1.4.2.3 Summmary
1. No zeros allowed.
2. No diagonals.
3. Only power of 2 numbers of cells in each group.
4. Groups should be as large as possible.

5. Every one must be in at least one group.
6. Overlapping allowed.
7. Wrap around allowed.
8. Fewest number of groups possible.
Courtesy: http://www.ee.surrey.ac.uk/Projects/Labview/minimisation/karrules.html
1.4.2.4 Don’t cares
Karnaugh maps also allow easy minimizations of functions whose truth tables include
‘Don’t care’ conditions. A ‘‘don’t care’’ condition is a combination of inputs for which the
designer doesn’t care what the output is. Therefore ‘‘don’t care’’ conditions can either be
included in or excluded from any circled group, whichever makes it larger. They are usually
indicated on the map with a dash or X.
1.4.2.5 Design Example Race hazards
Karnaugh maps are useful for detecting and eliminating race hazards. Race hazards are
very easy to spot using a Karnaugh map, because a race condition may exist when moving
between any pair of adjacent, but disjointed, regions circled on the map.
1.4.2.6 Some Examples
Example 1
F = x’yz’ + x’yz + xy’z’ + xy’z + xyz

Example 2. Use a K-Map to simplify the following Boolean expression F(a, b, c) = Σm (2,
3, 6, 7).
Perform three variable KMAP for the above Boolean equation which is F = a’bc’ + a’bc
+abc’ + abc
Step 1: Plot the K-map
1 1
1 1
00 01 11 10
C
AB
0
1
Step 2: Circle Prime Implicants
1 1
1 1
00 01 11 10
C
AB
0
1
F(a, b, c) = Σm (2, 3, 6, 7)
Solution:
F(a, b, c) = b
Example 3. Use a K-Map to simplify the following Boolean expression
F(a, b, c, d) = Σm (0, 2, 3, 6, 8, 12, 13, 15)
Draw the K-Map
00 01 11 10
1 1 1
1
1
1
1
1
00
01
11
10
CD
AB

Solution.
F = a b d a b c abd ac d
′ ′ ′ + ′ ′ + + ′ ′
Now we show an example using don’t care terms
Example 4. Use a K-Map to simplify the following Boolean expression
F(a, b, c, d) = Sm (0, 2, 6, 8, 12, 13, 15) + d(3, 9, 10)
D = Don’t care (i.e. either 1 or 0)
Draw the K-Map
00 01 11 10
1 1 1
1
1
1
1
d
00
01
11
10
CD
AB
d
d
F (a, b, c, d) = Σm (0, 2, 6, 8, 12, 13, 15) + d(3, 4, 9)
F = a d ac abd
′ ′ + ′ +
Example 5. Given the Boolean function Z = A’B’C’D’ + A’BC’D’ + ABC’D’ + AB’C’D’ +
A’BC’D + ABC’D + A’B’CD’ + AB’CD’. Minimize the function using K Map
Solution.
00 01 11 10
1 1 1
1
1
00
01
11
10
CD
AB
1
1
1
Z = + BC’ + B’D’

1.4.3 Elimination of Race Hazards
As mentioned earlier Karnaugh maps are useful for detecting and eliminating race hazards.
Race hazards are very easy to spot using a Karnaugh map, because a race condition may
exist when moving between any pair of adjacent, but disjointed, regions circled on the map.
Consider the example:
f(A, B, C, D) = Σm (6, 8, 9, 10, 11, 12, 13, 14)
Karnaugh Map for this Boolean equation is shown in Fig. 1.3.
●
In the example, a potential race condition exists when C is 1 and D is 0, A is 1,
and B changes from 1 to 0 (moving from the blue state to the green state (Fig. 1.3).
For this case, the output is defined to remain unchanged at 1, but because this
transition is not covered by a specific term in the equation, a potential for a glitch
(a momentary transition of the output to 0) exists.
● There is a second potential glitch in the same example that is more difficult to spot:
when D is 0 and A and B are both 1, with C changing from 1 to 0 (moving from the
blue state to the red state). In this case the glitch wraps around from the top of the
map to the bottom.
00 01 11 10
0 0 1 1
1 1
0 0
0 0
0 1 1 1
0 1
AB
CD
10
11
01
00
Fig. 1.3 Karnaugh Map for Race hazard example.
Above k-map (Fig. 1.3) with the AD term added to avoid race hazards.
Whether these glitches will actually occur depends on the physical nature of the
implementation, and whether we need to worry about it depends on the application.
In this case, an additional term of AD would eliminate the potential race hazard

The term is redundant in terms of the static logic of the system, but such redundant, or
consensuses terms are often needed to assure race-free dynamic performance.
Courtesy:
https://www.google.co.in/search?hl=enINsource= hpq=karnaugh+map+tutorial+pptg
bv= 2oq= karngs_l=heirloomhp.1.0.35i39j0i20l2j0l7.2937.6703.0.11297.4.4.0.0.0.0.610.
1485.22j1j0j1.4.0....0...1ac.1.34.heirloom-hp..0.4.1485.GwfNqIIdJig
Karnaugh map could be used for more than four variables.
1.4.4 Quine-McCluskey Algorithm
The Quine-McCluskey algorithm (or the method of prime implicants) is a method
used for minimization of Boolean functions which was developed by W.V.Quine and
Edward J. McCluskey in 1956. It is functionally identical to Karnaugh mapping, but the
tabular form makes it more efficient for use in computer algorithms, and it also gives a
deterministic way to check that the minimal form of a Boolean function has been reached.
It is sometimes referred to as the tabulation method.
The method involves two steps:
1. Finding all prime implicants of the function.
2. Use those prime implicants in a prime implicant chart to find the essential prime
implicants of the function, as well as other prime implicants that are necessary to
cover the function.
Although more practical than Karnaugh mapping when dealing with more than four
variables, the Quine-McCluskey algorithm also has a limited range of use since the problem
it solves is NP-hard: the runtime of the Quine-McCluskey algorithm grows exponentially
with the number of variables. It can be shown that for a function of n variables the upper
bound on the number of prime implicants is 3n/n. If n = 32 there may be over 6.5 ∗ 1015
prime implicants. Functions with a large number of variables have to be minimized with
potentially non-optimal heuristic methods, of which the Espresso heuristic logic minimize
is the de facto standard.
1.4.4.1 Example
Step 1: finding prime implicants
Minimizing an arbitrary function:
f(A, B, C, D) = S(m (4, 8, 10, 11, 12, 15) + d(9, 14)
This expression says that the output function f will be 1 for the minterms 4, 8, 10, 11,
12 and 15 (denoted by the ‘m’ term). But it also says that we don’t care about the output for
9 and 14 combinations (denoted by the ‘d’ term). (‘x’ stands for don’t care).
A B C D f
m0 0 0 0 0 0
m1 0 0 0 1 0
m2 0 0 1 0 0

m3 0 0 1 1 0
m4 0 1 0 0 1
m5 0 1 0 1 0
m6 0 1 1 0 0
m7 0 1 1 1 0
m8 1 0 0 0 1
m9 1 0 0 1 x
m10 1 0 1 0 1
m11 1 0 1 1 1
m12 1 1 0 0 1
m13 1 1 0 1 0
m14 1 1 1 0 x
m15 1 1 1 1 1
One can easily form the canonical sum of products expression from this table, simply by
summing the minterms (leaving out don’t-care terms) where the function evaluates to one:
fA,B,C,D = A’BC’D’ + AB’C’D’ + AB’CD’ + AB’CD + ABC’D’ + ABCD
which is not minimal. So to optimize, all minterms that evaluate to one are first placed in
a minterm table. Don’t-care terms are also added into this table, so they can be combined
with minterms:
Number of 1s Minterm Binary Representation
1 m4 0100
m8 1000
2 m9 1001
m10 1010
m12 1100
3 m11 1011
m14 1110
4 m15 1111
At this point, one can start combining minterms with other minterms. If two terms vary
by only a single digit changing, that digit can be replaced with a dash indicating that the
digit doesn’t matter. Terms that can’t be combined any more are marked with a ‘‘∗’’. When
going from Size 2 to Size 4, treat ‘–’ as a third bit value. Ex: –110 and –100 or -11- can be
combined, but not -110 and 011-. (Trick: Match up the ‘–’ first.)

Number of
1s
Minterm 0-Cube Size 2
Implicants
Size 4 Implicants
1 m4 0100 m(4,12) -100* m(8,9,10,11) 10--*
m8 1000 m(8,9) 100- m(8,10,12,14) 1--0*
-- -- m(8,10) 10-0 --
-- -- m(8,12) 1-00 --
2 m9 1001 m(9,11) 10-1 m(10,11,14,15) 1-1-*
m10 1010 m(10,11) 101- --
m12 1100 m(10,14) 1-10 --
-- -- m(12,14) 11-0 --
3 m11 1011 m(11,15) 1-11 --
m14 1110 m(14,15) 111- --
4 m15 1111 -- --
Note: In this example, none of the terms in the size 4 implicants table can be combined
any further. Be aware that this processing should be continued otherwise (size 8 etc.).
Step 2: prime implicant chart
None of the terms can be combined any further than this, so at this point we construct
an essential prime implicant table. Along the side goes the prime implicants that have just
been generated, and along the top go the minterms specified earlier. The don’t care terms
are not placed on top - they are omitted from this section because they are not necessary
inputs.
4 8 10 11 12 15 ⇒ A B C D
m(4, 12)* X X ⇒ – 1 0 0
m(8, 9, 10, 11) X X X ⇒
m(8, 10, 12, 14) X X X ⇒
m(10, 11, 14, 15)* X X X ⇒ 1 – 1 –
To find the essential prime implicants, we run along the top row. We have to look for
columns with only 1 star. If a column has only 1 star, this means that the minterm can only
be covered by 1 prime implicant. This prime implicant is essential. For example: in the first
column, with minterm 4, there is only 1 star. This means that m(4, 12) is essential. So we
place a star next to it. Minterm 15 also only has 1 star. This means that m(10, 11, 14, 15)
is also essential. Now all columns with 1 star are covered.
The second prime implicant can be ‘covered’ by the third and fourth, and the third
prime implicant can be ‘covered’ by the second and first, and neither is thus essential. If a
prime implicant is essential then, as would be expected, it is necessary to include it in the
minimized boolean equation. In some cases, the essential prime implicants do not cover all

minterms, in which case additional procedures for chart reduction can be employed. The
simplest ‘‘additional procedure’’ is trial and error, but a more systematic way is Petrick’s
Method. In the current example, the essential prime implicants do not handle all of the
minterms, so, in this case, one can combine the essential implicants with one of the two
non-essential ones to yield one equation:
fA,B,C,D = BC’D’ + AB’ + AC
Both of those final equations are functionally equivalent to the original, verbose
equation
fA,B,C,D = A’BCD’ + AB’C’D + AB’C’D + AB’CD’ + AB’CD
+ ABC’D’ + ABCD’ + ABCD
Courtesy:
http://en.wikipedia.org/wiki/Quine%E2%80%93McCluskey_algorithm
As an exercise, the same Boolean equation
fA,B,C,D = Σm (4, 8, 10, 11, 12, 15) + d(9, 14).
Will be subjected to minimization using Karnaugh method. The Karanugh map is
shown in Fig. 1.4
F(A, B, C, D) = BC’D’ + AC + AB’
Fig. 1.4 Karnaugh Map for the Boolean function
f(A, B, C, D) = Σm(4, 8, 10, 11, 12, 15) + d(9, 14).
The same result that is obtained using Quine McClusky method.
1.4.4.2 Alternate Method
Now an alternate solution for the same equation is tried using Quine McClusky method.
f(A, B, C, D) = Σm(4, 8, 10, 11, 12, 15) + d(9, 14).

Table 1
0 1 0 0
1 0 0 0
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1 0 0 1
1 0 1 0
1 1 0 0
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1 0 1 1
1 1 1 0
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1 1 1 1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2
1 0 – – P2
1 0 – –
1 – – 0 P3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1 – – 9 P3
1 – 1 –
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1 – 1 – P4
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3
0 1 0 0 P1
1 0 – – P2
1 – – 0 P3
1 – 1 – P4
The PI are
P1 = A’BC’D’
P2 = AB’
P3 = AD’’
P4 = AC

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by the presence of his son’s widow and her seven children. Owen
delighted in the country. He had a genuine love for outdoor natural
history, and ‘the sight of the deer and other animals in the park, the
birds and insects in the garden, the trees, flowers, and varying
aspects of the sky, filled him with enthusiastic admiration.’ He died,
literally of old age, on Sunday, 18 January, 1892.
It is much to be regretted that one who worked at his own
subjects with such untiring zeal should have left behind him almost
nothing to perpetuate his name with the great mass of the people.
Mr Huxley remarks that, ‘whether we consider the quantity or the
quality of the work done, or the wide range of his labours, I doubt if,
in the long annals of anatomy, more is to be placed to the credit of
any single worker’ (ii. 306); but he presently adds this caution:
‘Obvious as are the merits of Owen’s anatomical work to every
expert, it is necessary to be an expert to discern them’ (ii. 332). He
gave popular lectures, but they were not printed[123]
; he wrote what
he intended to be a work for all time, but it has faded out of
recollection, and the whole theory of the archetype is now as dead
as his own Dinornis. Nor was he at pains to surround himself with a
circle of pupils who might have handed down the teaching of the
Master to another generation, as Cuvier’s teaching was handed
down by his pupils. It was one of Owen’s defects that he was
repellent to younger men. In a word, he was secretive, impatient of
interference, and preferred to be aut Cæsar aut nullus. Credit was to
him worth nothing if it was to be divided. Again, brilliant as were his
talents and assured as was his position, he could not recognize the
truth that men may sometimes err, and that the greatest gain rather
than lose by admitting it. During the whole of his long life we believe
that he never owned to a mistake. Not only was what he said law,
but what others ventured to say—especially if it ‘came between the
wind and his nobility’—was to be brushed aside as of no moment.
We believe that this feeling on his part explains his refusal to accept
the Darwinian theory. As we have shown, he went half way with it,
and then dropped it, because it had not been hammered on his own
anvil. This unfortunate antagonism to other workers, coupled with
his readiness to enter into controversy, and the acrimony and

dexterity with which he handled his adversaries, naturally
discouraged those who would otherwise have been only too happy
to sit at the feet of the Nestor of English zoology; and during the last
thirty years of his life he became gradually more and more isolated.
Moreover, there was, or there was thought to be, a certain want of
sincerity about him which no amount of external courtesy could
wholly conceal. In a word, he was compact of strange
contradictions. He had many noble qualities; and yet he could not
truly be called great, for they were warped and overshadowed by
many moral perversities. Had he lived in the previous century his
portrait might have been sketched by Pope:
‘But were there one whose fires
True genius kindles and fair fame inspires;
Blest with each talent and each art to please,
And born to write, converse, and live with ease;
Should such a man, too fond to rule alone,
Bear, like the Turk, no brother near the throne,
View him with scornful yet with jealous eyes,
And hate for arts that caused himself to rise;
* * * * * * *
Like Cato, give his little senate laws,
And sit attentive to his own applause;
While wits and templars every sentence raise,
And wonder with a foolish face of praise—
Who but must laugh, if such a man there be?
Who would not weep, if Atticus were he!’

CAMBRIDGE: PRINTED BY J. AND C. F. CLAY, AT THE UNIVERSITY PRESS.

Cambridge Described Illustrated. Being a Short History of
the Town and University. By Thomas Dinham Atkinson; with an
Introduction by John Willis Clark, M.A., F.S.A., Registrary of the
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ACADEMY.—“His book will be welcomed by all those who desire to
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London: Macmillan and Company, Limited.
Cambridge: Macmillan and Bowes.

A Concise Guide to the Town and University of Cambridge
in Four Walks. By John Willis Clark, M.A., F.S.A., Registrary of the
University, formerly Fellow of Trinity College. With Map and 75
Illustrations. Price 1s. net, or in limp cloth cover with pocket and
duplicate of the map, 2s. net.
TIMES.—“All intelligent visitors to Cambridge, however short their
stay, will be grateful to Mr. J. W. Clark, the Registrary of the
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of Cambridge in Four Walks. It is not often that the casual visitor to
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much condensed, but so far as it goes it is excellent.”
Libraries in the Medieval and Renaissance Periods. The
Rede Lecture, delivered June 13, 1894. By J. W. Clark, M.A.,
F.S.A. Crown 8vo. 2s. 6d. net.
Cambridge: Macmillan and Bowes.

Footnotes
1. 1. William Whewell, D.D., Master of Trinity College,
Cambridge. An Account of his Writings, with Selections
from his Literary and Scientific Correspondence. By I.
Todhunter, M.A., F.R.S., Honorary Fellow of S. John’s
College. 2 vols., 8vo. (London, 1876.)
2. The Life and Selections from the Correspondence of
William Whewell, D.D., late Master of Trinity College,
Cambridge. By Mrs Stair Douglas. 8vo. (London, 1881.)
2. In the fifteen years from 1800-1814 inclusive the
average was 205; from 1815-1829 it was 402; and from
1830-1844 it was 433; from 1845-1859 it was 444; from
1859-1874 it was 545.
3. Todhunter’s Life, ii. 91.
4. Life and Letters of Sir C. Lyell, ii. 38. In the same letter
he expresses his astonishment at finding that Whewell,
while writing one of his papers on the Tides, was passing
through the press four other works.
5. The inscription runs: munificentia · fultus · Alex. J. B.
Hope, generosi · hisce · ædibus · antiquam · speciem ·
restituit. W. Whewell. Mag. Collegii. A. D. MDCCCXLIII. Mr
Hope gave £1000, and the Master himself £250; but the
liberality of the College, which spent some £4000 before
the work was finished, is unrecorded. It was on this
occasion that somebody wrote a parody on The House that
Jack Built, beginning:

This is the House that Hope built.
This is the Master, rude and rough,
Who lives in the House that Hope built.
These are the Seniors, greedy and gruff,
Who toady the Master, rude and rough,
Who lives in the House that Hope built.
6. The Times, February 25 and 26, 1847. Mrs Stair
Douglas, p. 285, prints a letter from Archdeacon Hare, who
had been disturbed by reports of the Vice-Chancellor’s
vehemence.
7. The visit of Queen Victoria to the University in 1843.
8. A Letter to the Rev. W. Whewell, B.D., Master of Trinity
College, etc. By an Undergraduate. 8vo. London, 1843.
9. The Victory of Faith, and other Sermons. By J. C.
Hare, M. A. 8vo. Cambridge, 1840, p. x.
10. Mrs Stair Douglas, p. 216.
11. Dr Lightfoot’s Sermon, preached in the College
Chapel on Sunday, March 18, 1866.
12. They appeared in Punch for March 17, 1866.
13. The letter is dated 30 October, 1857.
14. Mrs Stair Douglas, p. 208.
15. Memoir by Sir John Herschel, Proceedings of Royal
Society, XVI., p. lvi.
16. Bishop Goodwin’s article in Macmillan’s Magazine for
December, 1881, p. 140.

17. We are not sure that he ever allowed the Origin of
Species to be admitted into the College Library. It was
certainly refused more than once, being probably dismissed
with the expression which he was fond of using when, as
Chairman of the Seniority, he read the list of books
proposed—‘a worthless publication.’
18. 1. Remains, Literary and Theological, of Connop
Thirlwall, late Lord Bishop of S. David’s. Edited by J. J.
Stewart Perowne, D.D. Vol. 1: Charges delivered between
the years 1842 and 1860. Vol. 2: Charges delivered
between the years 1863 and 1872. 8vo. (London, 1877.)
2. Essays, Speeches, and Sermons. By Connop Thirlwall,
D.D., late Lord Bishop of S. David’s. Edited by J. J. Stewart
Perowne, D.D. 8vo. (London, 1880.)
3. Letters to a Friend. By Connop Thirlwall, late Lord
Bishop of S. David’s. Edited by the Very Rev. Arthur Penrhyn
Stanley, D.D. 8vo. (London, 1881.)
4. Letters, Literary and Theological, of Connop Thirlwall,
late Lord Bishop of S. David’s. Edited by the Very Rev. J. J.
Stewart Perowne, D.D., Dean of Peterborough, and the Rev.
Louis Stokes, B.A. Corpus Christi College, Cambridge. With
Annotations and Preliminary Memoirs by the Rev. Louis
Stokes. 8vo. (London, 1881.)
5. Letters to a Friend. New Edition. (London, 1882.)
19. Dr Perowne’s Preface to Letters, c., p. vi.
20. Letters, c., p. 177.
21. Primitiæ, p. 52. The essay is endorsed: ‘Composed
1st January, 1806. Eight years old.’
22. Primitiæ, p. 224. The piece is dated October 28,
1808.

23. Letters to a Friend, p. 155. As a matter of fact the
Bishop did buy and destroy all the copies that he could.
24. Dean Perowne mentions (Preface, p. viii.) that ‘at
school he did not care to enter into the games and
amusements of the other boys, but was to be seen at play-
hour withdrawing himself into some corner with a pile of
books under his arm.’
25. Candler was seven years older than Thirlwall. He was
junior assistant in a draper’s shop at Ipswich, and
afterwards set up in business on his own account at
Chelmsford, where he became a leading member of the
Society of Friends. He died, nearly eighty years of age, in
1872. We have not been able to ascertain how he became
acquainted with Thirlwall.
26. Letters, c., p. 7.
27. Letters, c., p. 17.
28. Ibid. p. 8.
29. Letters to a Friend, p. 225.
30. Letters, c., p. 21. The letter is dated December,
1813, when the writer was sixteen years old.
31. Professor Monk, who had examined Thirlwall on one
of these occasions, was so much struck with the vigour and
accuracy of his translations that he remarked to a friend,
who had also had experience of his worth as a scholar,
‘Had I been sitting in my library, with unlimited access to
books, I could not have done better.’ ‘Nor so well,’ was the
reply.

32. Cooper’s Annals of the Town and University of
Cambridge, iv. 516. The words between inverted commas
in our text are from a pamphlet entitled ‘A Statement
regarding the Union, an Academical Debating Society,
which existed at Cambridge from February 13, 1815, to
March 24, 1817, when it was suppressed by the Vice-
Chancellor.’ The ‘statement’ is evidently official, and is
thoroughly business-like and temperate. The Vice-
Chancellor was Dr Wood, Master of S. John’s College; the
officers of the society were: Mr Whewell, President; Mr
Thirlwall, Secretary; Mr H. J. Rose, Treasurer. The late
Professor Selwyn, in a speech at the opening of the new
Union building, October 30, 1866, stated that on the
entrance of the proctors the President said, ‘Strangers will
please to withdraw, and the House will take the message
into consideration.’
33. Autobiography of John Stuart Mill, p. 125. Mill is
describing a debate at ‘a society of Owenites called the Co-
operation Society,’ in 1825. ‘It was a lutte corps à corps
between Owenites and political economists, whom the
Owenites regarded as their most inveterate opponents; but
it was a perfectly friendly dispute.... The speaker with
whom I was most struck, though I dissented from nearly
every word he said, was Thirlwall, the historian, since
Bishop of S. David’s, then a Chancery barrister, unknown
except by a high reputation for eloquence acquired at the
Cambridge Union before the era of Austin and Macaulay.
His speech was in answer to one of mine. Before he had
uttered ten sentences, I set him down as the best speaker
I had ever heard, and I have never since heard anyone
whom I placed above him.’
34. Letters, c., p. 31.

35. An old friend of Bishop Thirlwall informs us that he
retained his preference for the ‘Paradiso’ in after years.
36. Life and Letters of Frances Baroness Bunsen; by
Augustus J. C. Hare. 8vo. Lond. 1882: i. 138.
37. Letter to Bunsen, November 21, 1831, Letters, c., p.
99.
38. Memoirs of Baron Bunsen, i. 339.
39. Marsh was professor from 1807 to 1839. The first
volume of his translation of Michaelis had appeared in
1793.
40. Letters, c., p. 55.
41. Edinburgh Review, April, 1876, p. 291.
42. A Critical Essay on the Gospel of S. Luke. By Dr
Frederick Schleiermacher. With an introduction by the
Translator, containing an account of the controversy
respecting the origin of the first three Gospels since Bishop
Marsh’s dissertation. 8vo. London: 1825.
43. F. D. Maurice writes, 25 February, 1848: ‘The Bishop
of S. David’s very injudiciously translated, about twenty
years ago, Schleiermacher’s book on S. Luke—the one of
all, perhaps, which he ever wrote the most likely to offend
religious people in England, and so mislead them as to his
real character and objects.’ Life of F. D. Maurice, i. 454.
44. Between 1827 and 1832 he held the college offices
of Junior Bursar, Junior Dean, and Head Lecturer. In 1828,
1829, 1832, and 1834 he was one of the examiners for the
Classical Tripos.

45. See Dean Stanley’s Memoir of Archdeacon Hare,
prefixed to the third edition of The Victory of Faith. 1874.
46. A Vindication of Niebuhr’s ‘History of Rome’ from the
Charges of the ‘Quarterly Review.’ By Julius Charles Hare,
M.A. Cambridge, 1829. The passage commented on will be
found in the Quarterly Review for January 1829 (vol. xxxix.
p. 8). The first edition of Niebuhr’s own work had been
highly praised in an article in the same Review for June
1825 (vol. xxxii. p. 67).
47. On the Life of Dr Whewell, printed above. It was
originally called ‘Half a Century of Cambridge Life,’ and
appeared in the Church Quarterly Review, April 1882.
48. The Caput Senatus consisted of five persons, viz. a
Doctor of Divinity, a Doctor of Laws, a Doctor of Physic, a
non-regent Master, and a regent Master. These persons
held office for a year. They were elected by the votes of the
Heads of Colleges, the Doctors in all faculties, and the
Scrutators. Each member had the right to veto any
proposal of which he disapproved. The Caput Senatus was
established by the Statutes of Elizabeth, 1570, Cap. xli, and
abolished by the University Act, 1856.
49. The first petition was presented to the House of
Lords on March 21, 1834; the protest is dated April 3; and
the counter-petition was presented on April 21 in the same
year.
50. A Letter etc., p. 20.
51. A Letter etc., pp. 21, 22.
52. When the ‘Society for the Prevention of Cruelty to
Undergraduates’ tabulated the weekly attendance of the
Fellows at Chapel in the Lent Term of 1838, and finally

published a list, like the class list at the end of an
examination, Whewell was placed in the middle of the
second class, having obtained only 34 marks. The Deans,
being obliged, in virtue of their office, to attend twice daily,
were disqualified from obtaining the prize—a Bible—which
the Society gave to Mr Perry, afterwards Bishop of
Melbourne, who had obtained 66 marks.
53. It has been said that the Master was advised to take
the course he did by Mr Hugh James Rose, who was in the
University at the time, and on Whitsunday, May 18, had
preached a sermon at Great S. Mary’s on the ‘Duty of
Maintaining the Truth,’ from S. Matt. x. 27: ‘What ye hear in
the ear, that preach ye upon the house-tops.’ Thirlwall’s
letter, however, was not published before May 21, so that,
unless the nature of it had been known beforehand, it is
clear that anything which Mr Rose had said in his sermon
could not have referred to it. That Thirlwall believed that
there was some connexion between the sermon, or at any
rate the preacher, and his dismissal, is evident from the fact
that after showing the Master’s letter to one of the junior
Fellows, who expressed indignant surprise that such a
course could have been taken, he remarked: ‘Ah! let this be
a warning to you to preach truth, if need be, upon the
house-tops, but never under any circumstances to preach
error.’ Thirlwall was a regular attendant at Great S. Mary’s,
and no doubt heard the sermon in question.
54. The letter, dated 27 May, 1834, is printed by Mrs
Stair Douglas, Life of Dr Whewell, p. 163.
55. The letter, dated 23 September 1834, is printed in
Letters of Bishop Thirlwall, p. 124; and by Mrs Stair
Douglas, Life of Dr Whewell, p. 168. Dr Wordsworth’s
action was noticed with disapproval beyond the limits of
Trinity College, for Professor Babington records in his Diary:

Nov. 17 [1834]. Attended a meeting at Mr Bowstead’s
rooms at Corpus, to vote an address to Mr Connop Thirlwall
expressive of our sorrow at his being prevented from acting
as tutor, and of our disapprobation of the discussion of
things not forming part of the duties of tuition being made
a cause for depriving a tutor of his office.
Nov. 29. A meeting was called for 28th to take into
consideration the address to Thirlwall. Laing, Henslow, and
I supposed that it was this day, and went, and found that
the meeting was over and the address, much to our sorrow
burnt. (Memorials, etc. of Charles Cardale Babington, 8vo.
Camb. 1897, p. 33). Professor Mayor (Ibid. 265)
conjectures, with much probability, that the address was
destroyed at Thirlwall’s own suggestion. It is curious that
his friends should have deferred their action for so many
months.
56. Life of Dr Whewell, by Mrs Stair Douglas, p. 211.
58. The preface to the first edition of vol. i. is dated
‘Trinity College, June 12, 1835.’ He was instituted to Kirby
Underdale, 13 February, 1835 (Letters, p. 136), but he did
not take up his residence there till July following (Ibid. p.
137). The dates of the subsequent volumes are ii. iii., 1836;
iv., 1837; v., 1838; vi., 1839; vii., 1840; viii., 1844.
59. Letters, c. p. 138.
60. Preface to the second edition, dated ‘London, May
1845.’
61. Letters, c. p. 194. The letter is dated April 9, 1846.
62. The Personal Life of George Grote. By Mrs Grote, p.
173.

63. Memoirs of Viscount Melbourne. By W. M. Torrens,
M.P. Vol. ii. p. 332. Lord Houghton in the Fortnightly
Review, February 1878.
65. Letters, c. p. 161.
66. Letters, c. p. 292.
67. Charges, vol. ii. pp. 90-100.
68. In his charge for 1851 (Charges, vol. i. p. 150) he
announced his intention to devote the surplus of his income
to the augmentation of small livings, and in 1866 he
pointed out that the fund had up to that time yielded
£24,000 (Ibid. vol. ii. p. 98).
69. He particularly disliked gossip. At Kirby Underdale the
old sexton used to relate how Mr Thirlwall said, ‘I never
’ears no tales’; and the following story shows that he
maintained the same wise discretion after he became a
bishop. One of his archdeacons thought it right to tell him
that a certain clergyman in the diocese, who was a clever
mimic, was fond of entertaining his friends with imitations
of the Bishop. Thirlwall listened, and then inquired, ‘Does
he do me well?’ ‘I am sure I cannot say, my Lord,’ replied
the informer; ‘I was never present myself at one of these
disgraceful exhibitions.’ ‘Ah! I should like to know, because
he does you admirably,’ replied the Bishop. It is needless to
say that no more stories were carried to his ears.
70. An Earnestly Respectful Letter, 8vo. 1860, pp. 20-23.
See also The Life and Letters of Rowland Williams, D.D.,
London, 1874, chap. xv., where his determination to make
the Bishop declare himself, under the belief that he really
agreed with him, is expressly stated.

71. A Letter to the Rev. Rowland Williams, 8vo. 1860, p.
19.
72. Dean Stanley’s preface to the Letters to a Friend, p.
xi.
74. Review of ‘The letters of Bishop Thirlwall,’ The Times,
23 November, 1881.
75. The Edinburgh Review, for April, 1876, p. 292.
76. These words are inscribed upon Bishop Thirlwall’s
grave.
77. Life, Letters, and Friendships of Richard Monckton
Milnes, first Lord Houghton. By T. Wemyss Reid. Second
Edition, 2 vols. London, 1890.
78. Life, vol. i. p. xiii.
79. Reminiscences and Opinions of Sir F. H. Doyle, 8vo. Lond. 1886.
p. 108.
80. Richard Chenevix Trench, Archbishop. Letters and Memorials.
8vo. Lond. 1888. Vol. i. p. 50. Letter from J. W. Blakesley, 24 Jan, 1830.
81. Life, vol. i. p. 78.
82. Lord Houghton has been heard to say, when
describing his interview with Dr Wordsworth, then Master
of Trinity College: ‘I have always had a dim suspicion,
though probably I did not do so, that I substituted the
name of Wordsworth for Shelley.’ Life, vol. i. p. 77.
83. Life, vol. ii. p. 162.

84. Life of Cardinal Manning, by E. S. Purcell, 8vo. Lond.
1895, vol. i. p. 33.
85. The Poems of Richard Monckton Milnes, 2 vols.
(London, 1838), vol. i. p. 93.
86. Vol. i. p. 214.
87. Vol. i. p. 384. The letter is dated 31 March, 1847.
88. 1. The Life and Achievements of Edward Henry
Palmer, late Lord Almoner’s Professor of Arabic in the
University of Cambridge and Fellow of S. John’s College. By
Walter Besant, M.A. (London, 1883.)
2. Correspondence respecting the Murder of Professor E.
H. Palmer, Captain William Gill, R.E., and Lieutenant Harold
Charrington, R.N. Presented to both Houses of Parliament
by Command of Her Majesty. (London, 1883.)
89. Life, p. 182.
90. Life, p. 11.
91. Testimonials in favour of Edward Henry Palmer, B.A.
8vo. Hertford, 1867.
92. Life, p. 48.
93. The Desert of the Exodus, 8vo. Cambridge,
Deightons, 1871.
94. Desert of the Exodus, p. 325.
95. Desert of the Exodus, p. 503.
96. Life, pp. 120-125.

97. It is stated in Nature for July 16, 1883, in an article
by Prof. W. Robertson Smith, Palmer’s successor at
Cambridge, that Dr Wright was elected Fellow ‘without his
knowledge or consent.’ We are able to state, on the
authority of Dr Phillips himself, that Dr Wright was perfectly
aware of the honour about to be conferred upon him.
98. The Catalogue of Arabic, Persian, and Turkish MSS. in
Trin. Coll. Camb. was not published until 1871; but the fact
that it had been made was of course well known.
99. Cambridge University Reporter, 1872, p. 181.
100. Cambridge University Reporter, 1873, p. 142.
101. Grace of the Senate, April 29, 1875, confirming a
Report of the Council, dated March 15. We believe that it
was thought desirable to make the salary of the Professor
of Arabic equal to that of the Professor of Sanskrit, who
from the creation of the Professorship in 1867 received
£500 a year out of the University Chest.
102. Life, p. 142.
103. Life, p. 145.
104. This was Misleh, Sheikh of the Teyáhah Arabs.—Warren’s
Narrative, p. 10.
105. Life, pp. 266-278.
106. Letter to Admiral Sir William Hewett, dated Suez,
August 8. Blue Book, p. 4.
107. These five were Professor Palmer, Captain Gill,
Lieutenant Charrington, Khalil Atek the dragoman, and
Bochor the cook.

108. The whole story of his expedition has been
admirably told by Captain Haynes, who accompanied
Colonel Warren, in Man-hunting in the Desert. 8vo. London.
1894.
109. The Wady Sudr is quite out of the direct route from
Moses’ Wells to Nakhl, as Palmer of course knew. He must
therefore have been induced to go that way by some
earnest representation made to him by Meter.
110. Balfour and his guide lost their lives in a couloir at
the foot of the Italian side of the Aiguille Blanche. They
started from Courmayeur to attempt the ascent of the
Aiguille on the afternoon of Tuesday, 18 July, 1882, with
the expectation of returning on Thursday. The accident is
supposed to have taken place on Wednesday, the 19th.
111. Saturday Review, November 12, 1881.
112. This Report, dated 27 March, 1882, was confirmed
by the Senate 11 May; and the Professor was elected 31
May.
113. Wednesday, 10 February, 1886.
114. Dr Thompson died on Friday, 1 October, 1886.
115. The portrait painted by Hubert Herkomer, R.A., in
1881, which hangs in the College Hall, gives a life-like idea
of him at that time, though the deep lines on the face, and
the sarcastic expression of the mouth, are slightly
exaggerated.
116. Mr Trotter died on the morning of Sunday, 4
December, 1887.
117. Dr Okes died on Sunday, 25 November, 1888.

118. Dr Luard died on Friday, 1 May, 1891.
119. Church Quarterly Review, Vol. IX. pp. 1-39.
120. 1. The Life of Richard Owen. By his Grandson, the
Rev. Richard Owen, M.A., with the Scientific Portions revised
by C. Davies Sherborn, and an Essay on Owen’s Position in
Anatomical Science by the Right Hon. T. H. Huxley, F.R.S.
Second edition, 2 vols. (London, 1895.)
2.: Richard Owen. (Article in the Dictionary of National
Biography, vol. xlii.) By Sir W. H. Flower, K.C.B. (London,
1895.)
121. Extinct Wingless Birds of New Zealand, Preface, p.
1.
122. Anatomy, iii. 796.
123. We must except one delivered to the Young Men’s
Christian Association at Exeter Hall in the autumn of 1863.
It is called: On some Instances of the Power of God as
manifested in His Animal Creation; and was published in
the series of Exeter Hall Lectures by Messrs Nisbet. It is as
accurate as it is courageous, and both in conception and
execution does Owen infinite credit.

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