FPGA ASIC ANti fuse eprom eeprom sram diagrams

UNIT-II
 FPGA general structure
 Programmable logic
 Anti fuse
 Static RAM
 EPROM and EEPROM technology,
 FPGA Logic block – ZYNQ 7000

Programmable logic
2
The logic cells within an FPGA are configured using a programming
technology. There are two classes of programming technology :
i. OTP(One time programmable)
ii. Reprogrammable
Different FPGAs use different programmable (switching) elements :
iii.Antifuse in ACTEL FPGA
iv. Static RAM cell in Xilinx FPGA
v. EPROM/ EEPROM in Altera CPLD
Programmable interconnect (PI) is used to connect any two logic
cells.
Different FPGAs use different interconnect architectures
vi.Segmented Channel routing in ACTEL FPGA
vii.LCA interconnect architecture in Xilinx FPGA

Antifuse
4
Two types of antifuses are used :
i.Poly-diffusion antifuse (Actel) [ii] Metal-metal antifuse
(Quick Logic)
 Actel calls its antifuse as Programmable Low Impedance
Circuit
Element (PLICE)
 Advantage: small area overhead (size of the antifuse switching
element is very small in comparison with size of sRAM cell)
 Disadvantage : OTP

Antifuse
3
 An antifuse is the opposite of a regular fuse.
 An antifuse is a normally open(N.O) type of switch. A programming
current of 5 mA through it closes the switch.
 In a poly-diffusion antifuse, the high current density causes a large
power dissipation in a small area, which melts a thin insulating
dielectric between polysilicon and diffusion electrodes and forms a
thin (about 20 nm in diameter), permanent, and resistive silicon link.
 The programming process also drives dopant atoms from the poly
and diffusion electrodes into the link, and the final level of doping
determines the resistance value of the link. Actel calls its antifuse a
programmable low-impedance circuit element (PLICE ).

 Figure shows a poly diffusion antifuse with an oxide nitride
oxide (ONO) dielectric sandwich of: silicon dioxide (SiO2 )
grown over the n-type antifuse diffusion, a silicon nitride (Si3N4
) layer, and another thin SiO2 layer.
 The layered ONO dielectric results in a tighter spread of blown
antifuse resistance values than using a single-oxide dielectric.
The effective electrical thickness is equivalent to 10nm of SiO2,
(Si3N4 has a higher dielectric constant than SiO2,. so the actual
thickness is less than 10 nm).
 Sometimes this device is called a fuse even though it is an anti
fuse, and both terms are often used interchangeably.
 Antifuses separate interconnect wires on FPGA and
programmer blows an antifuse to make a permanent
connection. This programming process cannot be reversed.

Actel antifuse (a) A cross section of a poly-diffusion antifuse (b) A
simplified drawing. The ONO (oxide–nitride–oxide) dielectric is less
than 10 nm thick, so this diagram is not to scale. (c) From above, an
antifuse is approximately the same size as a contact.
6
Antifuse

7
• The size of an antifuse is limited by the resolution of the
lithography equipment used to makes ICs.
 The fabrication process and the programming current
control the average resistance of a blown antifuse.
 For programming current of 5 mA, antifuse resistance is
of the order of about 500 Ω. For 15 mA current, antifuse
resistance is about 100 Ω.
 The number of antifuse switches used in an ACTEL FPGA
is large. Eg. An Actel 1010 contains 1,12,000 antifuses.
 But we typically only need to program about 2 percent of
anti fuses on an actel chips

FPGA ASIC ANti fuse eprom eeprom sram diagrams

• To design and program an Actel FPGA, designers iterate between
design entry and simulation. When they are satisfied the design is
correct they plug the chip into a socket on a special programming
box, called an Activator, that generates the programming voltage.
• A PC downloads the configuration file to the Activator instructing it
to blow the necessary antifuses on the chip. When the chip is
programmed it may be removed from the Activator without
harming the configuration data and the chip assembled into a
system.
• One disadvantage of this procedure is that modern packages with
hundreds of thin metal leads are susceptible to damage when they
are inserted and removed from sockets.
• The advantage of other programming technologies is that chips
may be programmed after they have been assembled on a printed-
circuit board a feature known as in-system programming ( ISP ).

Metal-metal antifuse (Quick Logic)
ViaLink
8

• The link is an alloy of tungsten, titanium, and silicon with a bulk resistance
of about 500 mW cm.
• There are two advantages of a metal-metal antifuse over a poly diffusion
antifuse.
• The first is that connections to a metal metal antifuse are direct to metal
the wiring layers.
• Connections from a poly diffusion antifuse to the wiring layers require extra
space and create additional parasitic capacitance.
• The second advantage is that the direct connection to the low-resistance
metal layers makes it easier to use larger programming currents to reduce
the antifuse resistance.
• For example, the antifuse resistance R = 0.8/I, with the programming
current I in mA and R in W, for the QuickLogic antifuse.
• Figure shows that the average QuickLogic metal-metal antifuse resistance is
approximately 80 W (with a standard deviation of about 10 W) using a
programming current of 15 mA as opposed to an average antifuse
resistance of 500 W (with a programming current of 5 mA) for a poly
diffusion antifuse.

• The size of an antifuse is limited by the resolution of
the lithography equipment used to makes ICs.
• The Actel antifuse connects diffusion and polysilicon,
and both these materials are too resistive for use as
signal interconnects.
• To connect the antifuse to the metal layers requires
contacts that take up more space than the antifuse
itself, reducing the advantage of the small antifuse size.
• However, the antifuse is so small that it is normally the
contact and metal spacing design rules that limit how
closely the antifuses may be packed rather than the
size of the antifuse itself.

• An antifuse is resistive and the addition of contacts adds parasitic
capacitance. The intrinsic parasitic capacitance of an antifuse is
small (approximately 1-2 fF in a 1 mm CMOS process), but to this
we must add the extrinsic parasitic capacitance that includes the
capacitance of the diffusion and poly electrodes (in a poly diffusion
antifuse) and connecting metal wires (approximately 10 fF).
• These unwanted parasitic elements can add considerable RC
interconnect delay if the number of antifuses connected in series is
not kept to an absolute minimum. Clever routing techniques are
therefore crucial to antifuse-based FPGAs.
• The long-term reliability of antifuses is an important issue since
there is a tendency for the antifuse properties to change over
time. There have been some problems in this area, but as a result
we now know an enormous amount about this failure mechanism.
There are many failure mechanisms in Ics.

9
programming current of 15 mA (for quick logic).
Advantages of metal-metal antifuse over poly-
diffusion antifuse:
(ii)
(i) Connections form antifuses to wiring layers (metal) are
direct. Hence, associated parasitic capacitance is less.
Because of direct connection, area requirement is also reduced.
(iii) Also due to to use larger
direct connection, it is easier
current which results in
programming
resistance.
reduced antifuse
 For Quick logic antifuse resistance is given by
R ≈ 0.8/ I Ω, where I in mA
 Resistance of metal-metal antifuse is around 80 Ω for
a

10
Xilinx sRAM configuration cell
sRAM Cell

• An example of static RAM (SRAM) programming technology
is shown in fig.
• This Xilinx SRAM configuration cell is constructed from two
cross-coupled inverters and uses a standard CMOS process.
• The configuration cell drives the gates of other transistors on
the chip either turning pass transistors or transmission gates
on to make a connection or off to break a connection.
• The advantages of SRAM programming technology are that
designers can reuse chips during prototyping and a system
can be manufactured using ISP.
• This programming technology is also useful for upgrades a
customer can be sent a new configuration file to reprogram
a chip, not a new chip. Designers can also update or change a
system on the fly in reconfigurable hardware.

• The disadvantage of using SRAM programming
technology is that you need to keep power
supplied to the programmable ASIC (at a low
level) for the volatile SRAM to retain the
connection information.
• Alternatively you can load the configuration data
from a permanently programmed memory
(typically a programmable read-only memory or
PROM) every time you turn the system on.

11
Advantages:
 Designers can reuse chips
 Easy to upgrade the circuit design
Disadvantages:
 Volatile and power supply should be kept applied (Alternatively,
the configuration data can be downloaded from a PROM or Flash
memory) every time the system is turned ON)
 Larger in size

sRAM cell
12
Word line
5V
BIT
Line
BIT
Line
 SRAM cells are found in Xilinx FPGA
 Allow for efficient implementation
of memory
Six transistor SRAM cell

• Altera MAX 5000 EPLDs and Xilinx EPLDs both use UV-erasable
electrically programmable read-only memory (EPROM) cells as
their programming technology. Altera's EPROM cell is shown in
Figure.
• The EPROM cell is almost as small as an antifuse. An EPROM
transistor looks like a normal MOS transistor except it has a
second, floating, gate (gate1 in Figure).
• Applying a programming voltage Vpp (usually greater than 12 V) to
the drain of the n- channel EPROM transistor programs the EPROM
cell.
• A high electric field causes electrons flowing toward the drain to
move so fast they jump across the insulating gate oxide where they
are trapped on the bottom, floating, gate.
• We say these energetic electrons are hot and the effect is known as
hot-electron injection or avalanche injection. EPROM technology is
sometimes called floating-gate avalanche MOS (FAMOS ).

• Electrons trapped on the floating gate raise the threshold voltage of the
n- channel EPROM transistor (Figure 4.6 b). Once programmed, an n-
channel EPROM device remains off even with VDD applied to the top
gate.
• An unprogrammed n- channel device will turn on as normal with a top-
gate voltage of VDD.
• The programming voltage is applied either from a special programming
box or by using on-chip charge pumps. Exposure to an ultraviolet (UV)
lamp will erase the EPROM cell (Figure 4.6 c).
• An absorbed light quantum gives an electron enough energy to jump
from the floating gate. To erase a part we place it under a UV lamp
(Xilinx specifies one hour within 1 inch of a 12,000 m Wcm 2 source for
its EPLDS).
• The manufacturer provides a software program that checks to see if a
part is erased. You can buy an EPLD part in a windowed package for
development, erase it, and use it again, or buy it in a non windowed
package and program (or burn) the part once only for production.

• The packages get hot while they are being erased, so
that windowed option is available with only ceramic
packages, which are more expensive than plastic
packages.
• Programming an EEPROM transistor is similar to
programming an UV-erasable EPROM transistor, but
the erase mechanism is different.
• In an EEPROM transistor an electric field is also used
to remove electrons from the floating gate of a
programmed transistor.
• This is faster than using a UV lamp and the chip does
not have to be removed from the system. If the part
contains circuits to generate both program and erase
voltages, it may use ISP.

FPGA Logic block – ZYNQ 7000

• The Zynq-7000 family is based on the Xilinx SoC architecture.
These products integrate a feature-rich dual or single-core
ARM® Cortex™-A9 MPCore based processing system (PS) and
Xilinx programmable logic (PL) in a single device, built on a
state-of-the-art
• high-performance, low-power (HPL),28 nm, and high-k metal
gate (HKMG) process technology.
• As a result, the Zynq-7000 SoC devices are able to serve a
wide range of applications including:
• i)Broadcast camera ii) Industrial motor control iii)
industrial networking iv) machine vision v)
IP and smart camera vi) LTE radio and baseband vii)
Medical diagnostics and imaging viii) Multifunction printers ix)
Video and night vision equipment
FPGA Logic block – ZYNQ 7000

Architecture (Block Diagram)
The Zynq-7000 SoC is composed of the following major functional
blocks:
1. Processing System (PS)
2. Application processor unit (APU)
3. Memory interfaces
4. I/O peripherals (IOP)
5. Interconnect
6. Programmable Logic (PL)
The PS and PL can be tightly or loosely coupled using multiple
interfaces and other signals that have a combined total of over 3,000
connections.
This enables you to effectively integrate user-created hardware
accelerators and other functions in the PL logic that are accessible to
the processors and can also access memory resources in the
processing system.
The PS I/O peripherals, including the static/flash memory interfaces
share a multiplexed I/O (MIO) of up to 54 MIO pins. This is done
through an extended multiplexed I/O interface (EMIO).

Processing System (PS) Features and Descriptions:
• Application Processor Unit (APU)
• The application processor unit (APU) provides an
extensive offering of high-performance features
• Run time options allow single processor,
asymmetrical (AMP) or symmetrical
multiprocessing (SMP) configurations.
• NEON™ 128b SIMD coprocessor and VFPv3 per
MPCore
• 32 KB instruction and 32 KB data L1 caches with
parity per MPCore
• 512 KB of shareable L2 cache with parity
• Private timers and watchdog timers

MEMORY INTERFACES
• The memory interfaces includes multiple memory
technologies.
• DDR Controller Supports DDR3, DDR3L, DDR2, LPDDR-2
• Rate is determined by speed and temperature grade of
the device.
• 32b wide: 4 x 8b, 2 x 16b, 1 x 32b
• 16b wide: 2 x 8b, 1 x 16b
• Autonomous DDR power down entry and exit based on
programmable idle periods.
• Data read strobe auto-calibration.
• Low latency read mechanism using HPR queue.
• Special urgent signaling to each port.

I/O Peripherals
• The I/O Peripherals (IOP) are a collection of industry-standard
interfaces for external data communication.
• GPIO
• Up to 54 GPIO signals for device pins routed.
• Outputs are 3-state capable.
• 192 GPIO signals between the PS and PL via the EMIO.
• 64 Inputs, 128 outputs (64 true outputs and 64 output enables).
• The function of each GPIO can be dynamically programmed on an
individual or group basis.
• Enable, bit or bank data write, output enable and direction controls
• Programmable Interrupts on individual GPIO basis.
• Status read of raw and masked interrupt.
• Positive edge, negative edge, either edge, high level, low level
sensitivities.

USB Controllers: Each as Host, Device or OTG (Two)
• USB 2.0 high speed on-the-go (OTG) dual role USB host controller
or USB device controller operation using the same hardware
• MIO pins only (one USB controller is available in the 7x010
device)
• Built-in DMA
• USB 2.0 high speed device
• USB 2.0 high speed host controller
• The USB host controller registers and data structures are EHCI
compatible
• Direct support for USB transceiver low pin interface (ULPI). The
ULPI module supports 8 bits
• External PHY required
• Support up to 12 endpoints

CLBs, Slices, and LUTs
Some key features of the CLB architecture include:
1. True 6-input LUTs
2. Memory capability within the LUT
3. Register and shift register functionality
• The LUTs in the Zynq-7000 All Programmable SoC can be configured
as either one 6-input LUT (64-bit ROMs) with one output, or as
two 5-input LUTs (32-bit ROMs) with separate outputs but common
addresses or logic inputs.
• Each LUT output can optionally be registered in a flip-flop. Four
such LUTs and their eight flip-flops as well as multiplexers and
arithmetic carry logic form a slice, and two slices form a
configurable logic block (CLB). Four of the eight flip-flops per slice
(one flip-flop per LUT) can optionally be configured as latches.
• Modern synthesis tools take advantage of these highly efficient
logic, arithmetic, and memory features.

PS-PL Interfaces
• The PS-PL interface contains all the signals available to the PL
designer for integrating the PL-based functions and the PS.
There are two types of interfaces between the PL and the PS.
1. Functional interfaces which include AXI interconnect,
extended MIO interfaces (EMIO) for most of the I/O peripherals,
interrupts, DMA flow control, clocks, and debug interfaces.
These signals are available for connecting with user-designed IP
blocks in the PL.
2. Configuration signals which include the processor
configuration access port (PCAP), configuration status, single
event upset (SEU) and Program/Done/Init. These signals are
connected to fixed logic within the PL configuration block,
providing PS control

FPGA ASIC ANti fuse eprom eeprom sram diagrams

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