Fpga implementation of multi protocol data

IJRET: International Journal of Research in Engineering and Technology ISSN: 2319-1163 | pISSN: 2321-7308
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Volume: 03 Issue: 07 | Jul-2014, Available @ http://www.ijret.org 390
FPGA IMPLEMENTATION OF MULTI-PROTOCOL DATA
ACQUISITION SYSTEM USING VHDL
Chetan.Umadi1
, G.V.Jayaramaiah2
1
PG Student, Dept. of ECE, Dr.AIT, Bangalore, Karnataka, India
2
Professor & HOD, Dept. of ECE, Dr.AIT, Bangalore, Karnataka, India
Abstract
This paper describes the implementation of multi-protocol data acquisition system on FPGA. Data acquisition system includes
four different bus protocols and storing element (FIFO). FPGA works as a data acquisition system and transfers data from the
sensors/ADC to the output device. As FPGA allows each module to work independently. Therefore, we can utilize FPGA as a
multi channeled data acquisition system. The four different protocols: Parallel bus protocol, SPI, I2
C and One-Wire. All modules
were designed in VHDL& simulated using Xilinx-ISE 12.4and Xilinx Spartan -3E.
Keywords: FPAG, Xilinx, Spartan-3E kit, Parallel bus, SPI, I2
C, One-Wire and FIFO.
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1. INTRODUCTION
The data acquisition systems are most widely employed as
measurement systems in many industries. Main part of the
data acquisition system is bus protocols used in it. Buses are
integral part of data transmission in electronic devices.
These buses are implemented in software so the main aim is
to collect data from sensors or ADC‟S. This paper describes
the implementation of parallel and serial data transfer
protocols along with comparison. Parallel protocol is alone
parallel data transfer protocol and remaining all are serial
data transfer protocols. Each protocol having their own
characteristics and applications. Some can be replaced by
other protocols and some applications needs particular bus
protocol like Display/printer connections needs parallel
lines.
All protocols implanted on FPGA kit and modeled using
VHDL. The digital signals are provided from multichannel
sensors and four different ADC protocols.
2. PROPOSED WORK
The proposed system is shown in Figure 1 & 2. It shows the
connection of the ADC‟s with Bus protocols. The Bus
protocol includes Parallel, SPI, I2
C and One-wire. Each one
having separate ADC connections and the FPGA would
collect data from ADC sensors.
Fig- 1: Proposed system diagram
The System would process all bus protocols separately and
produce data at the output. Which intern connected to the
CRO to visualize the output waveform.

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Fig-2: Complete system design
3. IMPLEMENTATIONS and RESULTS
3.1 Parallel Bus Protocol
Bus is important part of data transmission for any on and
off-board communication. Bus may either parallel or serial
type. Parallel bus enables a system to communicate
simultaneously 8-bit to 64-bit with other devices or systems.
The parallel bus protocol is most widely used protocol for
data transmission as it can data transfer rate is higher than
serial protocols. The proposed design uses ADC0820 as a
example. Figure 3 shows simulation results of the parallel
bus.
Main steps in conversion process
 FPGA sends „initial‟ signal to ADC to start and
waits for data.
 After conversion ADC sends an acknowledgement
signal to the FPGA. FPGA reads all data and repeat
the process.
3.2 Serial Peripheral Interface (SPI) Protocol
SPI is a serial communication bus developed by Motorola. It
is a full-duplex protocol that functions on a master-slave
relation that is ideally suited for on board communication.
This design uses MCP3201 as a example. Figure 4 shows
the master-slave paradigm block diagram.
Fig-3: Simulated waveform of parallel bus protocol
SDOUT: Serial data output signal that carries data out of the
device.
SDIN: Serial data input signal it carries data into the device.
SCLK: Serial clock generated by Master for
synchronization.
SS: Slave select line to select/ activate slave device.
As SPI protocol is a serial protocol FPGA will read data in
serial manner. Procedure remains same like previous
protocol i.e. FPGA sends initial command to ADC to start
conversion and ADC informs with a signal to the FPGA
after conversion. Figure 5 shows the simulated SPI protocol
waveforms.

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Fig- 4: Master/Slave Transfer Block Diagram
Fig-5: Simulated waveform of SPI bus protocol.
3.3 Inter-Integrated Circuit Protocol (I2C) protocol
I2
C is a communication protocol having less number I/O
ports compared to SPI. It requires only two signal
connection wires namely SDA and SCL. It is a multi-
master/ salve system. Figure 6 shows typical I2
C master-
slave arrangement. This design uses PCF8591 ADC as a
example.
Both SDA and SCL lines are tied to VDD before start of the
data transfer.
Fig-6: Master/Slave Block Diagram of the I2
C protocol
Few general procedures for data manipulation.
 Initial state: SCL=VDD, SDA=VDD.
 Start Condition : SDA 10, SCL=1.
 Stop Condition : SDA 0  1, SCL=1.
Data has to transfer only between Start and Stop condition.
I2
C protocol is little complicated. This design uses PCF8591
ADC as a example. Figure 7 shows simulation result.
 The FPGA (Master) follows START procedure as
shown in the above condition. After this FPGA
writes Slave address on bus to identification and
waits for the acknowledgement.
 After acknowledgement FPGA sends register
address of the slave and waits for
acknowledgement.
 Now the FPGA sends read command to start
reading from slave. Each time acknowledgement is
must.
 Once completion of data transfer Master initiates
the STOP procedure by pulling SDA line to high.
Fig- 7: Simulated waveform of the I2
C bus protocol.
3.4 One-Wire Protocol
One-Wire communication protocol was developed by Dallas
Semiconductor owned by Maxim. This protocol allows
communication of multiple chips to one host with minimal
pin count. The protocol is called 1-Wire because it uses 1
wire to transfer data. 1-Wire architecture uses pull up
resistor to pull voltage of data line at master side. DS1820
used as the input of this One-Wire acquisition data protocol.
Conversion steps:
 The first step for this protocol is the „reset‟ from
the FPGA (master device).
 The FPGA would send a reset signal to the bus, and
wait for an presence pulse from sensor (slave
device). After receiving presence pulse.
 After that the FPGA would send the command to
sensor let it start data conversion.
 After series of commands FPGA reads scratch pad
memory of the slave device. That value indicates
temperature details.

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Figure 8 shows the simulated waveform of one-wire
protocol.
Fig-8: Simulated waveform of the one-wire bus protocol.
3.5 FIFO
A FIFO is a special type of buffer. The name FIFO stands
for first in first out and means that the data written into the
buffer first comes out of it first. They often called a stack
memory, and the shared memory. The choice of buffer
architecture depends on the application to be solved. Figure
9 shows generalized FIFO operation.
In this paper 8*512 size FIFO is designed, which is capable
of concurrent write and read operation.
1. Read Pointer and Write Pointer: Keep track of data
written/ read from memory/stack. Gray code counters
usually used to generate these pointers.
2. Write and Read Enable: These are used to start writing
or reading from buffer. Figure 10 shows FIFO write
operation.
Fig-9: General FIFO operation.
Fig-10: Simulation waveform of the FIFO.
3.6 Control Unit & Multiplexer
Control unit generates read_req signal and select line signal
for FIFO and Mux respectively. Once read signal activated
then FIFO outputs values and values reach as a mux input.
Based on select line mux produces output.
Multiplexer (or mux) is a device that selects one of several
analog or digital input signals and forwards the selected
input into a single line. A multiplexer of „2n‟ inputs has ‟n‟
select lines, which are used to select which input line to send
to the output. Mux designed for 4 (8 bit) lines with 3 bit
select line. Figure 11 shows final output waveform.
Fig-11: Final output waveform of the system
4. CONCLUSIONS
From the simulation results of the all bus protocol, we can
compare speed and pin count of all protocols. As parallel
bus having highest speed data transmission but alongside it
is having more pins. Similarly One-wire bus with only one
pin/line for communication but it is having limited
applications. I2
C having advantage of slave
acknowledgement feature but SPI does not support this
feature.

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Finally, we may conclude that based on the application
requirement bus protocols can be chosen. Even more types
bus protocols can also be implementing on FPGA and
compare with these bus protocols & even system can be
interfaced to PC through USB interface.
REFERENCES
[1]. S.Thane, S.Somkuamanit, S.Khuntawee.
“Implementation of Multi-Protocol, Data Acquisition with
High Speed USB interface, Using FPGA”, The International
Multi Conference of Engineers and Computer Scientists
(IMECS)- Vol I, March 17-19, 2010. Hong Kong.
[2]. Frédéric Leens, “An Introduction to I2C and SPI
protocols”. IEEE Instrumentation & Measurement Magazine
February 2009.
[3]. Bollam Eswari, N.Onmagal, K.Preethi, S.G. Sreejeesh,
“Implementation of I2C Master Bus Controller on FPGA”.
International Conference on Communication and Signal
Processing, April 3-5, 2013, India.
[4]. Bernhard Linke, “Overview of 1-Wire Technology and
Its Use”, Jun 19, 2008, Maxim Integrated Products, Inc.
[5]. Volnei A.Pedroni, “Circuit Design with VHDL”,MIT
Press, England.
[6]. Douglas L. Perry, “VHDL: Programming by Example”
4th
Edition.
BIOGRAPHIES
Chetan Umadi completed his Bachelor of
Engineering at K.L.S Vishwanath Rao
Deshpande Rural Institute of Technology,
Haliyal. Karnataka India in 2012.He is
Pursuing Master in Technology at
Dr.Ambedkar Institute of Technology,
Bangalore, India. His areas of interest are Digital design and
Embedded System Design.
Dr. G.V. Jayaramaiah completed his
Ph.D. From IIT-Bombay. He has
published around 19 Papers in
international journals. He is working as
Professor and Head of the department of
ECE at Dr.Ambedkar Institute of
Technology. Bangalore. India. His areas of interest are
Power Electronics, Renewable Energy and Embedded
Systems.

Fpga implementation of multi protocol data

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