I2C-Bus Design and Verification Specs

By/ Mostafa Khamis
Mostafaa.soc@riotmicro.com
I2C-Bus Design Specs

 Introduction
 Data Format Validation
 General Call Address Programming
 Arbitration
 Synchronization
 Clock Stretching
 Ultra Fast-mode Protocol
 Features Applicability
 I2C-Bus Registers
 Verification Specs.
Outline
Mostafa KhamisI2C-Bus Design and Verification Specs

 Philips Semiconductors (now NXP Semiconductors) developed a simple bidirectional 2-wire bus for efficient inter-IC control. This bus is
called the Inter-IC or I2C-bus which is a 8-bit oriented serial bus. Only two bus lines are required:
 a serial data line (SDA)
 a serial clock line (SCL).


 Data transfers operation modes:
1) Standard-mode >> up to 100 kbit/s
2) Fast-mode >> up to 400 kbit/s
3) Fast-mode plus (Fm+) >> up to 1 Mbit/s
4) High-speed mode >> up to 3.4 Mbit/s
5) Ultra Fast-mode (uni-directional mode) >> up to 5 Mbit/s
6)
7)
 All I2C-bus compatible devices incorporate an on-chip interface which allows them to communicate directly with each other via the I2C-bus.
This design concept solves the many interfacing problems encountered when designing digital control circuits.
Introduction

Some intelligent control, usually a single-chip micro—controller

 General-purpose circuits like LCD and LED drivers, remote I/O ports, RAM, EEPROM, real-time clocks or A/D and D/A
converters

 Application-oriented circuits such as digital tuning and signal processing circuits for radio and video systems, temperature
sensors, and smart cards
I2C-bus Applications:

Only two bus lines are required; a serial data line (SDA) and a serial clock line (SCL).

 Each device connected to the bus is software addressable by a unique address and simple master/slave relationships exist at
all times; masters can operate as master-transmitters or as master-receivers.

 It is a true multi-master bus including collision detection and arbitration to prevent data corruption if two or more masters
simultaneously initiate data transfer.

 Serial, 8-bit oriented, bidirectional data transfers can be made at up to 100 kbit/s in the Standard-mode, up to 400 kbit/s in
the Fast-mode, up to 1 Mbit/s in Fast-mode Plus, or up to 3.4 Mbit/s in the High-speed mode. The freq could be easily
programmed by software.

 Serial, 8-bit oriented, unidirectional data transfers up to 5 Mbit/s in Ultra Fast-mode

 The number of ICs that can be connected to the same bus is limited only by a maximum bus capacitance. More capacitance
may be allowed under some conditions.
I2C Features

Compatible with multiple masters.

 Includes clock stretching, so it could support a wait state generation.

 The acknowledge bit is software programmable.

 The core has interrupt driven byte-by-byte data transfers.

 The core supports different modes of operating conditions like- start, stop, repeated start and detects these conditions.

 Support to detect if the bus is busy processing other requests.

 Provides support for both 7-bit and 10-bit addressing modes.
I2C Features

Terminology
 The I2C-bus is a multi-master bus. This means that more than one device capable of controlling the bus can be connected
to it. As masters are usually microcontrollers, let us consider the case of a data transfer between two microcontrollers
connected to the I2 C-bus

Terminology
A is a master, addresses B(Slave)
 For transmission and receiving
 A terminates the transfer
 A generates the clk signals

Data Validity

Start and Stop Conditions
From high to low
while SCL is high
From low to high
while SCL is high
 Generated by the master
 The bus is considered to be busy after start (S) condition and free after stop (P)
 The same for repeated start (Sr)

Byte Format

ACK and NACK
The Acknowledge signal is defined as follows: the transmitter releases the SDA line during the acknowledge clock
pulse so the receiver can pull the SDA line LOW and it remains stable LOW during the HIGH period of this clock
pulse. Set-up and hold times must also be taken into account.

 When SDA remains HIGH during this ninth clock pulse, this is defined as the Not Acknowledge signal. The master
can then generate either a STOP condition to abort the transfer, or a repeated START condition to start a new
transfer.



 NACK Conditions:
 No receiver is present on the bus with the transmitted address so there is no device to respond with an
acknowledge.
 The slave is unable to receive or transmit because it is performing some real-time function and is not ready to
start communication with the master.
 During the transfer, the receiver gets data or commands that it does not understand.
 During the transfer, the receiver cannot receive any more data bytes.
 A master-receiver must signal the end of the transfer to the slave transmitter.

Slave Address and R/W bit

Slave Address and R/W bit
A master-transmitter addressing
a slave receiver with a 7-bit address

A master reads a slave immediately after the first byte

 Combined format

10-bit Addressing
10-bit addressing expands the number of possible addresses

 The first seven bits of the first byte are the combination 1111 0XX of which the last two bits (XX) are the two Most-
Significant Bits (MSB) of the 10-bit address; the eighth bit of the first byte is the R/W bit that determines the
direction of the message.

 The remaining first 5 bits are reserved for future I2C bus enhancements.

 A master-transmitter addresses a slave-receiver with a 10-bit address




 A master-receiver addresses a slave-transmitter with a 10-bit address

General Call Address Programming

General Call Address
 This format is done to write or program all slaves that are connected on the I2C bus.
 The master is waiting for acknowledgement at least from one slave.

 The general call address format




 When B = ‘0’: The second byte has the following meanings:
 0000 0110 (06h): Reset and write programmable part of slave address by hardware.
 0000 0100 (04h): Write programmable part of slave address by hardware.
 0000 0000 (00h): This code is not allowed to be used as the second byte.

 When B = ‘1’: The second byte is a hardware general call, this means that the transmitted sequence is sent by a
hardware master device, such as keyboard scanner (which can be programmed to transmit a desired slave
address).
 Note: the remaining 7-bits are for the hardware master
 address to acknowledge all connected slaves.

Bus Clear
If the data line (SDA) is stuck LOW, the master should send nine clock pulses.
The device that held the bus LOW should release it sometime within those nine clocks.
If not, then use the HW reset or cycle power to clear the bus.

Device ID
An optional 3-byte read-only (24 bits) word giving the following information:
 Could be accessed as follows:
1) START condition
2) The master sends the Reserved Device ID I2C-bus address followed by the R/W bit set to ‘0’ (write): ‘1111 1000’.
3) The master sends the I2C-bus slave address of the slave device it must identify.
4) The master sends a Re-START condition.
5) The master sends the Reserved Device ID I2C-bus address followed by the R/W bit set to ‘1’ (read): ‘1111 1001’.
6) The Device ID Read can be done, starting with the 12 manufacturer bits followed by the nine part identification bits, and then the
three die revision bits.
7) The master ends the reading sequence by NACKing the last byte, thus resetting the slave device state machine and allowing the
master to send the STOP condition.
8)
1) Note: If the master continues to ACK the bytes after the third byte, the slave rolls back to the first byte and keeps sending the
Device ID sequence until a NACK has been detected.
Twelve bits with the manufacturer name, unique per manufacturer
Nine bits with the part identification, assigned by manufacturer
Three bits with the die revision, assigned by manufacturer

Device ID
Assigned Manufacturer IDs:

If two or more masters try to put information onto the bus, the first to produce a ‘one’ when the other produces a ‘zero’ loses
the arbitration. The clock signals during arbitration are a synchronized combination of the clocks generated by the masters using
the wired-AND connection to the SCL line.

 Slaves are not included in the arbitration procedure.

 Arbitration proceeds bit by bit. During every bit, while SCL is HIGH, each master checks to see if the SDA level matches what
it has sent.

 Two masters can actually complete an entire transaction without error, as long as the transmissions are identical.

 A master that loses the arbitration can generate clock pulses until the end of the byte in which it loses the arbitration and
must restart its transaction when the bus is free.
Arbitration Logic


 Undefined conditions, if the arbitration procedure is still in progress at the moment when one master sends a repeated
START or a STOP condition:
 Master 1 sends a repeated START condition and master 2 sends a data bit.
 Master 1 sends a STOP condition and master 2 sends a data bit.
 Master 1 sends a repeated START condition and master 2 sends a STOP condition.
Arbitration Procedure

Generation of clock signals on the I2C-bus is always the responsibility of master devices; each master generates its own clock
signals when transferring data on the bus. Bus clock signals from a master can only be altered when they are stretched by a slow
slave device holding down the clock line or by another master when arbitration occurs.

 Two masters can begin transmitting on a free bus at the same time and there must be a method for deciding which takes
control of the bus and complete its transmission. This is done by clock synchronization and arbitration using the wired-AND.
In single master systems, clock synchronization and arbitration are not needed.
Synchronization Logic
A synchronized SCL clock is generated with its
LOW period determined by the master with the
longest clock LOW period, and its HIGH period
determined by the one with the shortest clock
HIGH period.

Instead of the master and slave agreeing to a predefined baud rate, the master controls the clock speed.

 Optional procedure, for pausing the transaction by holding the SCL to low.

 The transaction cannot continue until the line is released HIGH again

 Slaves are not applicable to stretch the clock because they don’t have SCL driver.

 For byte date level, when being sent in a fast rate, the device needs more time to store the byte before start another one.
So, a clock stretching here is needed after reception and acknowledgement of a byte by forcing the master into a wait state.

 Also, it can be used to slow down the bus clk when communicating with other controller with/without limited hardware.
Clock Stretching

Operates from DC to 5 MHz transmitting data in one direction.

 It is most useful for speeds greater than 1 MHz to drive LED controllers and other devices that do not need feedback.

 Is based on the standard protocol which consists of START, slave address, command bit, ninth clock, and a STOP bit. But the
command bit is a ‘write’ only, and the data bit on the ninth clock is driven HIGH, ignoring the ACK cycle due to the
unidirectional nature of the bus.

 The 2-wire push-pull driver consists of a UFm serial clock (USCL) and serial data (USDA).

 Since UFm I2C-bus uses push-pull drivers, it does not have the multi-master capability of the wired-AND open-drain Sm, Fm,
and Fm+ I2C-buses.

 The possibility of connecting more than one UFm master to the UFm I2C-bus is not allowed due to bus contention on the
push-pull outputs. (One Hot MUX)
Ultra Fast-mode (Ufm) protocol

Applicability of I2C-bus protocol features

Applicability of UFm I2C-bus

I2C-Bus Registers

 Prescaler 16-bits registers:
 The prescaler factor can be determined through the following equation: prescaler = (peripheral_clock / (5 * desired_SCL)) -1.
 Control Register:
Transmit Register:

 Receive Register
I2C-Bus Registers

Command Register:

 To generate and tells the Core what commands to do next. All the bits of this register are automatically cleared
and are usually read as Zeros.
I2C-Bus Registers

Status Register:

 Gives information about the status of the core and if any data transfer is in progress.
I2C-Bus Registers

I2C-Bus UVM Environment

 I2C Interface:
 It consists of Clock, Reset, SCL, and SDA signals for communication with the bus functional model and DUT.

 I2C BFM:
 It is used as drivers to drive the I2C interface signals through untimed separated tasks.
 UVM driver controls the BFM anyway and calls the tasks in BFM.
 UVM monitor also can call the BFM tasks to read from the DUT.

 I2C BFM Tasks:
 Reset Task
 Write Task
 It takes in the arguments delay, the master interface handle, the address and the data that needs to be
written
 Read Task
 It is similar to the write task in terms of the parameter it takes in but instead of writing data, the task read
data from the given address
I2C-Bus UVM Environment

I2C-Bus Design and Verification Specs

I2C-Bus Design and Verification Specs

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