I2C BUS PROTOCOL
- 1. Birla Vishwakarma Mahavidyalaya ET Department Under the Guidance :- Prof. Hiren Patel ET Department Prepared By:- Kashyap Mandaliya(08) Disha Rashtrapal(13) Meet Thakkar (18) Viral Rabadiya(22) I2C PROTOCOL 1
- 2. Topics :- • I2C BUS • I2C LINE ELECTRICAL CHARACTERISTICS • I2C NODES • BIT FORMATE • START AND STOP CONDITIONS • PACKET FORMAT IN I2C • CLOCK STRETCHING • ARBITRATION • MULTIBYTE BURST WRITE • MULTIBYTE BURST READ 2
- 3. Introduction WHY REQUIRED ? Many of today’s applications, however, require higher bus speeds and lower supply voltages. Description :- • The I2C bus was designed by PHILIPS in the early '80s to allow easy communication between components which reside on the same circuit board. • Philips Semiconductors migrated to NXP in 2006. • The name I²C translates into "Inter IC". Sometimes the bus is called IIC . 3
- 4. Generation of I2C • 1982 :- first release • 1998 :- higher bus speeds and lower supply voltage • 2007 introduced by NXP ) :- Fast mode plus introduced in this version • 2012 :- user manual release 4
- 5. I2C Architecture Half-duplex, synchronous, multi-master bus No chip select or arbitration logic required Serial data (SDA) and Serial clock (SCL) Fig 1 5
- 6. I2C NODES • Can function like a master or a slave . • Clock is generated by the master • The master device addresses the slave. • Both the master as well as the slave can transmit as well as receive data • Four operating modes :- -master transmitter -master receiver -slave transmitter -slave receiver NOTE :- A NODE CAN HAVE MORE THAN ONE OPERATING MODE. HOWEVER,AT A TIMES IT HAS ONLY ONE OPERATING NODE. Fig 2 Electrical Characteristics 6
- 7. Start & stop condition Start Condition – A high to low transition on SDA when SCL is high. Stop Condition – A low to high transition on SDA when SCL is high. Fig 3 7
- 8. Packet format in I2C 8
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- 19. 19 I2C Module
- 20. 20 THANK YOU