Iaetsd 128-bit area

128-Bit Area
K .Bala Sindhuri1
,
Assistant Professor,
SRKR Engineering College,
Bhimavaram,India.
k.b.sindhuri@gmail.comn_uk2010@yahoo.com
D.V.N.Bharathi3
, B. Tapasvi
M.Tech Student,
Department of ECE,
SRKR Engineering college,
Bhimavaram, India.
bapu.bharathi@gmail.com
Abstract—Carry Select Adder (CSLA)
of the fastest adders used in many data
processors to perform fast arithmetic functions.
structure of the CSLA, suggests that there is scope for
reducing the area in the CSLA. This work
simple and efficient gate-level modi
significantly reduce the area of the CSLA.
uses first, the implementation of adder and then excess
one adder. Based on this modification 128
root CSLA (SQRT CSLA) architecture has
and compared with the regular SQRT CSLA
architecture. For both modified and regular SQRT
CSLA adders, the theoretical calculations for delay and
area are tabulated. Experimentally delay and area
comparisons for both regular and modified
CSLA are done. The simulation is performed using
Modelsim and synthesis is carried on Xilinx ISE12.2
Index Terms— Area-efficient, CSLA, low
power.
I . INTRODUCTION
Design of area- and power-efficient high
speed data path logic systems are one of the most
substantial areas of research in VLSI system design.
In digital adders, the speed of addition is limited by
the time required to propagate a carry through the
adder. The sum for each bit position in an elementary
adder is generated sequentially only after the
previous bit position has been summed and a carry
propagated into the next position.
The CSLA is used in many computational
systems to alleviate the problem of carry propagation
delay by independently generating multiple carries
and then select a carry to generate the
sum[2].However, the CSLA is not area efficient
because it uses multiple pairs of Ripple Carry Adders
(RCA) to generate partial sum and carry by
considering carry input and ,then the final sum and
carry are selected by the multiplexers (mux).
Bit Area-Efficient Carry Select Adder
Prof .N .Udaya Kumar2
,
Professor, Department of ECE,
ng College, SRKREngineeringCollege,
Bhimavaram,India. Bhimavaram, India.
k.b.sindhuri@gmail.comn_uk2010@yahoo.com
B. Tapasvi4
,
M.Tech Student,
Department of ECE,
Bhimavaram,India.
tapasvi07@gmail.com
Carry Select Adder (CSLA) is one
of the fastest adders used in many data-processing
processors to perform fast arithmetic functions. the
that there is scope for
reducing the area in the CSLA. This work presents a
level modification to
of the CSLA. This method
and then excess
one adder. Based on this modification 128-bit square-
t CSLA (SQRT CSLA) architecture has presented
compared with the regular SQRT CSLA
For both modified and regular SQRT
, the theoretical calculations for delay and
area are tabulated. Experimentally delay and area
comparisons for both regular and modified SQRT
e simulation is performed using
Modelsim and synthesis is carried on Xilinx ISE12.2
efficient, CSLA, low
efficient high-
speed data path logic systems are one of the most
as of research in VLSI system design.
In digital adders, the speed of addition is limited by
the time required to propagate a carry through the
adder. The sum for each bit position in an elementary
adder is generated sequentially only after the
t position has been summed and a carry
The CSLA is used in many computational
systems to alleviate the problem of carry propagation
delay by independently generating multiple carries
a carry to generate the
However, the CSLA is not area efficient
because it uses multiple pairs of Ripple Carry Adders
(RCA) to generate partial sum and carry by
considering carry input and ,then the final sum and
exers (mux).
The basic idea of this work is to use Binary
to Excess-1 Converter (BEC) instead of RCA with in
the regular CSLA to achieve low
consumption [3]–[4]. The main advantage of this
BEC logic comes from the lesser number of logic
gates than the n-bit Full Adder (FA) structure. The
details of the BEC logic are discussed in Section III.
This paperis structured as follows:
deals with the delay and area evaluation methodology
of the basic adder blocks. Section III presents t
detailed structure and the function of the BEC logic.
The SQRT CSLA has been chosen for comparison
with the proposed design as it has a more balanced
delay, and requires lower power and area [5], [6].
The delay and area evaluation methodology of the
regular and modified SQRT CSLA are presented in
Sections IV and V, respectively. Results are analysed
in Section VI. Finally, the work is concluded in
Section VII.
Fig.1. Delay and Area evaluation of an XOR gate.
Department of ECE,
M.Tech Student,
The basic idea of this work is to use Binary
1 Converter (BEC) instead of RCA with in
the regular CSLA to achieve lower area and power
[4]. The main advantage of this
BEC logic comes from the lesser number of logic
bit Full Adder (FA) structure. The
details of the BEC logic are discussed in Section III.
is structured as follows:Section II
deals with the delay and area evaluation methodology
of the basic adder blocks. Section III presents the
detailed structure and the function of the BEC logic.
The SQRT CSLA has been chosen for comparison
with the proposed design as it has a more balanced
delay, and requires lower power and area [5], [6].
The delay and area evaluation methodology of the
ular and modified SQRT CSLA are presented in
Sections IV and V, respectively. Results are analysed
in Section VI. Finally, the work is concluded in
Fig.1. Delay and Area evaluation of an XOR gate.
INTERNATIONAL CONFERENCE ON CIVIL AND MECHANICAL ENGINEERING, ICCME-2014
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ISBN:378-26-138420-0217

Fig. 2.4-b BEC.
Fig. 3.4-b BEC with 8:4 mux.
II. DELAY AND AREA EVALUATION
METHODOLOGY OF THE BASIC ADDER
BLOCKS
The AND, OR, and Inverter (AOI)
implementation of an XOR gate is shown in Fig. 1.
The gates between the dotted lines are performing the
operations in parallel and the numeric representation
of each gate indicates the delay contributed by that
gate. The delay and area evaluation methodology
considers all gates to be made up of AND, OR, and
Inverter, each having delay equal to 1 unit and area
equal to 1 unit. We then add up the number of gates
in the longest path of a logic block that contributes to
the maximum delay. The area evaluation is done by
counting the total number of AOI gates required for
each logic block. Based on this approach, the CSLA
adder blocks of 2:1 mux, Half Adder (HA), and FA
are evaluated and listed in Table I.
with 8:4 mux.
II. DELAY AND AREA EVALUATION
METHODOLOGY OF THE BASIC ADDER
The AND, OR, and Inverter (AOI)
implementation of an XOR gate is shown in Fig. 1.
The gates between the dotted lines are performing the
umeric representation
of each gate indicates the delay contributed by that
gate. The delay and area evaluation methodology
considers all gates to be made up of AND, OR, and
Inverter, each having delay equal to 1 unit and area
p the number of gates
in the longest path of a logic block that contributes to
the maximum delay. The area evaluation is done by
counting the total number of AOI gates required for
each logic block. Based on this approach, the CSLA
Half Adder (HA), and FA
III.BINARY TO EXCESS-1CONVERTER (BEC)
As stated in section II the main idea of this
work is to use BEC instead of the RCA
to reduce the area and power consumption of the
regular CSLA. To replace the n
BEC is required. A structure and the function table o
a 4-b BEC are shown in Fig. 2. and
respectively.
Fig. 3. Illustrates how the basic fun
the CSLA is obtained by using the 4
together with the mux. One input of the 8:4 mux gets
as it input (B3, B2, B1, and B0) and another input of
the mux is the BEC output. This produces the two
possible partial results in parallel and the mu
to select either the BEC output or the direct inputs
according to the control signal Cin. The importance
of the BEC logic stems from the large silicon area
reduction when the CSLA with large number of bits
are designed. The Boolean expressions of
BEC is listed as (note the functional
& AND. XOR)
IV. DELAY AND AREA EVALUATION
METHODOLOGY OF REGULAR 128
CSLA
The structure of the 128
CSLA is shown in Fig. 4. It has five groups of
different size RCA. The delay and area evaluation o
last group is shown in Fig. 5.
CONVERTER (BEC)
the main idea of this
work is to use BEC instead of the RCA with in order
to reduce the area and power consumption of the
n-bit RCA, an n-bit
BEC is required. A structure and the function table of
b BEC are shown in Fig. 2. and Table II,
how the basic function of
the CSLA is obtained by using the 4-bit BEC
together with the mux. One input of the 8:4 mux gets
as it input (B3, B2, B1, and B0) and another input of
the mux is the BEC output. This produces the two
possible partial results in parallel and the mux is used
to select either the BEC output or the direct inputs
according to the control signal Cin. The importance
of the BEC logic stems from the large silicon area
reduction when the CSLA with large number of bits
are designed. The Boolean expressions of the 4-bit
BEC is listed as (note the functional symbols NOT,
IV. DELAY AND AREA EVALUATION
METHODOLOGY OF REGULAR 128-B SQRT
The structure of the 128-b regular SQRT
CSLA is shown in Fig. 4. It has five groups of
elay and area evaluation of
shown in Fig. 5.in which the
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ISBN:378-26-138420-0218

Fig.4.Regular 128-b SQRT CSLA
numerals within [ ] specify the delay values, e.g.,
10 gate delays. The steps leading to the evaluation
are as follows.
1)The group15 has fifteen sets of 28-b RCA. Based
on the consideration of delay values of Table I, the
arrival time of selection input ‫݁݉݅ݐ[211ܥ‬ሺ‫ݐ‬ሻ = 46]of
6:3 mux is earlier than ܵ114[‫ݐ‬ = 8]and later
than ܵ113[‫ݐ‬ = 6].Thus, ‫ݐ[411݉ݑݏ‬ = 52] is
summation of ܵ3and ‫ݐ[ݔݑܯ‬ = 3] and ‫ݐ[311݉ݑݏ‬ =
49] is summation of ‫ 211ܥ‬and mux.
Fig5. Delay and area evaluation of regular SQRT
CSLA ofgroup 15
2) The one set of 28-b RCA in group15 has 14 FA for
cin=1 and the other set has 1 FA and 1 HA for cin=0
.Based on the area count of Table I, the total number
of gate counts in group15 is determined as follows:
Gate count =447(FA+HA+Mux)
FA=337(29*13)
HA=6(1*6)
Mux=64(16*4)
Table III:
Delayand Area Countof Regular SQRT CSLA
Groups
3) Similarly, the estimated maximum delay
calculations for group2-group5[11-19] and area
calculations for group2-group5[57-147] are studied
[1].For the other groups in regular SQRT CSLA are
evaluated and listed in Table III.
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ISBN:378-26-138420-0219

Fig.6. Modified 128-bit SQRT CSLA
V. DELAY AND AREA EVALUATION
METHODOLOGY OF MODIFIED 128-B SQRT
CSLA
The structure of the proposed 128-b SQRT
CSLA using BEC for RCA with ‫ܥ‬௜௡ = 1 to optimize
the area and power is shown in Fig. 6. We again split
the structure into five groups. The delay and area
estimation of each group are shown in Fig. 7. The
steps leading to the evaluation are given here.
1) The group15 has one 28-b RCA which has 1 FA
and 1 HA for ‫ܥ‬௜௡ = 0. Instead of another 28-b RCA
with ‫ܥ‬௜௡ = 1 a 16-b BEC is used which adds one to
the output from 28-b RCA.Based on the
consideration of delay values of Table I, the arrival
time of selection input ‫݁݉݅ݐ[211ܥ‬ሺ‫ݐ‬ሻ = 46] of 6:3
mux is earlier than the ܵ114[‫ݐ‬ = 8]and‫ݐ[ݐݑ݋ܥ‬ = 36]
and later than the ܵ113[‫ݐ‬ = 6]. Thus, the sum3 and
final Cout (output from mux) are depending onS114
and mux and partial Cout (input to mux) and mux,
respectively. The sum2 depends on C112 and mux.
2) For the remaining group’s the arrival time of mux
selection input is always greater than the arrival time
of data inputs from the BEC’s. Thus, the delay of the
remaining groups depends on the arrival time of mux
selection input and the mux delay.
3) The area count of group15 is determined as
follows:
Gate count=342(FA+HA+MUX+BEC)
FA=182(14*13)
HA=6(1*6)
AND=14
NOT=1
XOR=75(15*5)
MUX=64(16*4)
Fig.7. Delay and area evaluation of Modified SQRT
CSLAOf group 15
4) Similarly, the estimated maximum
delaycalculations for group2-group5(13-22) and area
calculations for group2-group(43-112) are studied
[1].For the other groups of the modified SQRT
CSLA are evaluated and listed in Table IV.
Comparing Tables III and IV, it is clearly
understood that the proposed modified SQRT CSLA
saves 882 gate areas than the regular SQRT CSLA,
with only 40 increases in gate delays. To further
evaluate the performance.
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ISBN:378-26-138420-0220

Table IV:
Delayand Area Countof Modified SQRT CSLA
Groups
VI.RESULTS
Fig.8. Simulated Results for 128-b regular SQRT
CSLA
Fig.9. Simulated Results for 128-b modified SQRT
CSLA
Table V:
Summary Resultfor 128-b RegularSQRT CSLA
Table VI:
Summary Resultfor 128-b Modified SQRT CSLA
VII. CONCLUSION
A simple approach is presented in this paper
to reduce the area of SQRT CSLA architecture. The
reduced number of gates ofthis work offers the great
advantage in the reduction of area. The modified
CSLA architecture issimple and efficient architecture
for VLSI hardware implementation in the aspect of
low area. The results show that the modified SQRT
CSLA has a slightly larger delay (24.276ns) than the
regular SQRT CSLA (17.446ns).
VIII. FUTURE SCOPE
Area delay product of regular 128-b SQRT
CSLAand modified 128-b SQRT CSLA can be
experimentally performed.
REFERENCES
[1]. B. Ramkumar and Harish M Kittur “Low-
Power and Area-Efficient Carry Select
Adder”371-375, VOL. 20, NO. 2,
FEBRUARY 2012.
[2]. O. J. Bedrij, “Carry-select adder,” IRETrans.
Electron. Comput., pp. 340–344,1962.
[3]. B. Ramkumar, H.M. Kittur, and P. M.
Kannan, “ASIC implementation of
modifiedfaster carry save adder,” Eur. J. Sci.
Res., vol.42, no. 1, pp. 53–58, 2010.
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[4]. Y. Kim and L.-S. Kim, “64-bit carry-select
adder with reduced area,”Electron. Lett, vol.
37, no. 10, pp. 614–615, May 2001.
[5]. J. M. Rabaey, Digtal Integrated Circuits—
ADesign Perspective.Upper Saddle River,
NJ:Prentice-Hall, 2001.
[6]. Y. He, C. H. Chang, and J. Gu, “An
areaefficient 64-bit square root carry-select
adder forlowpower applications,” in Proc.
IEEE Int. Symp.Circuits Syst., 2005, vol. 4,
pp. 4082–4085.
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ISBN:378-26-138420-0222

Iaetsd 128-bit area

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