introduction to Architecture of 8086 and it's application

Dr. Vikas Mahor
Lecture-3
Architecture and Pin
Configuration of 8086

Architecture
Execution Unit (EU)
EU executes instructions that have
already been fetched by the BIU.
BIU and EU functions separately.
Bus Interface Unit (BIU)
BIU fetches instructions, reads data
from memory and I/O ports, writes
data to memory and I/ O ports.
8086 microprocessor

Architecture
Dedicated Adder to generate
20 bit address
Four 16-bit segment
registers
Code Segment (CS)
Data Segment (DS)
Stack Segment (SS)
Extra Segment (ES)
Segment Registers >>
8086 microprocessor

Architecture
Segment
Registers
Code Segment Register
16-bit
CS contains the base or start of the current code segment; IP contains the
distance or offset from this address to the next instruction byte to be fetched.
BIU computes the 20-bit physical address by logically shifting the contents of CS
4-bits to the left and then adding the 16-bit contents of IP.
That is, all instructions of a program are relative to the contents of the CS
register multiplied by 16 and then offset is added provided by the IP.
8086 microprocessor

Architecture
Segment
Registers
Data Segment Register
16-bit
Points to the current data segment; operands for most instructions are fetched
from this segment.
The 16-bit contents of the Source Index (SI) or Destination Index (DI) or a 16-bit
displacement are used as offset for computing the 20-bit physical address.
8086 microprocessor

Architecture
Segment
Registers
Stack Segment Register
16-bit
Points to the current stack.
The 20-bit physical stack address is calculated from the Stack Segment (SS) and
the Stack Pointer (SP) for stack instructions such as PUSH and POP.
In based addressing mode, the 20-bit physical stack address is calculated from
the Stack segment (SS) and the Base Pointer (BP).
8086 microprocessor

Architecture
Segment
Registers
Extra Segment Register
16-bit
Points to the extra segment in which data (in excess of 64K pointed to by the DS)
is stored.
String instructions use the ES and DI to determine the 20-bit physical address for
the destination.
8086 microprocessor

Architecture
Segment
Registers
Instruction Pointer
16-bit
Always points to the next instruction to be executed within
the currently executing code segment.
So, this register contains the 16-bit offset address pointing
to the next instruction code within the 64Kb of the code
segment area.
Its content is automatically incremented as the execution
of the next instruction takes place.
8086 microprocessor

Architecture
A group of First-In-First-Out (FIFO)
in which up to 6 bytes of
instruction code are pre fetched
from the memory ahead of time.
This is done in order to speed up
the execution by overlapping
instruction fetch with execution.
This mechanism is known as
pipelining.
Instruction queue
8086 microprocessor

Architecture
Some of the 16 bit registers can be
used as two 8 bit registers as :
AX can be used as AH and AL
BX can be used as BH and BL
CX can be used as CH and CL
DX can be used as DH and DL
Execution Unit (EU)
EU decodes and
executes instructions.
A decoder in the EU
control system
translates instructions.
16-bit ALU for
performing arithmetic
and logic operation
Four general purpose
registers(AX, BX, CX, DX);
Pointer registers (Stack
Pointer, Base Pointer);
and
Index registers (Source
Index, Destination Index)
each of 16-bits
8086 microprocessor

Architecture
EU
Registers
Accumulator Register (AX)
Consists of two 8-bit registers AL and AH, which can be
combined together and used as a 16-bit register AX.
AL in this case contains the low order byte of the word,
and AH contains the high-order byte.
The I/O instructions use the AX or AL for inputting /
outputting 16 or 8 bit data to or from an I/O port.
Multiplication and Division instructions also use the AX or
AL.
Execution Unit (EU)
8086 microprocessor

Architecture
EU
Registers
Base Register (BX)
Consists of two 8-bit registers BL and BH, which can be
combined together and used as a 16-bit register BX.
BL in this case contains the low-order byte of the word,
and BH contains the high-order byte.
This is the only general purpose register whose contents
can be used for addressing the 8086 memory.
All memory references utilizing this register content for
addressing use DS as the default segment register.
Execution Unit (EU)
8086 microprocessor

Architecture
EU
Registers
Counter Register (CX)
Consists of two 8-bit registers CL and CH, which can be
combined together and used as a 16-bit register CX.
When combined, CL register contains the low order byte of
the word, and CH contains the high-order byte.
Instructions such as SHIFT, ROTATE and LOOP use the
contents of CX as a counter.
Execution Unit (EU)
Example:
The instruction LOOP START automatically decrements
CX by 1 without affecting flags and will check if [CX] =
0.
If it is zero, 8086 executes the next instruction;
otherwise the 8086 branches to the label START.
8086 microprocessor

Architecture
EU
Registers
Data Register (DX)
Consists of two 8-bit registers DL and DH, which can be
combined together and used as a 16-bit register DX.
When combined, DL register contains the low order byte of
the word, and DH contains the high-order byte.
Used to hold the high 16-bit result (data) in 16 X 16
multiplication or the high 16-bit dividend (data) before a
32 ÷ 16 division and the 16-bit reminder after division.
Execution Unit (EU)
8086 microprocessor

Architecture
EU
Registers
Stack Pointer (SP) and Base Pointer (BP)
SP and BP are used to access data in the stack segment.
SP is used as an offset from the current SS during
execution of instructions that involve the stack segment in
the external memory.
SP contents are automatically updated (incremented/
decremented) due to execution of a POP or PUSH
instruction.
BP contains an offset address in the current SS, which is
used by instructions utilizing the based addressing mode.
Execution Unit (EU)
8086 microprocessor

Architecture
8086
Microprocessor
EU
Registers
Source Index (SI) and Destination Index (DI)
Used in indexed addressing.
Instructions that process data strings use the SI and DI
registers together with DS and ES respectively in order to
distinguish between the source and destination addresses.
Execution Unit (EU)

Architecture
Flag Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OF DF IF TF SF ZF AF PF CF
Carry Flag
This flag is set, when there is
a carry out of MSB in case of
addition or a borrow in case
of subtraction.
Parity Flag
This flag is set to 1, if the lower
byte of the result contains even
number of 1’s ; for odd number
of 1’s set to zero.
Auxiliary Carry Flag
This is set, if there is a carry from the
lowest nibble, i.e, bit three during
addition, or borrow for the lowest
nibble, i.e, bit three, during
subtraction.
Zero Flag
This flag is set, if the result of
the computation or comparison
performed by an instruction is
zero
Sign Flag
This flag is set, when the
result of any computation
is negative
Tarp Flag
If this flag is set, the processor
enters the single step execution
mode by generating internal
interrupts after the execution of
each instruction
Interrupt Flag
Causes the 8086 to recognize
external mask interrupts; clearing IF
disables these interrupts.
Direction Flag
This is used by string manipulation instructions. If this flag bit
is ‘0’, the string is processed beginning from the lowest
address to the highest address, i.e., auto incrementing mode.
Otherwise, the string is processed from the highest address
towards the lowest address, i.e., auto incrementing mode.
Over flow Flag
This flag is set, if an overflow occurs, i.e, if the result of a signed
operation is large enough to accommodate in a destination
register. The result is of more than 7-bits in size in case of 8-bit
signed operation and more than 15-bits in size in case of 16-bit
sign operations, then the overflow will be set.
Execution Unit (EU)
8086 microprocessor

Architecture
Sl.No. Type Register width Name of register
1 General purpose register 16 bit AX, BX, CX, DX
8 bit AL, AH, BL, BH, CL, CH, DL, DH
2 Pointer register 16 bit SP, BP
3 Index register 16 bit SI, DI
4 Instruction Pointer 16 bit IP
5 Segment register 16 bit CS, DS, SS, ES
6 Flag (PSW) 16 bit Flag register
8086 registers
categorized
into 4 groups
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OF DF IF TF SF ZF AF PF CF
8086 microprocessor

Architecture
Register Name of the Register Special Function
AX 16-bit Accumulator Stores the 16-bit results of arithmetic and logic operations
AL 8-bit Accumulator Stores the 8-bit results of arithmetic and logic operations
BX Base register Used to hold base value in base addressing mode to access memory
data
CX Count Register Used to hold the count value in SHIFT, ROTATE and LOOP instructions
DX Data Register Used to hold data for multiplication and division operations
SP Stack Pointer Used to hold the offset address of top stack memory
BP Base Pointer Used to hold the base value in base addressing using SS register to
access data from stack memory
SI Source Index Used to hold index value of source operand (data) for string
instructions
DI Data Index Used to hold the index value of destination operand (data) for string
operations
Registers and Special Functions
8086 microprocessor

Signal Description of 8086 Microprocessor
• The 8086 Microprocessor is a 16-bit CPU available in
3 clock rates, i.e. 5, 8 and 10MHz, packaged in a 40
pin CERDIP or plastic package.
• The 8086 Microprocessor operates in single
processor or multiprocessor configurations to
achieve high performance.
• Some of the pins serve a particular function in
minimum mode (single processor mode) and others
function in maximum mode (multiprocessor mode)
configuration.

• The 8086 signals can be categorized in three groups.
• The first are the signals having common functions in
minimum as well as maximum mode.
• The second are the signals which have special
functions in minimum mode
• Third are the signals having special functions for
maximum mode

The following signal description are common for both
the minimum and maximum modes.
AD15-AD0:
•These are the time multiplexed memory I/O address
and data lines.
•Address remains on the lines during T1 state, while the
data is available on the data bus during T2, T3, TW and
T4. Here T1, T2, T3, T4 and TW are the clock states of a
machine cycle.
• TW is a wait state.
• These lines are active high and float to a tristate during
interrupt acknowledge and local bus hold acknowledge
cycles.

A19/S6, A18/S5, A17/S4, A16/S3:
• These are the time multiplexed address and status
lines.
• During T1, these are the most significant address
lines or memory operations.
• During I/O operations, these lines are low.
• During memory or I/O operations, status information
is available on those lines for T2, T3, TW and T4 .
• The status of the interrupt enable flag bit(displayed
on S5) is updated at the beginning of each clock
cycle.

A19/S6, A18/S5, A17/S4, A16/S3….:
• The S4 and S3 combinedly indicate which segment
register is presently being used for memory accesses
as shown in Table.
• The status line S6 is always low(logical).

BHE’/S7-Bus High Enable/Status:
• The bus high enable signal is used to indicate the
transfer of data over the higher order (D15-D8) data
bus as shown in Table.
• It goes low for the data transfers over D15-D8 and is
used to derive chip selects of odd address memory
bank or peripherals.

BHE’/S7-Bus High Enable/Status…….:
• BHE’ is low during T1 for read, write and interrupt
acknowledge cycles, when- ever a byte is to be
transferred on the higher byte of the data bus.
• The status information is available during T2, T3 and T4.
• The signal is active low and is tri-stated during 'hold'.
• It is low during T1 for the first pulse of the interrupt
acknowledge cycle.
MN/MX ‘:
• The logic level at this pin decides whether the processor
is to operate in either minimum (single processor) or
maximum (multiprocessor) mode.

RD’-Read:
• Read signal, when low, indicates the peripherals that the
processor is performing a memory or I/O read operation.
• RD is active low and shows the state for T2, T3, TW of any
read cycle.
• The signal remains tri-stated during the 'hold acknowledge'.
READY:
• This is the acknowledgement from the slow devices or
memory that they have completed the data transfer.
• The signal made available by the devices is synchronized by
the 8284A clock generator to provide ready input to the 8086.

INTR-lnterrupt Request:
• This is a level triggered input.
• This is sampled during the last clock cycle of each
instruction to determine the availability of the
request.
• If any interrupt request is pending, the processor
enters the interrupt acknowledge cycle.
• This can be internally masked by resetting the
interrupt enable flag.
• This signal is active high and internally synchronized.

TEST:
• This input is examined by a 'WAIT' instruction.
• If the TEST input goes low, execution will continue,
else, the processor remains in an idle state.
• The input is synchronized internally during each clock
cycle on leading edge of clock.
NMI-Non-maskable Interrupt:
• This is an edge-triggered input which causes a Type2
interrupt.
• A transition from low to high initiates the interrupt
response at the end of the current instruction.
• This input is internally synchronized.

RESET:
• This input causes the processor to terminate the
current activity and start execution from FFFF0H.
• The signal is active high and must be active for at least
four clock cycles.
• It restarts execution when the RESET returns low.
• RESET is also internally synchronized.
CLK-Clock Input:
• The clock input provides the basic timing for
processor operation and bus control activity.
• The range of frequency for different 8086 versions is
from 5MHz to 10MHz.

Pin Functions for the Minimum Mode Operation of 8086.
M/IO’ -Memory/IO:
• This is a status line logically equivalent to S2 in
maximum mode.
• When it is low, it indicates the CPU is having an I/O
operation, and when it is high, it indicates that the
CPU is having a memory operation.
• This line becomes active in the previous T4 and
remains active till final T4 of the current cycle.
• It is tri-stated during local bus "hold acknowledge".

INTA’ -Interrupt Acknowledge:
• This signal is used as a read strobe for interrupt
acknowledge cycles.
• In other words, when it goes low, it means that the
processor has accepted the interrupt.
• It is active low during T2, T3 and TW of each interrupt
acknowledge cycle.
ALE-Address latch Enable:
• This output signal indicates the availability of the valid
address on the address/data lines, and is connected to
latch enable input of latches.
• This signal is active high and is never tri-stated.

DT /R’ -Data Transmit/Receive:
• This output is used to decide the direction of data flow
through the trans-receivers (bidirectional buffers).
• When the processor sends out data, this signal is high
and when the processor is receiving data, this signal is
low.
• Logically, this is equivalent to S1 in maximum mode.
• Its timing is the same as M/IO.
• This is tri-stated during 'hold acknowledge'.

DEN’-Data Enable:
• This signal indicates the availability of valid data over
the address/data lines.
• It is used to enable the trans-receivers (bidirectional
buffers) to separate the data from the multiplexed
address/data signal.
• It is active from the middle ofT2 until the middle of
T4 DEN is tri-stated during 'hold acknowledge' cycle.
HOLD, HLDA-Hold/Hold Acknowledge:
• When the HOLD line goes high, it indicates to the
processor that another master is requesting the bus
access.

HOLD, HLDA-Hold/Hold Acknowledge...:
• The processor, after receiving the HOLD request, issues
the hold acknowledge signal on HLDA pin, in the
middle of the next clock cycle after completing the
current bus (instruction) cycle.
• At the same time, the processor floats the local bus
and control lines.
• When the processor detects the HOLD line low, it
lowers the HLDA signal.
• HOLD is an asynchronous input, and it should be
externally synchronized.

HOLD, HLDA-Hold/Hold Acknowledge...:

Pin Functions for Maximum Mode Operation
S2, S1, S0 -Status Lines:
• These are the status lines which reflect the type of
operation, being carried out by the processor.

QS1, QS0-Queue Status:
• These lines give information about the status of the
code prefetch queue.
• These are active during the CLK cycle after which the
queue operation is performed.

LOCK’:
• The LOCK signal is activated by the 'LOCK' prefix
instruction and remains active until the completion of
the next instruction.
• This output pin indicates that other system bus
masters will be prevented from gaining the system
bus, while the LOCK signal is low.
• When the CPU is executing a critical instruction which
requires the system bus, the LOCK prefix instruction
ensures that other processors connected in the system
will not gain the control of the bus.
• This floats to tri-state off during "hold acknowledge".

RQ/GT0, RQ/GT1-ReQuest/Grant:
• These pins are used by other local bus masters, in maximum
mode, to force the processor to release the local bus at the end
of the processor's current bus cycle.
• Each of the pins is bidirectional with RQ/GT0 having higher
priority than RQ/ GT1, RQ/GT pins have internal pull-up
resistors and may be left unconnected.
• The request! grant sequence is as follows:
1. A pulse one clock wide from another bus master requests the
bus access to 8086.
2. During T4 (current) or T1 (next) clock cycle, a pulse one clock
wide from 8086 to the requesting master, indicates that the
8086 has allowed the local bus to float and that it will enter the
"hold acknowledge" state at next clock cycle.

RQ/GT0, RQ/GT1-ReQuest/Grant...........:
3. A one clock wide pulse from the another master
indicates to 8086 that the 'hold’ request is about to
end and the 8086 may regain control of the local bus
at the next clock cycle.
• Thus each master to master exchange of the local
bus is a sequence of 3 pulses. There must be at least
one dead clock cycle after each bus exchange.

introduction to Architecture of 8086 and it's application

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