![[1] https://www.computerhope.com/jargon/f/finfet.htm
[2] https://en.wikipedia.org/wiki/FinFET
[3] http://www.radio-electronics.com/info/data/semicond/fet-field-
effect-transistor/finfet-technology-basics.php
[4]https://www.electronicsnotes.com/articles/electronic_compone
nts/fet-field-effect-transistor/finfet-transistor-technology.php
REFERENCES](https://image.slidesharecdn.com/introductiontofinfet-180227020253/85/Introduction-to-FinFET-13-320.jpg)
Introduction to FinFET
- 1. Prepared and Presented By: Manish Kenchi USN 2KA14EC021 ECE ( 8TH SEM) SKSVMACET Laxmeshwar
- 2. INTRODUCTION HISTORY CONSTRUCTION WORKING APPLICATIONS ADVANTAGES AND DRAWBACKS CONCLUSION List of Contents
- 3. The term “FINFET” describes a non- planar, double gate transistor built on an SOI substrate, based on the single gate transistor design. The important characteristics of FINFET is that the conducting channel is wrapped by a thin Si “fin”, which forms the body of the device. INTRODUCTION The thickness of the fin determines the effective channel length of the device.
- 4. FINFET is a transistor design first developed by Chenming Hu and his colleagues at the University of California at Berkeley, which tries to overcome the worst types of SCE(Short Channel Effect). HISTORY OF FINFET SOI FINFET with thick oxide on top of fin are called “Double-Gate” and those with thin oxide on top as well as on sides are called “Triple-Gate” FINFETs Originally, FINFET was developed for use on Silicon- On-Insulator(SOI).
- 5. CONTRUCTION OF A FINFET 1. Substrate 3. Oxide deposition 2. Fin etch
- 6. 6. Gate oxide 4. Planarization 5. Recess etch
- 7. 7. Deposition of the gate Finally a highly n+-doped poly silicon layer is deposited on top of the fins, thus up to three gates are wrapped around the channel: one on each side of the fin, and - depending on the thickness of the gate oxide on top - a third gate above.
- 8. WORKING OF A FINFET The working principle of a FinFet is similar to that of a conventional MOSFET. The MOSFET can function in two modes for both p-channel and n-channel MOSFETs: enhancement mode and depletion mode The channel shows maximum conductance when there is no voltage on the gate terminal. As the voltage changes to positive or negative, the conductivity of the channel reduces. In enhancement mode of MOSFET, when there is no voltage on the gate terminal, it does not conduct. Unlike the depletion mode, in enhancement mode, the device conducts better when there is more voltage on the gate terminal.
- 9. ADVANTAGES OF FINFET Higher technological maturity than planar DG. Suppressed Short Channel Effect(SCE) Better in driving current More compact Low cost DISADVANTAGES OF FINFET Reduced mobility for electrons Higher source and drain resistances Poor reliability
- 10. This month it is expected Qualcomm Snapdragon 855 will reportedly be the 'world's first' 7nm SoC Media tek helio x30 chipset with decacore processor uses 10nm technology Samsung started its 10nm SoC mass production in the year 2016 (Samsung galaxy s8) In the New York Times, On may 4 2011, it was published that INTEL will use FINFET for about 22nm. LATEST UPDATES ABOUT FINFET
- 11. Possibility to save power arises when both gates can be controlled separately. The second gate can be used to control the threshold voltage of the device, thereby allowing fast switching on one side and reduced leakage currents when circuits are idle. Finally, separate access to both gates could also be used to design simplified logic gates. This would also reduce power, and save chip area, leading to smaller, more cost-efficient designs. World leader in smartphones, Samsung Electronics has incorporated FinFet in its 14nm processors (Exynos7 Octra). This processor is used in the latest Samsung smartphone, the Samsung Galaxy S6. Along with Samsung, Apple, Intel and TSMC are set to ship the 14nm technology by 2016. This technology will benefit all smartphones as it will speed up the phone. APPLICATIONS
- 12. Finally, the industry has proved already many times that existing planar technology can be mastered and new roadblocks in device scaling can be removed either by innovations in technological processes or design solutions. This moves the targeted introduction of FINFET technology towards even smaller technology nodes increasing technological challenges and restricting its specifications even more. CONCLUSION
- 13. [1] https://www.computerhope.com/jargon/f/finfet.htm [2] https://en.wikipedia.org/wiki/FinFET [3] http://www.radio-electronics.com/info/data/semicond/fet-field- effect-transistor/finfet-technology-basics.php [4]https://www.electronicsnotes.com/articles/electronic_compone nts/fet-field-effect-transistor/finfet-transistor-technology.php REFERENCES