IT3030E-CA-Chap2-Computer System and Interconnection.pdf

IT3030E Fall 2024 1
Computer Architecture
Ngo Lam Trung & Pham Ngoc Hung, Hoang Van Hiep
Department of Computer Engineering
School of Information and Communication Technology (SoICT)
Hanoi University of Science and Technology
E-mail: [trungnl, hungpn, hiephv]@soict.hust.edu.vn

IT3030E Fall 2024 2
Chapter 2: Top-level view of Computer Functions
and Interconnection
1. Computer Components
2. Computer Functions
3. Inter-connection Structures
[with materials from Computer Organization and Architecture, 10th Edition,
William Stallings, ©2016, Pearson]

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Computer Organization
❑ From Chap.1: classic components of a computer
❑ Computer
❑ Input data
❑ Execute stored programs
❑ Output result

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1. Computer Components
❑ More detailed computer organization
Memory
Link Input/Output
To/from network
Processor
Control
Datapath
Input
Output
CPU I/O
Computer organization with system link

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Hardware and software approaches
❑ Hardware approach
l For a specific computation:
- Construct the computation function by connecting several basic
logic components: hardwired programming
l New program or new computation → rewiring the hardware
l General computer does not follow this approach

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Hardware and software approaches
❑ Software approach
l Use a general-purpose hardware taking data and control signals
as input, produce results
l Programing is now much easier, instead of rewiring the
hardware → provide new sequence of codes (instructions)
l Question: where the Data comes from? Where the instructions
come from?

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Computer components: top-level view

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CPU (Central Processing Unit)
❑ Control Unit
l Fetch instruction from memory.
l Interpret instruction.
l Control other components to execute instruction.
❑ Datapath: performs arithmetic operations to process data
(i.e., Arithmetic and Logic Unit).
❑ Register file (chapter 3): small and fast data storage for
instruction execution.
❑ Some other dedicated components

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CPU
❑ Example: Apple A5

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Memory
❑ Store instructions of the running programs.
❑ Store data that are currently in use.
Further reading: memory technologies

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Memory
❑ Logical organization
l Array of memory cells
l Each cell holds one byte of data
l Each cell is assigned an unique adress
l Data value can be changed, address is fixed
❑ Data are stored on memory cells
l 8-bit integer requires 1 cell
l 32-bit integer requires 4 cells
l Array requires consecutive cells according to
its size.
l …

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Input/output
❑ Interfacing computer with physical world/environment.
❑ Types of I/O device
l Input: mouse, keyboard, webcam…
l Output: display, printer, speaker…
l Storage: HDD, SSD, optical, USB drives…
l Communication: WiFi, Ethernet, Bluetooth modules…

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Link: System interconnection
❑ The fabric to connect all components
❑ Huge number of connection, requires very good design
so that all components function properly
❑ A modern computer motherboard (mainboard) typically
has 4 to 12 layers.

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2. Computer functions
❑ Executing program
❑ Interrupt
❑ Input/Output

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2.1 Executing program
❑ ➔ the most basic function of computers.
❑ Program: a set of instructions.
❑ Instruction: a set of binary bits in a predefined format
(usually consist of two main parts: Opcode and
Operands)
❑ Computers execute instructions sequentially.
❑ Instruction cycle: the processing required for a single
instruction execution
l Instruction fetch (fetch cycle): control unit fetches an instruction
from memory
l Instruction execution (execute cycle):
- control unit decodes instruction,
- then “tells” datapath and other components to perform the required
action.
- More details in Chapter 5.

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Instruction fetch
❑ Questions:
l How does the CPU know which instruction to fetch next?
l Where is the location of the fetched instruction inside CPU?

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Instruction fetch
❑ Importance
l To get the correct instruction.
l To execute all instructions in a program sequentially.
❑ At the beginning of each instruction cycle the processor
fetches an instruction from memory.
❑ The program counter (PC) holds the address of the
instruction to be fetched.
❑ The processor increases PC after each instruction fetch
so that PC points to the next instruction in sequence.
❑ The fetched instruction is loaded into the instruction
register (IR).

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Instruction execution
❑ Instruction (fetched and stored in IR) is decoded to get
l The operation that the processor needs to do
l The location to get input data (source operands)
l The location to store output data (destination operand)
❑ Operand address calculation: calculate the address of
operands
❑ Operand fetch: fetch source operands
❑ Data operation: perform the action on source operands
and get result
❑ Operand store: store result into destination operand

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Types of operation
• The processor may
perform some
arithmetic or logic
operation on data
• An instruction may
specify that the
sequence of
execution be altered
• Data transferred to
or from a peripheral
device by
transferring between
the processor and
an I/O module
• Data transferred
from processor to
memory or from
memory to
processor
Processor-
memory
Processor-
I/O
Data
processing
Control

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Example
❑ Consider following hypothetical computer
l The computer contains a single register named AC (16 bits)
l Instruction format: 16 bits, 4 bits for the Opcode (representing 16
different opcodes/instructions)

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Example
❑ What is the value of AC register in step 2, 3, 4, 5, 6?
Elaboration: How to support branching?

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Example
❑ Solution

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2.2 Interrupt
❑ What if CPU operates without interrupt?
❑ Fact: most external devices are much slower than CPU
❑ Suppose that CPU is transferring data with a printer
using above instruction cycle scheme
l After each write operator, CPU must wait until the printer
catches up

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2.2 Interrupt
❑ The mechanism to allow other components (memory,
I/O) interrupt the normal processing of processor.
❑ Servicing interrupt: processor temporarily switch from the
current program to execute a different (rather short)
program, before continuing the original program.
Elaboration: what is the difference
between servicing interrupt and
calling sub-routines?

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CPU time consume when I/O operation time is short
❑ Assume the
I/O operation
time is shorter
than
execution time
of instructions
between two
“WRITE”
instructions in
user program

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CPU time consume when I/O operation time is long
❑ Assume the I/O
operation time is
longer than
execution time of
instructions between
two “WRITE”
instructions in user
program

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Sources of interrupt
❑ Typical sources of interrupt:
l Software/program: occurs during instruction execution upon
some special condition such as division by 0, arithmetic
overflow… Can also be called exception.
l Timer: generated by system timer inside processor, to provide
timing service, such as for operating system task scheduler
service.
l I/O: generated by I/O modules, to request service from
processor or acknowledge the completion of an operation.
l Hardware failure: generated when error happens with hardware.
❑ Example: detecting keyboard events (key up/key down)
l Method 1: CPU checks keyboard status frequently
l Method 2: keyboard issue interrupt to notify CPU upon key
up/down
l Which is better regarding CPU usage?

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Interrupt handler/Interrupt service routine (ISR)
❑ Special programs to be executed to service interrupts.
❑ Usually a part of operating system or system software.
❑ Typical operation:
l Determine the nature of interrupt: source and reason of interrupt.
l Perform corresponding operation.
l Return control to the interrupted program.
❑ Structure:
l Interrupt handler ends with a special instruction, to restore
context and value of PC, so that CPU can continue the
interrupted program properly.

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Servicing interrupts: instruction and interrupt cycle
❑ Interrupt is checked at the end of each instruction cycle
❑ Interrupt cycle if interrupt occurred:
l CPU saves context of current program (current value of PC).
l Address of interrupt handler is loaded to PC.
l CPU continues with new instruction cycles, with new PC.
Interrupt handler will be executed instead of original program.
l At the end of interrupt handler, context will be restored including
PC value. CPU return to the interrupted program.

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Multiple interrupt procesing
❑ Number of interrupt sources is (always) high.
❑ Interrupts can occur at the same time or overlap.
❑ Sequential vs nested interrupt processing
l Usually priority-based.
l More details in chapter 7.

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2.3 Input/output
❑ The operation when data is transferred between I/O
modules and CPU/memory.
❑ CPU-controlled data transfer: data is transferred between
CPU and I/O, under the control of CPU.
❑ Direct memory access: data is transferred between
memory and I/O, under the control of special controllers
called DMAC.

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3. System interconnection
❑ Interconnection model of each component
➔ Need to connect these components
❑ Theoretical bus interconnection scheme

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System interconnection
❑ Interconnection system for high performance computers:
hierarchical bus

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End of chapter 2

IT3030E-CA-Chap2-Computer System and Interconnection.pdf

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