Chapter01 (1).ppt

1
Computer System Overview
Chapter 1

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Operating System
• Exploits the hardware resources of one
or more processors
• Provides a set of services to system users
• Manages secondary memory and I/O
devices

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Basic Elements
• Processor
• Main Memory
– Volatile
– referred to as real memory or primary memory
• I/O modules
– secondary memory devices
– communications equipment
– terminals
• System bus
– communication among processors, memory, and
I/O modules

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Basic Elements
• Processor: Controls the operation of the
computer
• Performs its data processing functions.
• When there is only one processor, it is often
referred to as the central processing unit
(CPU).

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Basic Elements
• Main memory: Stores data and programs.
This memory is typically volatile; that is,
when the computer is shut down, the contents
of the memory are lost.
• In contrast, the contents of disk memory are
retained even when the computer system is
shut down.
• Main memory is also referred to as real
memory or primary memory.

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Basic Elements
• I/O modules: Move data between the
computer and its external environment.
• The external environment consists of a variety
of devices, including secondary memory
devices (e.g., disks), communications
equipment, and terminals.
• System bus: Provides for communication
among processors, main memory, and I/O
modules.

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Top-Level Components
PC MAR
IR MBR
I/O AR
I/O BR
CPU Main Memory
System
Bus
I/O Module
•
•
•
•
•
•
•
•
•
Buffers
Instruction
0
1
2
n - 2
n - 1
Data
Data
Data
Data
Instruction
Instruction
Figure 1.1 Computer Components: Top-Level View
PC = Program counter
IR = Instruction register
MAR = Memory address register
MBR = Memory buffer register
I/O AR = Input/output address register
I/O BR = Input/output buffer register
Execution
unit

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Processor
• Two internal registers
– Memory address register (MAR)
• Specifies the address for the next read or write
– Memory buffer register (MBR)
• Contains data written into memory or receives
data read from memory
– I/O address register
– I/O buffer register

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Processor Registers
• User-visible registers
– Enable programmer to minimize main-
memory references by optimizing register
use
• Control and status registers
– Used by processor to control operating of
the processor
– Used by privileged operating-system
routines to control the execution of
programs

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User-Visible Registers
• May be referenced by machine language
• Available to all programs - application
programs and system programs
• Types of registers
– Data
– Address
• Index
• Segment pointer
• Stack pointer

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User-Visible Registers
• Address Registers
– Index
• Involves adding an index to a base value to get
an address
– Segment pointer
• When memory is divided into segments,
memory is referenced by a segment and an
offset
– Stack pointer
• Points to top of stack

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Control and Status Registers
• Program Counter (PC)
– Contains the address of an instruction to be fetched
• Instruction Register (IR)
– Contains the instruction most recently fetched
• Program Status Word (PSW)
– Condition codes
– Interrupt enable/disable
– Supervisor/user mode

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Control and Status Registers
• Condition Codes or Flags
– Bits set by the processor hardware as a
result of operations
– Examples
• Positive result
• Negative result
• Zero
• Overflow

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EVOLUTION OF THE MICROPROCESSOR
• Earlier : multichip processor
• Microprocessor: Contained a processor on a single
chip.
• They are now multiprocessors; each chip (called a
socket) contains multiple processors (called
cores), each with multiple levels of large memory
caches, and multiple logical processors sharing the
execution units of each core.
• Graphical Processing Units (GPUs) provide
efficient computation on arrays of data using
“Single-Instruction Multiple Data (SIMD)”
techniques pioneered in supercomputers.

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EVOLUTION OF THE MICROPROCESSOR
• Digital Signal Processors (DSPs) are also
present, for dealing with streaming signals—
such as audio or video.
• DSPs used to be embedded in I/O devices, like
modems,
• but now becoming first-class computational
devices, especially in handhelds
• Summary:
• To satisfy the requirements of handheld devices, instead of
classic microprocessor “System on a Chip (SoC), CPUs and
caches are on the same chip + such as DSPs, GPUs, I/O devices
(such as radios and codecs), and main memory on single chip.

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Instruction Execution
• Two steps
– Processor reads instructions from memory
• Fetches
– Processor executes each instruction

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Instruction Fetch and Execute
• The processor fetches the instruction
from memory
• Program counter (PC) holds address of
the instruction to be fetched next
• Program counter is incremented after
each fetch

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Instruction Register
• Fetched instruction is placed in the instruction
register.
• The instruction contains bits that specify the
action the processor is to take.
• The processor interprets the instruction and
performs the required action .
• These actions generally grouped into four
categories.

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Instruction Register
• Categories
– Processor-memory
• Transfer data between processor and memory
– Processor-I/O
• Data transferred to or from a peripheral device
– Data processing
• Arithmetic or logic operation on data
– Control
• Alter sequence of execution

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Characteristics of a
Hypothetical Machine
Both
instructions and
data are 16 bits
long, and
memory is
organized as a
sequence of 16-
bit words.

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• 300 1940
• 301 5940
• 302 2941
• 940 0002
• 941 0003

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• The instruction format provides 4 bits for the
opcode, allowing as many as 24 16 different
opcodes
• (represented by a single hexadecimal 1 digit).
• The opcode defines the operation the processor
is to perform. With the remaining 12 bits of
the instruction format, up to 212 4,096 (4K)
words of memory (denoted by three
hexadecimal digits) can be directly addressed.

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• The PC contains 300, the address of the first instruction. This instruction
(the value 1940 in hexadecimal) is loaded into the IR and the PC is
incremented.
• Note that this process involves the use of a memory address register
(MAR) and a memory buffer register (MBR).
• 2. The first 4 bits (first hexadecimal digit) in the IR indicate that the AC
is to be loaded from memory. The remaining 12 bits (three hexadecimal
digits) specify the address, which is 940.
• 3. The next instruction (5941) is fetched from location 301 and the PC is
• incremented.
• 4. The old contents of the AC and the contents of location 941 are added
and the result is stored in the AC.
• 5. The next instruction (2941) is fetched from location 302 and the PC is
• incremented.
• 6. The contents of the AC are stored in location 941.

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Example of Program Execution

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Interrupts
• What?
• A mechanism by which other modules (I/O,
memory) may interrupt the normal sequencing of
the processor.

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Interrupts
• Why?
• Interrupts are provided primarily as a way to
improve processor utilization.
• When?
• Most I/O devices are slower than the processor
– Processor must pause to wait for device
– E.g processor-printer

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Program Flow of Control
Without Interrupts

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Program Flow of Control Without
Interrupts
• A sequence of instructions, to prepare for the actual I/O
operation.
– i.e This may include copying the data to be output into a special
buffer and preparing the parameters for a device command.
• The actual I/O command.
– Without the use of interrupts, once this command is issued, the
program must wait for the I/O device to perform the requested
function (or periodically check the status, or poll, the I/O
device).
– The program might wait by simply repeatedly performing a test
operation to determine if the I/O operation is done.
• A sequence of instructions, to complete the operation.
– This may include setting a flag indicating the success or failure
of the operation.

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Program Flow of Control With
Interrupts, Short I/O Wait
User
Program
WRITE
WRITE
WRITE
I/O
Program
I/O
Command
Interrupt
Handler
END
1
2a
2b
3a
3b
4
5
(b) Interrupts; short I/O wait

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Program Flow of Control With
Interrupts; Long I/O Wait

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Interrupt Handler
• Program to service a particular I/O
device
• Generally part of the operating system

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Interrupts
• Suspends the normal sequence of
execution

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Interrupt Cycle
• Processor checks for interrupts
• If no interrupts fetch the next instruction
for the current program
• If an interrupt is pending, suspend
execution of the current program, and
execute the interrupt-handler routine

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Timing Diagram Based on Short
I/O Wait

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Timing Diagram Based on long
I/O Wait

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Simple Interrupt Processing

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Changes in Memory and
Registers for an Interrupt

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Changes in Memory and
Registers for an Interrupt

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Multiple Interrupts
• Disable interrupts while an interrupt is
being processed

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Multiple Interrupts
• Define priorities for interrupts

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Multiprogramming
• Processor has more than one program to
execute
• The sequence the programs are executed
depend on their relative priority and
whether they are waiting for I/O
• After an interrupt handler completes,
control may not return to the program
that was executing at the time of the
interrupt

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Memory Hierarchy
• The design constraints on a computer’s memory can
be summed up by three questions:
• How much?
• How fast?
• How expensive? (Tradeoff)
• Faster access time, greater cost per bit
• Greater capacity, smaller cost per bit
• Greater capacity, slower access speed

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Going Down the Hierarchy
• Decreasing cost per bit
• Increasing capacity
• Increasing access time
• Decreasing frequency of access of the
memory by the processor
– Locality of reference

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• Locality of reference / principle of
locality:
– Tendency of the computer program to
access the same set of memory
locations for a particular time period.
– Spatial Locality
– Temporal Locality

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– Temporal Locality :
• This type of optimization includes bringing in
the frequently accessed memory references
to a nearby memory location for a short
duration of time so that the future accesses
are much faster.
• Eg. if in an instruction set we have a
variable declared that is being accessed
very frequently we bring in that variable
in a memory register which is the nearest
in memory hierarchy for faster access.

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– Spatial Locality :
• Assumes that if a memory location has been
accessed it is highly likely that a
nearby/consecutive memory location will be
accessed as well
• Hence we bring in the nearby memory
references too in a nearby memory location
for faster access.
• E.g : Traversal of a one-dimensional array
in any instruction set will benefit from this
optimization.

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– Does the strategy of using two memory levels
works in principle, but only if
conditions(a) through (d) applies.

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Exercise Given:
• Suppose that the processor has access to two levels of
memory. Level 1 contains 1,000 bytes and has an access
time of 0.1 μs; level 2 contains 100,000 bytes and has an
access time of 1 μs. Assume that if a byte to be accessed is
in level 1, then the processor accesses it directly. If it is in
level 2, then the byte is first transferred to level 1 and then
accessed by the processor. (for simplicity we ignore the
transfer time)
• In our example, suppose 95% of the memory accesses are
found in the cache . Then the average time to access a byte:

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Exercise Given:
• Memory hit / Miss:
– A Memory hit refers to the situation wherein the memory is
able to successfully find data and supply to the application.
– Memory Hit Ratio :
• A hit ratio is a calculation of memory hits, and comparing
them with how many total content requests were
received.

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Exercise Given:
• Average Time to access a byte:
• (0.95) *(0.1 s) + (0.05)* (0.1 s + 1 s)= 0.095 + 0.055 =
0.15 s

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Memory
• Registers,Cache, and Primary memory
– Employs semi conductor technology
– Volatile
– May be visible to the programmer in terms of
individual bytes or words
• Secondary / Auxiliary memory
– Nonvolatile
– Used to store program and data files
– visible to the programmer only in terms of files
and records,
– A hard disk is also used to provide an extension to
main memory known as virtual memory

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Disk Cache
• A portion of main memory used as a buffer to
temporarily to hold data for the disk.
• Rationale ????
• Disk writes are clustered
• Adv….
• Some data written out may be referenced
again. The data are retrieved rapidly from the
software cache instead of slowly from disk

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Cache Memory
• Invisible to operating system
• But,Interacts with other memory management hardware.
• Motivation
• In every instruction cycle, processor access memory many
times (to fetch instruction, operands and store result).
• Problem: The rate at which the processor can execute
instructions is clearly limited by the memory cycle time
(Bottleneck)
• Ideally, Technology to built processor registers, should be
used to built main memory. (Expensive)

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Cache Memory
• Solution:
• Exploit the principle of locality by providing a small, fast
memory between the processor and main memory.
• Increase the speed of memory access
• Still with a price of less expensive types.
• Exploit the principle of locality
• There is a relatively large and slow main memory together
with a smaller, faster cache memory.

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Cache Memory
• Contains a copy of a portion of main memory
• When processor wants a byte or word, cache is first
checked for it.
• If not found in cache, fixed number of blocks of
memory containing the needed information is
moved to the cache and delivered to the processor.
• Locality of reference plays role that this process is
not so frequent.

Cache/Main Memory System
Memory
address
0
1
2
0
1
2
C - 1
3
2n - 1
Word
Length
Block Length
(K Words)
Block
(K words)
Block
Line
Number Tag Block
(b) Main memory
(a) Cache
Figure 1.17 Cache/Main-Memory Structure
M(No. of Blocks)=2n/K
&
C<<<M

Cache/Main Memory System
As a simple example, suppose that we have a 6-bit address
and a 2-bit tag. The tag 01 refers to the block of locations
with the following addresses:
010000, 010001, 010010, 010011, 010100, 010101, 010110,
010111, 011000, 011001, 011010, 011011, 011100, 011101,
011110, 011111.

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Cache Design
• Cache size
– Small caches have a significant impact on
performance
• Block size
– The unit of data exchanged between cache and
main memory
– Larger block size more hits until probability of
using newly fetched data becomes less than the
probability of reusing data that have to be
moved out of cache

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Cache Design
• Mapping function
– Determines which cache location the block
will occupy
– Once cache filled (which to replace?)
– Target – maximize hit ratio.
• Replacement algorithm
– Determines which block to replace
– Least-Recently-Used (LRU) algorithm

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Cache Design
• Write policy
– When the memory write operation takes
place
– Can occur every time block is updated
– Can occur only when block is replaced
• Minimizes memory write operations
• Leaves main memory in an obsolete state

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Programmed I/O
• I/O module performs the
action, not the processor
• Sets appropriate bits in the
I/O status register
• No interrupts occur
• Processor checks status until
operation is complete

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Interrupt-Driven I/O
• Processor is interrupted when I/O
module ready to exchange data
• Processor saves context of
program executing and begins
executing interrupt-handler
• No needless waiting
• Consumes a lot of processor time
because every word read or
written passes through the
processor

70
Direct Memory Access
(DMA)
• I/O exchanges occur directly with
memory
• Processor grants I/O module authority to
read from or write to memory
• Relieves the processor responsibility for
the exchange

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Direct Memory Access
• Transfers a block of data
directly to or from memory
• An interrupt is sent when
the transfer is complete
• Processor continues with
other work

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MULTIPROCESSOR AND MULTICORE
ORGANIZATION
• The three most popular approaches to providing parallelism:
• How?
• by replicating processors:
symmetric multiprocessors (SMPs),
multicore computers,
clusters.

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ORGANIZATION
• An SMP can be defined as a stand-alone computer system with the
• following characteristics:
• 1. There are two or more similar processors of comparable capability.
• 2. These processors share the same main memory and I/O facilities and
are interconnected by a bus or other internal connection scheme, such
that memory access time is approximately the same for each processor.
• 3. All processors share access to I/O devices, either through the same
channels or through different channels that provide paths to the same
device.
• 4. All processors can perform the same functions (hence the term
symmetric ).
• 5. The system is controlled by an integrated operating system that
provides interaction between processors and their programs at the job,
task, file, and data element levels.

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ORGANIZATION
Symmetric Multiprocessor

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ORGANIZATION
• Cache Coherence Problem :
Problem :
• Processors generally have at least one level of cache
• This use of cache introduces some new design considerations.
• Local cache contains an image of a portion of main memory, if a
word is altered in one cache, it could invalidate a word in another
cache.
Solution :
• Other processors must be alerted that an update has taken place.
• Addressed in hardware rather than by the OS. 6

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ORGANIZATION
• SMP Vs Uniprocessor Organization (Potential Advantages)
– Performance: some portions of the work can be done in parallel (If
the work to be done by a computer can be organized in such a way)
– Availability : The failure of a single processor does not halt the
machine. Instead, the system can continue to function at reduced
performance (all processors can perform the same functions.)
– Incremental growth: A user can enhance the performance of a
system by adding an additional processor. Incrementally
– Scaling: Vendors can offer a range of products with different price
and performance characteristics based on the number of processors
configured in the system.

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ORGANIZATION
Multicore Computers (chip multiprocessor) :
– combines two or more processors (called cores) on a single piece of
silicon (called a die).
– Typically, each core consists of all of the components of an
independent processor
• Registers
• ALU
• pipeline hardware
• control unit
• L1 instruction and data caches.
• Contemporary multicore chips also contain L2 cache and sometimes
even L3.

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ORGANIZATION
Multicore Computers (chip multiprocessor) :

79
Where you stand?????
Now you are able to:
• Describe the basic elements of a computer system and their
interrelationship.
• Explain the steps taken by a processor to execute an instruction.
• Understand the concept of interrupts and how and why a processor
uses interrupts.
• List and describe the levels of a typical computer memory
hierarchy.
• Explain the basic characteristics of multiprocessor and multicore
organizations.
• Discuss the concept of locality and analyse the performance of a
multilevel memory hierarchy.
• Understand the operation of a stack and its use to support
procedure call and return.

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Practice Exercise 1:
• Consider a hypothetical 32-bit microprocessor having 32-bit
instructions composed of two fields. The first byte contains
the opcode and the remainder an immediate operand or an
operand address.
• a. What is the maximum directly addressable memory
capacity (in bytes)?
• b. Discuss the impact on the system speed if the
Microprocessor bus has
– 1. a 32-bit local address bus and a 16-bit local data bus, or
– 2. a 16-bit local address bus and a 16-bit local data bus.
• c. How many bits are needed for the program counter and
the instruction register?

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Practice Exercise 1: (Solution)
• a. 2^(32-8) = 2^24 = 16,777,216 bytes = 16 MB
–(8 bits = 1 byte for the opcode).
b.1. a 32-bit local address bus and a 16-bit local data bus.
Instruction and data transfers would take three bus cycles
each, one for the address and two for the data. Since If the
address bus is 32 bits, the whole address can be transferred
to memory at once and decoded there; however, since the
data bus is only 16 bits, it will require 2 bus cycles (accesses
to memory) to fetch the 32-bit instruction or operand.
.

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Practice Exercise 1: (Solution)
• b.2. a 16-bit local address bus and a 16-bit local data bus.
Instruction and data transfers would take four bus cycles each, two
for the address and two for the data. Therefore, that will have the
processor perform two transmissions in order to send to memory
the whole 32-bit address; this will require more complex memory
interface control to latch the two halves of the address before it
performs an access to it. In addition to this two-step address issue,
since the data bus is also 16 bits, the microprocessor will need 2
bus cycles to fetch the 32-bit instruction or operand.
c. For the PC needs 24 bits (24-bit addresses), and for the IR needs
32 bits (32-bit addresses).

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Practice Exercise : 2
• Suppose the hypothetical processor of Figure 1.3 also has
two I/O instructions:
– 0011 Load AC from I/O
– 0111 Store AC to I/O
• In these cases, the 12-bit address identifies a particular
external device. Show the program execution (using format
of Figure 1.4 ) for the following program:
– 1. Load AC from device 5.
– 2. Add contents of memory location 940.
– 3. Store AC to device 6.
• Assume that the next value retrieved from device 5 is 3 and
that location 940 contains a value of 2

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