Jtagppt
- 2. WHAT IS JTAG??.. Joint Test Action Group (JTAG) is the common name used for a debugging, programming, and testing interface typically found on microcontrollers, ASICs, and FPGAs. It enables all components with this interface to be tested, programmed, and/or debugged using a single connector on a PC board which can daisy chain them together. JTAG is the name of the group that defined the IEEE 1149.1 standard. This standard defines the Test Access Port (TAP) controller logic used in processors with JTAG interfaces. Required below pins - TMS -Test Mode Select TCK - Test Clock Input TDI - Test Data Input TDO - Test Data Output TRST - Test Reset (optional)
- 3. WHY JTAG??? This interface enables you to debug the hardware easily in real time (i.e. emulate). It can control directly the clock cycles provided to the micro controller through software This unique interface enables you to debug the hardware easily in real time (i.e. emulate). It can control directly the clock cycles provided to the micro controller through software. Therefore you can put hardware breakpoints in your code execution. You can start, pause, stop the execution of the code in the hardware as you want.
- 4. For simplicity, one may assume the following hardware Whenever JTAG control is set to '1', oscillator clock will be connected to CPU, else CPU will not receive clock and cannot execute any instruction. This way, you can control the execution of instructions in hardware.
- 5. HOW JTAG??... JTAG PORT TYPICALLY CONTAINS FIVE SIGNALS LIKE TDI TDO TMS TCK TRST THE DATA SHIFTED FROM THE TEST DATA IN PUT CAN BE SHIFTED TO SEVERAL DATA DESTINATIONS ONE SUCH DESTINATION IS BOUNDARY SCAN REGISTER THIS ARE THE CELLS WHICH CONNECTS THE BOUNDARY IO PINS OF THE DEVICE TEST VECTOR IS SHIFTED INTO THE BOUNDARY SCAN REGISTER DATA IS ALSO SHIFTED OUT FROM THE PREVIOUS TEST VECTOR SO THAT IT CAN BE COMPAED
- 6. TAP CONTROLLER TAP is the abbreviation for the test access port it is the part of IEEE 1149.1 Standard for JTAG THE ORIGINAL MOTIVATION FOR JTAG IS BOUNDARY SCAN TEST BOUNDARY SCAN IS THE METHOD FOR GAINING CONTROL FOR THE IO PINS The TAP controller is a finite state machine with a state diagram containing 16 states IT CONSISTS OF THREE BLOCKS 1) RESET AND RUN TEST BLOCK 2) INSTRUCTION REGISTER BLOCK 3) DATA REGISTER BLOCK
- 7. Test logic
- 12. EXTEST
- 14. INTEST