This document describes the VLSI implementation of a 4x4 MIMO-OFDM transceiver for 802.11n systems using a Spartan 6 FPGA. The transceiver uses OFDM modulation with 64-bit FFT and 1/2 rate encoding. It was designed and tested on a Diligent Atlys FPGA board with a wired channel. Performance was analyzed by measuring BER and data rate with varying SNR. Data rates up to 216 Mbps were achieved with 16QAM modulation. The design was implemented and tested using Matlab Simulink, Xilinx tools, and hardware co-simulation between Simulink and the FPGA board.