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- 1. Lecture 20: Introduction to semiconductor manufacturing Contents 1 Introduction 1 2 Integrated circuits 5 3 Device miniaturization 7 4 Challenges in IC manufacturing 11 5 IC manufacturing stages 17 1 Introduction There are a wide variety of electronic devices starting with the simple pn junction diodes, transistors, and extending into opto-electronic devices like LEDs, lasers, and solar cells. These are made from a variety of semiconduc- tor materials though silicon is the dominant material in the micro electronics industry. Other semiconductors are used, especially for optical devices, since silicon is an indirect band gap material. How these devices are manufactured and assembled to form useful devices, like computers, tablets, cell phones, and a host of other microelectronic devices is a critical part of the industry. This is especially important, since, with increased miniaturization, devices are becoming smaller and have greater functionality. Other form factors like battery life, operating power, heat generation and dissipation, also become critical, especially for mobile computing. Understanding the various steps behind fabrication of these devices is important to understand the challenges facing the semiconductor industry. The first electronic device invented was the vacuum tube, by Lee Deforest in 1906. This was the triode, called audion, and the schematic of the device 1
- 2. MM5017: Electronic materials, devices, and fabrication Figure 1: Schematic of the vacuum tube (a) triode and (b) diode. Sources http://en.wikipedia.org/wiki/Triode and http://en.wikipedia.org/wiki/Diode is shown in figure 1. Before the invention of the triode, the two terminal vacuum tube diode was postulated by Thomas Edison. The schematic of the diode is shown in figure 1. In a diode, the central cathode is heated to give electrons, a process called thermionic emission. The electrons that are generated, are accelerated to the anode and produce current. Current in the reverse direction, from an- ode to cathode, is not possible due to the biasing of the device. The triode improves upon this arrangement by using a third electrode, grid, which can independently control the current from the cathode to the anode. This en- ables the vacuum tube to perform two functions, switching and amplification (forerunner to the modern solid state transistors). The drawbacks of vacuum tubes are that they are huge and bulky. They are also not energy efficient since the glass tubes can lose vacuum and also consume a lot of power. The invention of the vacuum tube started the modern electronics indus- try. It made possible commercial devices like the radio and television. The world’s first electronic computer, ENIAC, was also made using vacuum tubes. ENIAC expands as Electronic N umeric I ntegrator And Calculator. It was first demonstrated in the Moore school of Pennsylvania in 1947. The ENIAC was a huge computer compared to modern systems, as seen in figure 2. Some of its statistics are shown in table 1. It was a massive machine occupying a large area of 1500 sq feet, with around 18000 vacuum tubes. It also con- 2
- 3. MM5017: Electronic materials, devices, and fabrication Figure 2: Two programmers operating the ENIAC. Typical statistics of the computer are listed in table 1. Source http://en.wikipedia.org/wiki/ENIAC Table 1: Some typical statistics of the ENIAC. Compared to the modern computer, it was a massive machine. SourceMicrochip fabrication - Peter van Zant. Size, ft 30 × 50 Weight, tons 30 Vacuum tubes, nos. 18,000 Resistors, nos 70,000 Capacitors, nos 10,000 Switches, nos 6000 Power requirement, W 150,000 Cost (in 1940) $ 400,000 3
- 4. MM5017: Electronic materials, devices, and fabrication Figure 3: Schematic of the first transistor developed in Bell labs. Adapted from Microchip fabrication - Peter van Zant. sumed a large amount of power and consequently generated a lot of heat. This made it highly unreliable with the longest operating period, without any vacuum tube failure, of 5 days (around 116 hours). The large size and poor performance of the ENIAC was due to the presence of vacuum tubes, which had to individually wired to achieve the desired performance. For any size reduction the triode size had to be reduced. This was made possible by the development of the modern solid state transistor, which started the revolution in micro electronics. The first solid state based triode i.e. the transistor was invented in Bell Labs in 1947. It was invented by John Bardeen, William Schokley, and Walter Brattain. The device was an electrical amplifier based on germanium, shown in figure 3. The device functioned similar to the vacuum tube triode, but was smaller, lighter, and had a much lower power requirement. A replica of the first transistor is shown in figure 4. The inventors of the solid state transistor won the Nobel prize in Physics for their work in 1956. John Bardeen then moved to University of Illinois at Urbana-Champaign where he won a sec- ond Nobel prize in Physics in 1972 for his work with Leon Cooper and John Schrieffer on a theory of superconductivity (BCS theory). Thus, he became the only person to win two Nobel prizes in Physics. The invention of the transistor started the era of solid state devices. Discrete electrical components like transistors, diodes, capacitors, and resistors can be fabricated and then joined to form the required device. While these were still smaller than vacuum tube devices, true miniaturization could only be achieved by integrating the various devices in one wafer. 4
- 5. MM5017: Electronic materials, devices, and fabrication Figure 4: Replica of the first transistor from Bell Labs. Source http://en.wikipedia.org/wiki/History of the transistor 2 Integrated circuits The first attempt in fabricating integrated circuits (ICs) was made by Jack Kilby from Texas Instruments. In 1959, he integrated transistors, diodes, and capacitors (a total of 5 components) on a single wafer of Ge. Resistors were formed by using the natural resistivity of Ge and the device were connected by external wiring. A schematic of Kilby circuit is shown in figure 5 and a picture of the original Kilby circuit is shown in figure 6. A modification to the Kilby IC was made by Robert Noyce, working in Fairchild Camera. This was based on an earlier design of a solid state device by Jean Horni, also working at Fairchild Camera, that was made using Si. A top down picture of the transistor is shown in figure 7. The advantage of using Si is that it naturally forms an oxide layer, which can help in getting a planar profile. The Horni transistor design also had evaporated aluminum as electrical contacts so that external wiring was not required. Robert Noyce was then able to fabricate the individual devices on a single wafer of Si to form the first monolith IC. The design of the Noyce IC is shown in figure 8. A monolith integrated circuit is defined as a set of electronic circuits that are fabricated on a single chip. Usually, silicon is the material of choice for the chip, but not always. For optoelectronic devices, GaAs is mainly used, as it is a direct band gap semiconductor and can be used as the substrate for growing other materials on top. The advantage of integrating the circuits on 5
- 6. MM5017: Electronic materials, devices, and fabrication Figure 5: The design of the Jack Kilby IC. Except for the metal wires, the rest of the IC was fabricated on a single wafer of Ge. Adapted from Microchip fabrication - Peter van Zant. Figure 6: Picture of the first IC. Source http://en.wikipedia.org/wiki/Jack Kilby 6
- 7. MM5017: Electronic materials, devices, and fabrication Figure 7: The Horni transistor made using Si with evaporated metal lines for electrical contact. Adapted from Microchip fabrication - Peter van Zant. a single chip is that it is much smaller than joining discrete devices. Also, the small distance that the carriers have to travel from one component to the other increases the speed of the device and reduces electrical losses (less power consumption). Initial ICs that were introduced in 1960s had only a few components but over time the number of components (usually measured as the number of transistors) have rapidly increased and correspondingly the individual transistor size has also reduced. There are essentially two kinds of improvements 1. Process - this refers to fabrication of devices and structures in smaller dimensions. In the simplest form, the original structure is not modified but only the individual components are scaled down. 2. Structure - this refers to newer device designs for greater performance. The new design makes use of the reduced size that allows to pack more components in the same area. 3 Device miniaturization Integrated circuits are characterized by the size of the individual device com- ponents and the density (number per unit area) of components. The feature size for a IC refers to the smallest dimensions in the device. Typical devices now have dimensions of tens of nm. This can be compared to the original device where dimensions were of the order of µm. This reduction in size correlates with a large increase in number of components. In 1965, Gordon Moore (one of the founders of Intel, the other two being Robert Noyce and 7
- 8. MM5017: Electronic materials, devices, and fabrication Figure 8: The patent application of the Robert Noyce IC showing the circuit design. A top-down and side view are included. Source http://www.computerhistory.org/semiconductor/timeline/1959-Noyce.html . 8
- 9. MM5017: Electronic materials, devices, and fabrication Figure 9: Semi-log plot of transistor count vs. manufacture year. Source http://en.wikipedia.org/wiki/Moore’s law Andrew Grove) came up with a prediction that the number of transistors in a IC will roughly double every 18 months (the original prediction was every 2 years). This prediction was called Moore’s law, though in a strict sense it was more of an observation based on earlier trends rather than a law. Moore’s law is also an example of the economics of manufacture since the doubling in transistor density is related to the costs of device fabrication. Moore’s law can be graphically represented in figure 9. This a semilog plot showing the increase in number of transistors with time. The doubling is roughly every 2 years. The data for a select few years is tabulated in 2. With the increase in number of transistors there are different levels of in- tegration that are defined. This is shown in table3. Initial devices were in the medium scale integration level. Now, device have billions of transistors and are in the ultra large scale integration level. Consider an example of Intel processor history, shown in table 4. With time, the transistor count has increased nearly six orders of magnitude. Correspondingly, the feature size has reduced from a few µm a few tens of nm. From 2007, the feature size has further reduced from 45 m to 32 nm to 22 nm to 14 nm and then 11 nm. As of 2014, 14 nm and 11 nm are under development but there are significant 9
- 10. MM5017: Electronic materials, devices, and fabrication Table 2: Transistor count for Intel chips Year Transistor count 1978 29,000 1982 275,000 1985 1,200,000 1991 3,100,000 1993 7,500,000 1997 9,500,000 2001 55,000,000 Table 3: The different levels of integration with increasing transistor density. Taken from Microchip fabrication - Peter van Zant. Level Abbreviation No. of components per chip Small scale integration SSI 2-50 Medium scale integration MSI 50-5000 Large scale integration LSI 5000-100,000 Very large scale integration VLSI 100,000-1,000,000 Ultra large scale integration ULSI ¿ 1,000,000 Table 4: Summary of select Intel ICs Chipset Year Clock speed No. of Transistors Technology 4004 1971 108 kHz 2300 10 µm 8008 1972 500-800 kHz 3500 10 µm 8086 1978 5 MHz 3 ×104 3 µm 286 1982 6 MHz 105 1.5 µm 486 1989 25 MHz 106 1 µm Pentium 1993 66 MHz 3 ×106 0.8 µm Pentium IV 2000 1.5 GHz 4 ×107 0.18 µm Quad core 2006 2.66 GHz 6 ×107 65 nm Xeon 2007 > 3 GHz 8 ×107 45 nm 10
- 11. MM5017: Electronic materials, devices, and fabrication Figure 10: Increasing size of the underlying wafers with device scaling. The higher size offsets the manufacturing cost since more number of ICs can be manufactured in a larger wafer. Adapted from Microchip fabrication - Peter van Zant. technological challenges with further shrinking of device dimensions. Along with the decreasing feature size and the increasing device complexity, the size of the underlying wafers have also increased. This is shown in figure 10. Starting from 50 mm wafers in 1970, wafer sizes have increased to 300 mm in 2000. 300 mm wafers are currently in use in the semiconductor in- dustry, though the transition to the next size of 450 mm has already started. The transition is supposed to take a few years and the first devices are ex- pected to be ready by 2018. The reason for increasing wafer size is to reduce overall fabrication cost. With increase in device complexity, the manufac- turing costs per chip increase. To offset this increased cost, more number of chips need to be manufactured. This can be done by increasing the wafer size. 4 Challenges in IC manufacturing One of the challenges in IC manufacturing is the fact that with reduction in feature size, size and density of defects becomes critical. Typical dust particles have a size of 1 µm. If the feature size is of the order of 10 mum, like in the 1970s, then a dust particle might not affect device performance critically. On the other hand, for a feature size of 100 nm (starting from 11
- 12. MM5017: Electronic materials, devices, and fabrication Figure 11: A two level interconnect scheme showing the metal layers and the interlayer dielectric. The earliest ICs had a two-level interconnect scheme while current ICs have up to 11 metal levels. Adapted from Microchip fabri- cation - Peter van Zant. 2000s, see table 4) the dust particle can cause shorting of the circuits and potentially kill the device. So with decreasing feature size, both the defect density and the maximum permissible defect size should also reduce making cleanliness very important for IC manufacturing. Typical IC manufacturing is done in clean rooms with low level of environmental pollutants. There are different classifications based on the maximum size of the dust particles and also their density. With decreasing feature size there is also increased levels of complexity in connecting the individual device components. This is because more number of components need to be connected while at the same time they are more closely spaced. Connection also have to be made to the external circuits. This is done by having multiple levels of wiring and interconnections. This is shown in figure 11. With decreasing device dimensions, the number of interconnection levels have also increased. The current 22 nm technology chips have 11 levels of interconnects, as shown in figure 12. Decreasing device dimensions also leads to materials challenges. Earlier, dielectrics used for MOSFETs were simple silicon oxides. These can be nat- urally grown on Si, which is one of the reasons for switching from Ge to Si. But one of the issues of having a SiO2 layer as dielectric is that with shrinking of the dimensions (thickness) while the capacitance of the dielec- tric decreases, the leakage current (due to quantum tunneling through the thin oxide layer) increases. Leakage current can be offset by having a thicker oxide but that presents growth challenges for smaller layers and also lowers the capacitance. So to maintain the high capacitance, while having a com- 12
- 13. MM5017: Electronic materials, devices, and fabrication Figure 12: Cross section SEM of 22 nm Tri- gate chips showing the metal interconnects.Source http://electroiq.com/chipworks real chips blog/2012/12/11/intel-details- 22nm-trigate-soc-process-at-iedm/ 13
- 14. MM5017: Electronic materials, devices, and fabrication Figure 13: Planar transistor showing the source, drain, and gate. There is a also the dielectric layer and there is only one interface between the semicon- ductor and the gate. Source http://www.anandtech.com/show/4313/intel- announces-first-22nm-3d-trigate-transistors-shipping-in-2h-2011 parable thick dielectric, the material can be changed from SiO2 to a high k-dielectric. Typically, Hafnium oxide based materials are used, but their compatibility with the fabrication process has to be optimized. This leads to increased complexity in manufacturing. Another example of increasing device complexity is the switch from linear two dimensional transistors into three dimensional transistors. The Intel 22 nm chip has the three dimensional transistor or tri-gate architecture. A traditional planar transistor is shown in figure 13. The gate has a single in- terface with the semiconductor and this determines the channel width. The three dimensional architecture is shown in figure 14. In this architecture, the gate wraps around the Si fin protruding from the surface. The fins form the source and drain and there are three interfaces with the gate for determining the channel, as shown in figure 15. This increases the overall surface area of the channel. The fin width determines the channel width. This also reduces the leakage current and power consumption. 14
- 15. MM5017: Electronic materials, devices, and fabrication Figure 14: Trigate transistor. Fins extend from the silicon surface and the gate wraps around the fins, separated by the dielectric. The fins have both source and drain. Now, there are three interfaces between the gate and semi- conductor. Source http://www.anandtech.com/show/4313/intel-announces- first-22nm-3d-trigate-transistors-shipping-in-2h-2011 15
- 16. MM5017: Electronic materials, devices, and fabrication Figure 15: Trigate transistor showing current flowing from source to drain. Source http://www.anandtech.com/show/4313/intel-announces-first- 22nm-3d-trigate-transistors-shipping-in-2h-2011 16
- 17. MM5017: Electronic materials, devices, and fabrication Figure 16: Various steps in IC manufacture. (a) Conversion of sand to polycrystalline Si (b) Poly Si to single crystal wafers. (c) IC fabrication (d) Packaging for final use (e) Electrical testing. Adapted from Microchip fabrication - Peter van Zant. 5 IC manufacturing stages IC manufacturing can be broadly divided into five stages. (a) Materials preparation - conversion of sand to polycrystalline silicon (b) Crystal growth and wafer preparation - converting the poly Si into single crystal wafers for use in the fab. This also involves removal of impurities and doping the silicon, if needed. (c) Wafer fab and sort - IC manufacturing and sorting the good chips in the fab (d) Packaging (e) Final electrical testing The various steps are summarized in figure 16. The first two steps are outside the fab. The single crystal wafers are then supplied to the fab where the IC processing happens. This is the most important step in the fabrication process. Sort refers to the electrical testing of the chips after processing, to separate the good from the bad. After sort, the wafers go out of the fab for packaging and final testing. 17